TW465031B - Copper manufacture process for semiconductor - Google Patents

Abstract

This invention provides a copper manufacture process for semiconductor industry. Firstly, a semiconductor substrate with complete front-end integrated circuit process is provided. Damascene trench is then formed on the substrate and copper film is electroplated on the substrate. An annealing treatment is carried out in vacuum state with a pressure less then 10<SP>-5</SP> torr. Finally, chemical mechanical polishing process is performed on the copper film to obtain copper wiring with low via resistance.

Description

V. Description of the invention (1) Field of the invention: The present invention relates to a method for copper process, and more particularly to a method for manufacturing copper wire with low dielectric resistance. Background of the Invention: In order to pursue faster operating speed, rate, and greater accumulation density, research units and manufacturers of integrated circuits have endeavored to design and manufacture components with smaller critical dimensions (CD). According to experiments, when the process of integrated circuits enters the technical field of 0.18 microns or even 0.13 microns, the key factors affecting the operating speed of components have been switched from the width of the gate to the resistance-capacitance hysteresis of the metal interconnection (metal interconnection). RC delay) effect. The resistance of the interlayer of a wire is inversely proportional to its cross-sectional area. As the integrated density of integrated circuits increases, the line width and thickness of the metal interconnects decrease, so the interlayer resistance increases. Or, as the integration density of the integrated circuit is increased, the line pitch of the metal interconnects is also reduced, resulting in an increased capacitance between the wires. Therefore, when the process of integrated circuits enters the deep sub-micron field, the resistance-capacitance hysteresis of the metal interconnects is greatly improved ', which also affects the operation rate and access rate of integrated circuits. In order to improve the integration density of integrated circuits, under the condition that the line width and line spacing should not be increased, it is the best choice to change the material of the metal interconnects and interlayer dielectric layers. In terms of metal interconnects, the metal material is changed from the original aluminum-silicon-copper alloy or aluminum-copper alloy to copper metal. In addition to the characteristics of low resistance, it also has good resistance to electron migration and good stress resistance. Raise yuan

Page 4650; 5. Description of the invention (2) '------ In addition to the operating speed of the piece, at the same time, you can choose the bucket-material to face, and enter Nf to plug the reliability of the piece; on the other side s 3; 丨 electricity must choose a low dielectric constant (Dielectric octant) material to replace the original dioxide, in order to reduce the surface capacitance between the f lines in the metal. The dielectric constant of the dioxide is about 3.9. Because a dielectric with a dielectric constant less than 3 · 9 must be selected as the interlayer dielectric layer, the effect of reducing the resistance-capacitance hysteresis can be achieved, for example, fluorine-doped Silicon dioxide (SiOF), organic spin-on glass (HSQ), etc. Another effective material with low dielectric constant is black diamond (Mack diam〇nd), which is formed by Uethyls Uane). Its composition is 20% silicon, 30% oxygen, 9% carbon, and 36% hydrogen. , And other elements. Because about 36% of the volume of black diamonds is holes ’, its dielectric constant is only about 2.9, which is a low-dielectric constant material with great potential. 〃 In the technology of copper process, because copper metal cannot be etched with gas like aluminum alloy ’, the industry has developed a damas cene trench process method. For the process technology of inlaid trenches, please refer to "Method for manufacturing a low dielectric constant inter-level integrated circuit structure11" disclosed by Motoro 1a Company Boeck; Bruce A 11 en et al. In US Patent No. 5880 0 18. Please refer to FIGS. 1A to 1C. First, a first silicon nitride layer 11, a low-k dielectric layer 12, and a second silicon nitride layer are successively formed on a semiconductor substrate 10 that has completed the previous process. The layer 13 and the second low-k dielectric layer 14 are formed by two successive lithography and etching techniques as shown in FIG. A. The opening 15 is an "embedded trench". Among them, the deposition of atmospheric sand layers 11 and 13 is based on SiH4 and NH3 as reaction gases and enhanced by plasma.

Page 5 4650 3 V. Description of the invention (3) Chemical vapor deposition method (PECVD) is deposited under an N2 environment to form a thin film of about 500 Angstroms. The required RF power is about 400 Watts. . The silicon nitride layer formed under normal process conditions has a compressive stress of about 1 E 9 dyne / cm 2. The deposition steps of the first low-k dielectric layer 12 and the second low-k dielectric layer 14 use N20 and methyl si lane as reaction gases, and use a plasma-enhanced chemical vapor phase. Deposition (PECVD) deposition, in which the required RF power is about 70 watts, the flow rate of N20 is about 370 sccm, the flow rate of fluorenylsilane is about 68 sccm, and the reaction time is about 60 seconds to form about 5 0 0 0 Black diamond film. Next, please refer to FIG. 1B 'a layer of copper film 16 is formed by electroplating, and then it is sent to the inside of a furnace for annealing for about 30 minutes', wherein the pressure inside the reactor is controlled in Bu 7 6 0Torr, and the temperature is controlled between 2 0 ~ 4 0 0 ° C. Finally, as shown in FIG. 1c, the copper thin film 16 is polished by using chemical mechanical polishing (CMP) to form a copper wire. With the advancement of semiconductor process technology, the manufacturing of components is becoming smaller and smaller. “Because of the copper layer I layer resistance resistance” is proportional to the dielectric constant P and the length L and inversely proportional to the cross-sectional area a. As the wires become smaller and smaller, the interlayer resistance R produced by them becomes higher and higher. As a result, the overall conductivity of the copper wires will be poor and the yield of the process will be reduced. According to the actual data, the average per 880,000 In the process of copper conductors, the failure of the process due to the excessively high interlayer resistance R accounts for about 30% to 100%. Therefore, reducing the interlayer resistance R to improve the yield of the copper process has become an issue in the semiconductor industry. Very important subject.

Page 6503: 5. Description of the invention (4) Purpose of the invention: The main purpose of the present invention is to provide a copper process method which can reduce the resistance of the interlayer to improve the yield of copper wires. The invention discloses a method for copper process. The steps include firstly providing a semiconductor substrate that has completed the previous stage of the integrated circuit, and forming a mosaic trench on the semiconductor substrate; forming a barrier layer and an electrode layer by a deposition method. And then forming a layer of copper film by electroplating; tempering in a reaction furnace for about 1 minute, wherein the pressure of the reaction furnace is controlled below 10E-5T0rr, and the temperature is between 100 ~ 200 c; CMP grinds the copper film to form a copper wire. '' During the tempering process provided by the present invention, during the tempering process, the defects of the internal grains of the copper wire are greatly improved, and the dielectric constant is reduced to reduce the dielectric resistance of the copper wire, thereby improving the impedance of the copper wire. Yield of copper process. In addition, since the time required for the tempering of the present invention is about 1 minute, compared with the conventional technology, the present invention can greatly reduce the process time to improve the production efficiency and capacity of the semiconductor. In order to allow your reviewers to have a better understanding and recognition of the purpose, features and effects of the present invention, we will explain the schematic diagram in detail with the drawings: The diagram is a cross-sectional view of a mosaic trench formed by conventional techniques; FIG. 1B is a cross-sectional view of forming a copper thin film by the conventional technique; FIG. 4 is a cross-sectional view of forming a copper wire by the CMP method of the conventional technique; FIG.

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Half of the previous stage of the integrated circuit has been completed. 5. Description of the invention (5) Figure 3A is a schematic diagram of the conductor substrate provided by the present invention: Figure 3B is a schematic diagram of forming a mosaic trench according to the present invention; Figure 3C is a diagram of the present invention Schematic diagram of barrier layer and seed layer Figure 3D is a schematic diagram of forming a copper thin film of the present invention; Figure 3E is a schematic diagram of forming a copper wire by CMP in the present invention. Layer 1 gasification stone layer 1 5 to opening 1 7 to copper wire 3 1 to first silicon nitride layer 33 to second nitride stone layer 3 5 to inlaid trench 37 to seed layer 3 9 to steel wire 10 to semiconductor Substrate 12 to first low dielectric constant dielectric layer 14 to second low dielectric constant dielectric layer 16 to copper film 30 to semiconductor substrate 32 to first low dielectric constant dielectric layer 34 to second low dielectric constant The constant dielectric layer 36 to the barrier layer 3 8 to the copper thin film are described in detail: Please refer to FIG. 2 'It is a flowchart of the copper process method of the present invention' The process method of the present invention includes: first providing a completed product Semiconductor substrate (21) in the previous stage of the bulk circuit; A dacene trench (22) is formed on the body substrate; a barrier layer and a seed layer (23) are formed by a deposition method; and a copper film (24) is formed by an electroplating method (24). ); Sent to the reaction furnace for tempering for 1 minute, where the pressure inside the reaction furnace is controlled at

Page 8 465031 V. Description of the invention (6) Below 10E-5 Torr, the temperature is controlled between 100 ~ 20 (rc (25); finally, chemical mechanical polishing method (Cheffiical Mechanical

Pol ishing 'CMP) polishes the copper film to form a copper wire (26). Please refer to FIG. 3A, which is a semiconductor substrate 30 which has completed the previous stage of the integrated circuit provided in step (21) of the present invention, and a first silicon nitride layer is sequentially formed on the surface of the semiconductor substrate 30 3 1. The first low-k dielectric layer 32, the second silicon nitride layer 33, and the second low-k dielectric layer 34, as shown in FIG. 3B, are steps of the present invention (22) Schematic diagram of the inlaid trench 35 formed on the semiconductor substrate 'wherein the inlaid trench 35 is formed by two successive lithography and silver engraving techniques, please refer to FIG. 3C, which is a step of the present invention (2 3) 'A schematic diagram of forming a barrier layer 36 and a seed layer 36 on the surface of the semiconductor substrate 30, wherein the barrier layer 36 is used to prevent the copper thin film 38 from penetrating into the silicon nitride layer, and the material is a nitride button (TaN) The seed layer 37 is used as a key electrode so that the copper film 38 can be deposited smoothly (see FIG. 3D), and FIG. 3E is a schematic diagram of the copper film 38 after the CMP polishing to form a copper wire 39 . The characteristics of the present invention are mainly controlled by the tempering process technology provided in step (2 5) to control the pressure inside the reaction furnace below 10E-5 Torr, and at the same time control the temperature between 100 ~ 20 0 ° C and Tempering is continued for about i minutes to improve the evolution of grain defects inside the copper wire. Therefore, the present invention can reduce the damage (such as wire breakage) of the copper wire in the copper dielectric window (Cu via) due to thermal stress. According to the actual test results, it can be known that the steel process method provided by the present invention can be used to make every 88,000 copper conductors because

4 6 · 5 Ο 31 V. Description of the invention (7) The defect of the via window R (Cu via resistance) is reduced from 30-100% to 0 ~ 2%, and the process failure caused by copper is greatly reduced. Improvement, in addition, 'the yield rate of the copper process equation of the present invention is obtained by performing the tempering process, compared with the conventional technology, it must = 1 minute of the tempering process is required.' The present invention can greatly reduce the overall production capacity of 30 minutes for semiconductor recycling. And productivity. "Time to improve the implementation of this method." Any familiarity with this technology should belong to the patent application scope of the present invention. Of course, the above is only a copper example of the present invention. It is not intended to limit the present invention. The scope of implementation The scope of modifications made by the artist without departing from the spirit of the invention, so the scope of protection of the invention should be based on the following.

Brief description of the drawing Brief description of the drawing: Figure 1A is a cross-sectional view of forming a mosaic trench using conventional techniques; Figure 1B is a cross-sectional view of forming a copper thin film using conventional techniques; Figure 1C is a conventional technique using CMP Figure 2 is a cross-sectional view of a copper wire method; Figure 2 is a flowchart of the copper process method of the present invention; Figure 3A is a schematic diagram of a semiconductor substrate that has completed the pre-process of a integrated circuit provided in the present invention, and Figure 3B is a Schematic diagram of the formation of inlaid trenches according to the invention; Fig. 3C is a schematic diagram of the formation of a barrier layer and a seed layer according to the invention; Fig. 3D is a schematic diagram of the formation of a copper thin film according to the invention; schematic diagram.

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Claims (1)

46 50 31 VI. Applying for a patent Fan Yuan applies for a patent scope 1. — A method of copper process, its process step U) provides a completed integrated circuit dagger. (B) a semiconductor substrate fabricated on the above semiconductor substrate (C) formed by electroplating—a layer of steel film; alder, (d) tempering the above-mentioned copper film by CMP at an atmospheric pressure of less than 10E_5 torr; 2, as described in the patent application The second item of item 1 forms a copper wire. The surface of the semiconductor substrate is in accordance with the copper I-process method, wherein step U) the dielectric constant dielectric layer, the second nitride is the first, and the nitrogen is the low dielectric layer. The copper process method described in item 1 of the first low-dielectric-constant range, wherein step 如 4 is to form a mosaic trench as two successive lithography and etching techniques. The .σ application applies to the copper process method described in item 1 of the scope, wherein step (c) 5 is a step of depositing a barrier layer and a sub-layer prior to the copper thin bond wire. Wherein step (c) is the copper process method described in step (c), wherein step (d) is the copper process method of lambda in the 4th item of the scope of ΐΐίΐί, where step s (c) ^ s 糸 can prevent the infiltration and disorder of the copper film Among the sand. .. The copper process method described in item 4 of the patent application ^ ^ 7 2 The material of the hafnium resist layer is a nitride group. . ° Application of the copper process method described in item 4 of the patent scope 8 such as: layer system as the electroplating electrode °.: Application of the copper process method described in the first scope of the patent application, wherein step (d is performed by a reaction furnace The internal temperature of the fire is controlled between 1000 and 2000C. 12 I 465031 Page 13