TW439257B - Cell for use in multi-voltage design environment - Google Patents

Abstract

The application specified integrated circuit (ASIC) design that uses multiple supply voltages has been proved to effectively reduce power consumption. The present invention proposes a new type layout manner of cell used in ASIC design in order to effectively use multiple-voltage design. Each cell has multi power source lines, which are used to individually provide different supply voltage. In addition, the cells of different supply voltages can be placed arbitrarily and adjacently when the cells are placed, such that it is not necessary to consider the supply voltage and replace the cells. Therefore, the placement and routing of cell can be executed by using the nowadays computer aided design software so as to achieve the purposes of simplifying design flow, shortening design time and saving power.

Description

Case No. 87119131 Complementary V. Description of the Invention (1) The present invention proposes a new method to deal with the physical level design. This new method uses a different cell layout. Each cell has multiple power lines, each providing a different supply voltage, but only one power line is connected to the cell's internal circuit. This new type of cell can be processed by current p & K tools. Since there is no need to reposition the cells due to consideration of the supply voltage, the layout can be completed most efficiently. We take the I SC AS, 85 test circuit as an example, each cell provides two kinds of supply voltages, and the layout is wound with a double-layer and three-layer metal system. The results show the great efficiency of the new cell Much better than other layout architectures. The scope of application of the present invention includes: (1) Standard cell library. (2) Low-power ASIC design. With the rapid development of highly complex very large-scale integrated circuits (VLSI) and the large demand for portable electronic products supplied by batteries, low power consumption has become one of the main goals of IC design, and is related to operation speed and chip Design considerations for areas with equal proportions [1]. In a cell-based (cel} based) AS 1C design, the characteristics of the standard cell determine the performance of the wafer, including power consumption. Voltage is used for logic gates on the critical path, so

Page 4 Most of the power consumption of CMOS circuits is dynamic power, and this dynamic power is proportional to the square of the supply voltage (VDD), so a lower value can save the maximum power consumption. However, lowering the value of V d d will reduce the operating speed of the circuit. If the lower supply voltage is used only for logic gates on non-critical paths, and the original or higher supply is _m-umm__g _ V. Description of the invention (2) As a result, the overall circuit speed and It will not be affected, and the power consumption can be effectively reduced. Applying the above voltage supply method, the design at the behavior level (behavi 〇r level) has been adopted for variable voltage adjustment (νΉαΐ e Voltage Scaling, VVS) [2], and the design at the logic level (1 og ic} e ve i) It is used in Clustered Voltage Sealing (CVS) [3] and Extended Clustered Voltage Scaling (EC VS) [4], and both are designed using two supply voltages. In addition, a row by row layout architecture [5] was proposed to achieve a practical hierarchical design using multiple power modules. / 'In order to effectively utilize multiple supply voltage designs to achieve low power consumption, behavior, logic, and actual class design must be considered simultaneously. If current computer-aided design (CAD) tools do not support cell placement and routing using multiple supply voltage designs, the circuit using this technique must be separated into multiple different clusters and individually placed and wound. A possible layout architecture of a cluster voltage adjustment using two supply voltages is shown in Figure 1, where VDDH 12f shows a higher voltage level and VDDL 1 3 shows a lower level. Obviously, its layout efficiency is not good, because its chip area and winding length are much larger than the original layout. The layout architecture of sequential processing is shown in Figure 2. It places the cell 11 that Shanru and VDDL supply power into different cell columns 21 and 22, and places them in the same block as the ι line. A special connection cell (v 丨 A ce u) must be placed at each end of each Γ fine 0w π column to determine the supply voltage of the column as VDDH or VDDL. Follow the process of sequential processing =; First, place the cell elements in the circuit without considering the voltage form, that is, amended by --ο 9 2 5 7 871 No. 87119131, which is the day of the month _ V. Description of the invention ( 3) The cells supplied by VDDH and VDDL are mixed in the same cell row. In the second step, the cells supplied by VDDH and VDDL are rearranged to different columns, so the original layout is compared.) Usually after the winding is completed, Layout 5 is the tool software for applying the layout of the sequential processing. Column processing This case is a kind of multi-electricity @ which uses-the actual hierarchical design of a kind of cell element 0 its characteristics are on line 0 as described above where the cell-a voltage supply environment 0 as described above the two cells in the cell element line The power line is composed of the first layer as described above. The two power lines in the cell line can be divided into three types: 1. The line is separated by the first layer of metal 2. The line is separated by the first layer of metal and the third layer is formed by the first layer of metal It is the same as the layout line of the standard cell in which the three supply voltages of the cell are as described above, and the novel thin line proposed by the present invention is a new cell circuit. Construct

PD1557 fix .ptc will be changed. Compared with the non-reposition, the area and winding length will increase. "Re-architecture" must be re-developed. The layout efficiency of the cell arrangement is still insufficient. The main layout method of the cell in the design environment is to handle multiple voltages. The cell has a plurality of power elements, including two power lines, and is applied to the manufacturing process through two layers of metal. Made up. Manufactured through a three-layer metal manufacturing process, the method is composed of: and arranged in parallel. It consists of two layers of metal stacked. It consists of two layers of metal stacked. The element system contains three power cords, which are used when there is only one power cord and one ground. The cell has multiple power cords and one ground. With ^ power cord

Hi Page 6 _Case No. 871J_g_131 __ One As of March ____ V. Cells of Invention Description (4) Each of its Bollinger functions needs to develop N types of cells. The cells of TYPE 1 are provided with power via the VDDi power line, and the cells of TYPE 2 are provided with VDD2 power lines. By analogy, the cells of T Y P N are provided via the V D DN power cord. Except for the connection of the power cord, its internal circuits are identical. In addition, in order for all cell types to be placed adjacent to each other, the pjJOS substrate end of the circuit of all cells must be connected to the highest supply voltage in the circuit (in this example, VDR). This new type of cell is derived from a standard cell, and only needs to modify the number and width of the power cords. As a result, the time and technical costs required to make this new library of cell components are quite small. The layout of the cell elements of multiple power lines can vary depending on the process. Examples are as follows: (1) Using a process with a double-layer metal Figure 4 is a schematic diagram of the layout of a process using a double-layer metal process, which contains multiple The power line 41, pin 42 (M2 pin) and ground line GND of the double-layer metal process. Figure ® (a) shows a general cell 'and Figure 翌 (b) shows a new type of cell using a double-layer metal. The new type of cell using double-layer metal uses the first layer of metal (M1) for all power and ground wires and is arranged in parallel. In order to consider the feasibility when winding, the input and output signal pins (p i π) use a second layer of metal (M2), so that M2 can cross M1 vertically when winding. Compared with the design of a single voltage source, the design of multiple voltages can reduce the overall power consumption. Under the design of multiple voltages, the current that was originally supplied by a single electric dust VDD is shared by all power lines. Therefore, the width of the power line and ground line of the new cell can be reduced. Since the amount of current flowing through the power line that provides a lower voltage is smaller, its width can be further reduced. PD1557 amended due to ΪΒΗΠ ^ .. pic page 7-case number 87119131 彳 P year March; ^ Japanese article five, description of the invention (5 ^ · The width of the power line and ground line of this' new type cell cell can be Adjust according to the application of the circuit. Furthermore, the design with two or three voltages is more feasible, so the increase of the cell area due to the increase in the number of power lines is not too large. One uses two supply voltages (N = 2) The two-input NAND gate circuit diagram and layout example are shown in Figure 5 and Figure 6, the two input voltages are VD]) H and VDDL 'The two cell elements are η-type and L-type, respectively. The technology used is 0.6 micro- (um) CMOS single-layer multi-silicon double-layer metal (SPDM) process. Taking the layout of Figure 5 as an example, the original cell height was 30 μm, and the power line and ground line were 4um each. In the new type of cell, the width of VDDH and GND is designed to be 3um ′, and the width of VDDL is reduced to 2 · Oum. Therefore, the height of the new type of cell is 30.8um ′. Compared with the original cell, the area excess is only 2.7%. These two types of cells can be placed next to each other during P & R, and VDDH and VDDL can be conducted through the cells in the same row. Due to its arbitrarily adjacent nature, winding can be performed immediately after the cell is placed. Therefore, the current CAD software can effectively automate the P & R program. Figure 7 shows a new cell layout architecture using two supply voltages. The gray elements in the figure represent L-type cells, while the white elements represent Η-type cells. (2) Using a process with three layers of metal. If three layers of metal are allowed in the process, the new cell can use the single-layer parallel power cord described in (1), and the power cord layout can also be stacked to save area. . FIG. 8 is a schematic diagram of a layout using a three-layer metal process, which includes a plurality of power lines 8 1 and a plurality of pins 82. Figure 8 (a) is a general cell, Figure 8 (b) is a new type of cell using M1 or M2 as the power line, and Figure 8 (c) is M1 or M3 (a third layer of gold) as the power line

PD1557 Amendment. Ptc Page 8 Wu 43925 7 Amendment No. 87119131 V. Description of the invention (6) Genus) a new type of cell. Cells using three layers of metal, each-button is a stack of two layers of metal. Take Figure 8 (b) as an example. Each group of thunder source lines are stacked by M1 and M2, M2 is stacked above M1, and M3 is the main power layer. In addition, the width of the power line 81 and the ground line GND can still be as large as The aforementioned shrinkage is reduced. If the layout of Figure 5 is made of three layers of metal, the X-plane can be smaller than that of a typical cell with a Zhuoyi power cord. If you design using the aforementioned very 6 micron CMOS process, the cell size shown in Figure 9 can be as small as 6.7? ^ 'Continued * in terms of performance comparison' In order to evaluate the layout efficiency using different layout architectures, The original circuit and the processed low-power circuit with dual voltage sources are respectively placed in DLM (double-layer metal P & R tool) and TLM (three-layer metal P & R tool) software used in the industry. Winding. Table 1 shows the layout area and total winding length using DLM, and Table 2 uses the data of tlM " The new cell forms in both tables use the new cells shown in Figure 5. Table I

PD1557 correction. PTC test area total winding length circuit Α〇Γίϊ (μΓη2) Απ% Anew% L〇rS (mm) Lrr% Lnew% C17 48x78 -3.4% 0.7% 0.6 -6.5% 3.1% C432 224x281 74.1% 7.9% 18.5 119.9% 0.7% C499 359x425 61.0% 8.6% 47.1 94.9% 13.5% C880 314x395 98.7% 10.8% 40.4 133.0% 11.0% C1355 351x442 38.6% 9.0% 47.3 57.3% 6.4% Cl 908 343x422 98.1% 10.4% 46.6 123.6% 9.2% C2670 431x524 104.7% 9.4% 79.6 134.1% 7.0% C3540 375x399 125.9% 6.3% J30.9 192.4% 5.5% C5315 697x909 236.6% 5.8% 231.1 239.9% 1.2% C7552 790x1002 114.8% 6.8% 301.9 172.9% 2.4% Mean 94.9% II- 1 7.6% 126.2% 6.0% A 仃 / ΐ)-(A | j- A〇 ″ g) / Aorg, Anew%-(Anew- A〇r | j) 'A〇rg,

Lrr%-(Lrr-Lor (1) / Loni ， Lnew% = (Lrnew-Lorfl) / LorK ”, page 9 i43 9 Π 5 years and months y amendments __ case number 87119131 V. Description of the invention (7) Table Second test area total winding length circuit Α0ΓΒ (μηι2) Arr% △ new% L〇rS (mm) U% Lnew% C17 50x71 -8.0% -6.9% 0.5 -6.2% -3.6% C432 223x204 7.0% 4.9% 12.9 48.1 % 16.1% C499 356x273 8.1% 3.4% 31.6 53.0% 0.7% C880 308x274 21.1% 8.4% 29.6 75.1% 9.9% C1355 353x270 13.5% 5.3% 33.1 48.2% 2.5% C1908 336x278 28.0% 10.8% 31.7 86.6% 13,1% C2670 452x312 46.4% 10.8% 59.4 106.1% 7.4% C3540 539x423 71.9% 16.3% 92.8 165.3% 11.3% C5315 699x513 111.1% 14.4% 163.8 218.0% 22.9% C7552 723x573 76.9% 17.7% 197.7 146.0% 8.5% Average 37.6% 8.5% 94 , 0% " " " 8 ^ 9% The circuits in the above table are ISCAS, 85 of the test circuits (benchmark circuits) »The original test circuit is composed of cells with a single power line, and its layout area and total winding The length of the line is expressed by Aorg and Lorg respectively. For low-power circuits with dual voltage sources, the layout area and the total winding length are respectively Represented by Anew and L new. In addition, in order to compare the layout efficiency, low-power circuits with dual voltage sources also use the cells of a single power line to produce a sequential layout structure, and the layout area and the total winding length are respectively Comparing Arr with 0 and Aorg, the average area of Anew is excessive, using dlm is 7.6%, using TLM is 8.5%. And the average area of Arf is excessive, using dlm is 94.9%, using Ding is "." On the other hand, compared with Lorg, the average winding length of Lnew is excessive, using the elbow is ", using Ding is 8_ 9 / ..., and the average winding length of Lrr is excessive, using DLM is 126, The use of TLM is 94%. This data shows that the layout structure of sequential processing will make the layout

PD1557 correction. Ptc page 10 '^ —- ΜΆ 87119131 βρ year θ month 1 correction V. Description of the invention (8) a = Area and winding length increase significantly. If the cell layout used is changed to the form of Figure 9 ', the total layout area will be smaller and the total winding length will be shorter.

The excess of Anew and Lnew comes from the added potential converter (^ evel converter) ′ In addition, the cell itself and the winding of VDDL are also the reasons for the increase. The major excesses of Arr and Lrr come from restricted cell placement. The significantly increased winding length not only increases power consumption, but also affects operating speed. This phenomenon will worsen in more advanced processes' because the winding area and delay will dominate the chip performance. It is worth mentioning that, as mentioned earlier, the new cell design in the second table adopts the method of Figure 5. At this time, the circuit performance has shown good performance, and the layout area and total winding length are also very small. If the new cell type adopts the design method of Figure 9, the layout area and total winding length loss will be smaller, or even better than the original design, and still maintain the advantage of low power consumption. When VDDH and VDDL are set to 3 · 3V and 2.2V respectively, the average power saving of the test circuit in the table when using the dual power supply design is higher than that of the single power supply design by 31-4 ° / 〇. In summary, we can draw the following five conclusions: (1) The goal of low power can be achieved under the established speed specifications. (2) The low power characteristics of multiple voltage source designs can be effectively used. (3) There is no need to redevelop the CAD tool program for cell arrangement. (4) There is no need to add design steps, and the current CAD software can directly perform cell placement and winding, which shortens the chip design time and product time to market. (5) Compared with other multiple voltage source bureau methods1, the excess of the chip area and the total winding length can be minimized.

PD [557 Amendment.ptc Page 11_Case No. 87119131 is the date of the month__i ± ^ ___ V. Description of the invention ¢ 9) From the above, the design of this case allows us to increase the cost of the design without increasing the design cost. Quickly design and manufacture high-speed, low-power, high-performance chips. In this highly competitive semiconductor market, the invention in this case can become a very powerful production advantage. This case may be modified by any person skilled in the art, but none of them can be protected as attached to the scope of patent application. References: [1] Abdellatif Bellaouar and Mohamed I. Elmasry, " Low-power digital VLSI design, " Kluwer Academic Publishers, 1995. [2] Salil Raje and Majid Sarrafzadeh, " Variable voltage scheduling, " International Symposium on Low Power Design, pp. 9-14, 1995.

[3] Kimiyoshi Usami and Mark Horowitz, " Clustered voltage scaling technique for low-power design, " International Symposium on Low Power Design, pp. 3-8, 1 9 9 5.

[4] K. Usami et a 1., M Automated low-power technique exploiting multiple supply voltages applied to a media processor, " Proc. IEEE Custom Integrated Circuits Conf., Pp. 1 3 1-1 34, 1 997.

[5] K. Usami et a 1., " Automated low-power technique exploiting multiple supply voltages

PDI557 Amendment.ptc Page 12 _ Case No. 87119131 March 13th Amendment _ V. Description of Invention (10) applied to a media processor, " IEEE J. Solid-State Circuits, Vol. 33, no. 3, pp. 4 63-472, Mar. 1 9 98.

PD1557 correction.ptc page 13 put 439257 __ discarded 87119131 simple illustration of the year and month

The following diagrams and explanations can be used to repair the JL case. A more in-depth understanding of circle I: Layout architecture using cluster voltage adjustment (CVS) Figure 2: Layout architecture using sequential processing Figure 3: Layout of a new type of cell Circuit structure diagram 4) Ra: schematic diagram of a single single-source source using a double-layer metal process _ ^^ element layout wheel squat Figure 4C b): -AAJt-layer metal process of a new type of cell 亓. 希希. 思. a): An example of a new type of thin film using two supply voltages LMM ΆΜ1 ° Figure 5 (b) L-shaped new plastic thin film with a supply voltage opening. 1_Double-layer metal process) Figure 6 (a) LAJL_ Figure 6 (b) of two new-type shovel cells with two supply voltages: _ ^ JL Two new-type cells with two supply voltages a) "Use; g · General single power line cell cloth for layer metal process! Outline drawing 1 18 (b) For layer metal process, the power line uses M1 or the new fine AAj seat outline J 8 (C ). Schematic diagram of the layout of a new type of cell element using M1 blanket for power lines made of metal. Η-type new type cell layout layout i (three-layer gold 1 process) for supply voltage (b ..) L-type new-type cell layout layout jj (three-layer metal process) for supplying lightning pressure

PD 丨 557 correction.ptc page 14 3 9?-^

Case No. 87119131 θ month; ^ said the corrections simply explain the meaning of each code in the illustration: 11 cell element 14: ground GND 12 high voltage level of supply voltage VDDH 13 low voltage level of supply voltage VDDL 15 VDDH cluster 16: VDDL cluster 21 VDDH column 22: VDDL column 41 Power line 4 2: Pin 81 Power line 8 2: Pin PD1557 correction. Ptc page 15

Claims (1)

_ Case No. 87119131 Sixth, the scope of the patent application for more than one month B Amendment 1. A cell used in a multiple voltage design environment, which includes: a plurality of power lines to provide different supply voltages, a plurality of cells, It has the plurality of power lines; each cell and power is provided only by one of the plurality of power lines. 1 of 2 _ The cell used in a multiple voltage design environment as described in item 1 of the scope of the patent application, wherein the cell uses two supply voltages. 3 _ The cell for a multiple voltage design environment as described in item 2 of the scope of the patent application, wherein the cell provides a first voltage level and a first power line with a first voltage level and a first power line, respectively. Two voltage levels. 4. The multi-voltage design environment branch cell as described in item 3 of the scope of patent application, wherein the cell has two types. 5 ‘The cell for a multi-voltage design environment as described in item 4 of the scope of the patent application, the power of the first type of cell is provided by the first power line. 6. The cell used in the multi-voltage design environment as described in item 4 of the scope of the patent application, the power of the second type of cell is provided by the second power line 0 7. As the scope of the patent application, 5 or 6 In the cell of the multi-voltage design environment described in the item, either of the cell layouts has two power lines. 8 'As described in item 3 of the scope of the patent application, the cells of the multi-voltage design environment, the power of the first type of cell layout is provided by the' power cord, and the second power source is built in The line is only used to conduct this second voltage level. PD1557 correction.pR First _ Case No. 8711 VI. Application for Patent Scope Application = Scope 3 item for multi-voltage design environment: 2 S: —The type of cell cell layout power is provided by the second power line k ,, built-in The first power line is only used to conduct the first voltage level. 1 · The first power line and the second power line of the two types of cells, which are used in the multi-voltage design environment, as described in item 8 or 9 of the patent application scope, are adjacent to each other when they are laid out. Place and connect naturally. 11. The cell used in the multi-voltage design environment as described in item 3 of the scope of the patent application, when the layout of the cell uses a two-layer metal system, the first power line and the second power line It consists of the first layer of metal separated and arranged in parallel. 1 2 · As described in item 3 of the scope of the patent application, the cell used in the multiple voltage design environment, when the layout of the cell uses a three-layer metal process, the first power line and the second power line It consists of the first layer of metal separated and arranged in parallel. 1 3. The cell used in the multi-voltage design environment as described in item 3 of the scope of the patent application, when the fabric of the cell uses a three-layer metal process, the first power cord and the second power supply The line is composed of a first metal layer and a second metal layer. 1 4 'As described in item 3 of the scope of the patent application, the cell used in the multi-voltage design environment, when the shoulder of the cell uses a three-layer metal process, the first power cord and the second The power line is composed of a first metal layer and a third metal layer. 15. For multi-voltage design environment as described in item 1 of the scope of patent application ^ 43925 7 _ Case No. 87119131d ^ 々 Day Amendment _ Sixth, the scope of patent application Cells, in which the cell element uses three supply voltages. 16. The cell for a multiple voltage design environment as described in item 15 of the scope of the patent application, wherein the cell is provided with three power lines with three different levels of supply voltages. 1 7. The cell for a multiple voltage design environment as described in item 15 of the scope of the patent application, wherein the cell has three types. PD1557 correction.ptc 苐 page 18