CN102591997B - Layout and schematic diagram consistency comparison method for multi-voltage chip design - Google Patents
Layout and schematic diagram consistency comparison method for multi-voltage chip design Download PDFInfo
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- CN102591997B CN102591997B CN201110001008.6A CN201110001008A CN102591997B CN 102591997 B CN102591997 B CN 102591997B CN 201110001008 A CN201110001008 A CN 201110001008A CN 102591997 B CN102591997 B CN 102591997B
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Abstract
The invention discloses a layout and schematic diagram consistency comparison method for multi-voltage chip design, which comprises the steps of: amending a script file of a layout netlist and executing the script file to amend the layout netlist. The procedure of amending the script file comprises the steps of: finding the power supply port titles and subject power supply domains of functional modules of a chip; respectively adding modules corresponding to the power supply port titles and power supply ports of standard units in the layout netlist; adding the power supply connecting line titles in the layout netlist according to the subject power supply domains of the functional modules; and adding the power supply connecting line titles of all functional modules in the top layer of the layout netlist. The method of the invention has the advantages of improving the check efficiency and reliability, reducing the check risk and saving the design cost.
Description
Technical field
The present invention relates to SIC (semiconductor integrated circuit) and manufacture field, particularly relate to a kind of domain and schematic diagram consistency comparison method of multivoltage chip design.
Background technology
In existing chip design, after finishing, chip layout design must carry out domain and schematic diagram comparison of coherence (Layout versus Schematic, LVS), to guarantee the consistance of domain and circuit theory diagrams.As shown in Figure 1, for the process flow diagram of existing LVS, the step of existing LVS comprises from layout data storehouse (Layout Database) step of extracting the step of domain net table (Layout Netlist) and carry out described domain net table and circuit theory diagrams net table (Schematic Netlist) to carry out comparison of coherence (Compare) under LVS design rule operation collection (Runset) environment.Described domain net table can also be modified by domain net table script file, and described domain net table script file is generally MPower.pl file.
In existing chip design, for reducing chip power-consumption, generally adopt multivoltage design, also adopt multi-power domain design.In existing multivoltage chip design, the power pin (pin) of the unit relevant with low-power consumption (Cell) is many.Because in the domain net table of existing automatic placement and routing instrument output, do not support, by the relevant separately output of cell power supply pin of low-power consumption, so it is relatively complicated to be LVS, in prior art, generally to adopt several method below to realize LVS:
First method, modification runset force a plurality of power supply pin of the relevant cell of low-power consumption to be defined as a power supply in runset, make LVS successful, but this kind of method can be brought certain risk, causes LVS can not reflect real situation.
A plurality of power supplys of second method, the cell that in domain, low-power consumption is correlated with are revised and are connected into a power supply, after checking successfully Deng LVS, in domain, change back again original connection, so not only loaded down with trivial details, take time and effort, equally also can bring certain risk, cause LVS can not reflect real situation.
So for existing multivoltage chip design, it is lower that prior art is done LVS efficiency, and there is certain risk to exist.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of domain and schematic diagram consistency comparison method of multivoltage chip design, can improve checkability and reliability, reduction check risk, save design cost.
For solving the problems of the technologies described above, the domain of multivoltage chip design provided by the invention and schematic diagram consistency comparison method, is characterized in that, comprises the steps:
Step 1, with script, revise the script file of domain net table.While revising described script file, comprise the steps:
Step 1 A, each power port name of each functional module of finding out chip and the power domain under each power port.
Step 1 B, according to power port name described in each of functional module described in each, in domain net table, add respectively and the module of power port name correspondence and the power port of standard block described in each.
Step 1 C, according to the power domain under functional module described in each, each power supply line title of functional module described in each is increased in described domain net table.
Step 1 D, in described domain net table top-level module, add each power supply line title of functional module described in all each.
Step 2, execution be the modification of described script file realization to described domain net table after revising.
Further improvement is, described script file is executable file MPower.pl, and described script is PERL language.
Further improve and be, described in each, functional module comprises power supply Chang Kaimo piece and can the large class of power-off modular two.
Further improve is that described domain net table also comprises and carries out the domain net table of chip and the step of schematic diagram one causing property of net table comparison after revising.
That the present invention has is simple, advantage conveniently, can improve efficiency and reliability that LVS checks, can save slip-stick artist's physical verification time, increase work efficiency, the present invention can also shorten chip roll off the production line (TAPEOUT) time, improve chip flow success ratio, save design cost.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the process flow diagram of existing LVS;
Fig. 2 is the process flow diagram of the inventive method.
Embodiment
Be the process flow diagram of the inventive method as shown in Figure 2, the domain of embodiment of the present invention multivoltage chip design and schematic diagram consistency comparison method, comprise the steps:
The script file MPower.pl of domain net table revised in step 1, use PERL language.While revising described MPOwer.pl, comprise the steps:
Step 1 A, each power port name of each functional module of finding out chip and the power domain under each power port.Described in each, functional module comprises power supply Chang Kaimo piece and can the large class of power-off modular two.
Step 1 B, according to power port name described in each of functional module described in each, in domain net table, add respectively and the module of power port name correspondence and the power port of standard block described in each.
Step 1 C, according to the power domain under each functional module, each power supply line title of functional module described in each is increased in described domain net table.
Step 1 D, in described domain net table top-level module, add each power supply line title of functional module described in all each.
Step 2, execution be the modification of described script file realization to described domain net table after revising.
Step 3, the domain net table that carries out chip and the comparison of schematic diagram consistance net table.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (3)
1. the domain of multivoltage chip design and a schematic diagram consistency comparison method, is characterized in that, comprises the steps:
Step 1, with script, revise the script file of domain net table; While revising described script file, comprise the steps:
Step 1 A, each power port name of each functional module of finding out chip and the power domain under each power port;
Step 1 B, according to power port name described in each of functional module described in each, in domain net table, add respectively and the module of power port name correspondence and the power port of standard block described in each;
Step 1 C, according to the power domain under functional module described in each, each power supply line title of functional module described in each is increased in described domain net table;
Step 1 D, in described domain net table top-level module, add each power supply line title of functional module described in all each;
Step 2, execution be the modification of described script file realization to described domain net table after revising;
Described domain net table also comprises and carries out the domain net table of chip and the step of schematic diagram consistance net table comparison after revising.
2. the domain of multivoltage chip design and schematic diagram consistency comparison method as claimed in claim 1, is characterized in that: described script file is executable file MPower.pl, and described script is PERL language.
3. the domain of multivoltage chip design and schematic diagram consistency comparison method as claimed in claim 1, is characterized in that: described in each, functional module comprises power supply Chang Kaimo piece and can the large class of power-off modular two.
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| CN201110001008.6A CN102591997B (en) | 2011-01-05 | 2011-01-05 | Layout and schematic diagram consistency comparison method for multi-voltage chip design |
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| CN201110001008.6A CN102591997B (en) | 2011-01-05 | 2011-01-05 | Layout and schematic diagram consistency comparison method for multi-voltage chip design |
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| CN102591997A CN102591997A (en) | 2012-07-18 |
| CN102591997B true CN102591997B (en) | 2014-02-26 |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103838890B (en) * | 2012-11-23 | 2016-12-21 | 上海华虹宏力半导体制造有限公司 | There is black box IP multi-power domain system domain and the conforming comparative approach of schematic diagram |
| CN104731994A (en) * | 2013-12-23 | 2015-06-24 | 上海华虹宏力半导体制造有限公司 | Method of generating schematic netlist through nonstandard cell library |
| CN104091161A (en) * | 2014-07-15 | 2014-10-08 | 山东超越数控电子有限公司 | Schematic circuit diagram netlist comparison method |
| KR20160078032A (en) * | 2014-12-24 | 2016-07-04 | 삼성전자주식회사 | Apparatus and method for electronic design automation |
| CN105373668B (en) * | 2015-11-30 | 2018-06-19 | 上海华虹宏力半导体制造有限公司 | Chip layout design method |
| CN105844012B (en) * | 2016-03-22 | 2019-01-04 | 中国科学院微电子研究所 | A kind of the domain comparison schematic diagram verification method and device of discrete device |
| CN109635488B (en) * | 2018-12-26 | 2020-05-12 | 南京九芯电子科技有限公司 | Method and tool for designing process of panel display integrated circuit |
| CN109948226B (en) * | 2019-03-13 | 2020-12-25 | 上海安路信息科技有限公司 | Method and system for processing drive information |
| CN112115666B (en) * | 2019-06-03 | 2023-04-14 | 迈普通信技术股份有限公司 | Method and system for drawing schematic diagram |
| CN112069749B (en) * | 2020-09-14 | 2021-07-20 | 成都海光微电子技术有限公司 | Power supply connection verification method and device, electronic equipment and storage medium |
| CN114650246A (en) * | 2020-12-18 | 2022-06-21 | 中国移动通信有限公司研究院 | Detection method, device and equipment for IP core calling |
| CN117272910B (en) * | 2023-11-22 | 2024-02-23 | 江山季丰电子科技有限公司 | Modularized design method and device for aging circuit board of integrated circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW439257B (en) * | 1998-11-18 | 2001-06-07 | Nat Science Council | Cell for use in multi-voltage design environment |
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| JPH0794587A (en) * | 1993-09-20 | 1995-04-07 | Fujitsu Ltd | Semiconductor device, method and system for designing semiconductor |
| JP2010033411A (en) * | 2008-07-30 | 2010-02-12 | Denso Corp | Data creation method for lvs of circuit diagram |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW439257B (en) * | 1998-11-18 | 2001-06-07 | Nat Science Council | Cell for use in multi-voltage design environment |
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| JP特开2010-33411A 2010.02.12 |
| JP特开平7-94587A 1995.04.07 |
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