4 34Qft9 6 d o c / Ο Ο 8 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（[) 本發明是有關於一種直接監視半導體製程優劣的掃 瞄式電子顯微鏡（Scanning Electron Microscope ’ SEM) ’ 且特別是有關於一種在生產線（In-Line)上，對用來判定 各階段半導體製程優劣之製程控制監視(Process Control Monitoring，PCM)結構，直接檢測之掃瞄式電子顯微鏡。 隨著科技的進步，半導體製造儼然已成爲最重要的 產業之一，然而，半導體爲因應不同的需求，其製造過 程也就變得越來越複雜，因此，要製造出高良率（Yield) 且低成本之晶片，也就變得越來越不容易了。 一般而言，半導體晶片在製造過程中，從投片（Wafer Start)到產品完成，動輒需要經過數百個製程步驟(Process Step)，如果單靠成品在包裝(Packing)前的測試，而要掌 握整個製程之優劣，這是相當不可能的，因此，若能夠 在製造過程中，隨時獲得製程優劣之訊息，不但可以掌 握製程狀況，及時採取改進措施或報廢不良製程的當站 晶片，更可有效降低生產成本，並縮短生產所需的時間。 爲使在半導體晶片製造過程中，隨時獲得製程優劣 之訊息，因此在半導體晶粒（Die)的周邊，會特別設計許 多測試鍵（Test Key)，用以監控各階段製程的優劣，此些 測試鍵一般稱爲製程控制監視結構。 在半導體製造的過程中，所需檢測的項目有多晶矽 電容器特性、閘氧化層特性、不同多晶矽層間的橋接 (bridging)情形、接觸窗（Contact)或介層窗（Via)整合 (Integraty)情形、以及同層及相鄰層之金屬線間的橋接情 ^^^1 ^—>1 J- - - tl^i J ^^^1 ^^^1 ^^^1 ^—4» - - I (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐> 經濟部智慧財產局員工消費合作社印製 90^6 ^ Λ 7 4 6 7 4 twf.doc/008 __ Β7 五、發明説明（>) 形等。 對於這些測試鍵的檢測，一般係以離線（〇ff_Line)的 方式’也就是必須將產品移至生產線以外來進行。一般 而言’檢測這些測試鍵大多是利用微探針設備來完成。 第1圖係繪示傳統檢測金屬線間是否發生橋接情形 的示意圖。 請參照第1圖，一梳型（Comb)測試鍵結構100 ,包括 一第一梳型結構l〇〇a與第二梳型結構l〇〇b，其中，第一 梳型結構l〇〇a與一測試墊（Test Pad)101a耦接，而第二 梳型結構l〇〇b與一測試墊i〇ib耦接，此第一梳型結構 100a、第二梳型結構100b與測試墊l〇la及l〇lb是定義 同一層金屬層而形成的 當第一梳型結構l〇〇a與第二梳型結構i〇〇b沒有發生 橋接的現象時，亦即當此二梳型結構100a與100b不是 處於短路的情形下，經由微探針（Probe)102a與102b在 測試墊l〇la與101b的探測，可測得第一梳型結構100a 與第二梳型結構l〇〇b間具有相當大的電阻値。 然而，當第一梳型結構l〇〇a與第二梳型結構i〇〇b間 發生橋接的現象時，亦即當此二梳型結構100a與100b 處於短路的狀態下，經由微探針l〇2a與102b在測試墊 101a與101b的探測，可測得第一梳型結構l〇〇a與第二 梳型結構100b間的電阻値變得相當小。 由於此梳型測試鍵結構100位於晶粒之周圍，因此 當此梳型測試鍵結構100沒有發生橋接的現象時，相對 4 ^^1 ^^^1 ^^^1 —^f f Jw HI ^^^1 ^^^1 ΐ ,， (請先聞讀背面之注意事項再填寫本頁) 本紙^度適用中國國家標準（CNS ) Α4ίξ^"( 210X297公釐) 43 9〇 96 A7 4 6 7 4 twf.d〇c/008_^__ 五、發明説明（> ) (請先聞讀背面之注意事項再填寫本頁) 地，也表示在其附近之晶粒，在定義同一層金屬層時， 沒有發生橋接的現象，反之亦然，因此藉由此梳型測試 鍵結構100的檢測，可監視相關製程之優劣。 然而，這種以微探針量測來檢測製程優劣的方式， 由於必須將產品移至生產線外來進行，因此易造成製程 時間的延若。 另外，一旦將晶片從生產線上移出以進行微探針檢 測，則晶片易發生不預期的污染而使污染粒子數增加， 或晶片損壞情形增加等情事 因此本發明提供一種直接監視半導體製程的掃瞄式 電子顯微鏡，用以改進傳統在進行微探針檢測晶片之測 試鍵時，所易發生的晶片污染或晶片損壞之缺點。 經濟部智慧財產局員工消費合作社印製 本發明提出一種直接監視半導體製程優劣的掃瞄式 電子顯微鏡，用於檢測置放於一晶片上之具有製程控制 監視結構的一測試鍵，以推測與製作此測試鍵相關之製 程優劣與否，此直接監視半導體製程優劣的掃瞄式電子 顯微鏡包括一真空腔體、一影像顯示系統與一數據處理 系統，其中，此真空腔體內包括一晶片夾盤，此晶片夾 盤上配置有上述之待檢測晶片，一電子束放射槍，用以 產生一電子束射至待檢測晶片之測試鍵，並藉此產生複 數個表面電子訊號，以及一偵測器，用於偵測此些表面 電子訊號β 而影像顯示系統，與偵測器耦接，用以將偵測器所 接收之表面電子訊號，轉換成一影像，數據處理系統， 5 本紙張尺度適用中國國家橾準（CNS ) A4ilt格（2丨ΟΧ297公釐） 4 4674twf.d〇c/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（(// ) 則是與影像顯示系統耦接，用於儲存影像顯示系統所顯 示之影像。 另外，測試鍵係指用於檢測多晶矽電容器、多晶矽 間之橋接、內層多晶矽層間之橋接、接觸窗或介層窗之 整合、金屬線間之橋接、內層金屬層間橋接等與半導體 製程優劣相關之製程控制監視結構。 本發明係揭露一種直接監視半導體製程優劣的掃瞄 式電子顯微鏡，利用被動電壓反差（Passive Voltage Contrast ; PVC)效應，對具有一端接地 端處於電性 浮動（Floating)之用於製程控制監視之測試鍵進行掃瞄， 並由此測試鍵表面所產生之表面電子訊號的強弱，或是 此表面電子訊號的強弱所顯示出之影像對比，來判定製 作此測試鍵之相關製程的優劣。 利用本發明，可直接在生產線上進行製程檢測，因 此可降低產品生產所需之時間，或硏究發展所需的週期 時間（cycle time)。特別注意的是，目前尙無可以直接應 用在線上之特殊功能的機臺，故本發明實屬創見。 利用本發明，可直接在生產線上進行製程檢測，因 此可減少晶片遭受污染或損壞之情形。 本發明另一個特色是其所進行的檢測是一種非破壞 性（non-destructive)的探測，因而可以應用在許多需要非 破壞性探測的半導體結構上。 由於這種利用影像結果來鑑定的方式非常淸楚明 顯，因而利用本發明，可以利用輕易而快速地完成製程 6 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐> ^^1' nn n ^^1 HI / l^i ^^1 1^1 ^^1 ^^1 ^ J. {請先閲讀背面之注意事項再填寫本頁) 439〇96 4674twf*doc/008 A7 B7 經濟部智慧財產局8工消費合作社印製 五、發明説明（t) 控制監視的工作。 本發明可應用在檢測目前半導體廠中使用的製程控 制監視結構之測試鍵，只要具有這種一端接地，一端浮 動的電路設計，均可利用本發明來完成檢測或硏發之工 .作，例如多晶矽或金屬線距的大小系列監測製程能力的 各種結構，進而得知各階段製程的優劣情況。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖係繪示傳統檢測金屬線間是否發生橋接情形 的示意圖； 第2圖係繪示依據本發明之較佳實施例之一種直接 監視半導體製程優劣的掃瞄式電子顯微鏡； 第3圖係繪示第2圖中，晶片240上所具有之測試 鍵200的結構示意圖： 第4A圖係繪示用以檢測介電層特性之測試鏈結構上 視示意圖； 第4B圖則繪示第4A圖沿IV-IV方向之結構剖面示意 圖； 第5圖係繪示用以檢測相鄰的不同導電層間是否發 生橋接現象的測試鍵結構上視示意圖； 第6圖係繪示用以檢測導電線連續性的測試鍵結構 上視示意圖；以及 n- m In ^^^1 1. · ^^1^TaJ {諳先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標牟{ CNS ) A4见格（210X297公嫠） 439〇96 五、發明説明（ί) 第7圖係繪示用以檢測接觸窗或介層窗特性的測試 鍵結構剖面示意圖。 圖式之標記說明： 100 :梳型測試鍵結構 100a、200a :第一梳型結構 100b、200b :第二梳型結構 101a 、 101b 、 201a 、 201b 、 602 、 604 、 706 、 708 :測 試墊 102a、102b :微探針 200 :測試鍵 210 :晶片夾盤 212 :夾角 220 :偵測器 230 :電子束放射槍 230a :電子束 230b :表面電子訊號 240 :晶片 245 :真空腔體 經濟部智慧財產局員工消黃合作社印製 ^^1 __ - - -- .^^1 n m 1 J - HI ^^1 - -- 、-< (請先聞讀背面之注意事項再填寫本頁) 25〇:直接監視半導體製程優劣的掃瞄式電子顯微鏡 2 6 0 .水平線 265 :影像顯示系統 270 :數據處理系統 400、404 :導電層 402 :介電層 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 X 297公釐） 經濟部智慧財產局貞工消費合作社印製 五'發明説明（1) 500、502、600、700、702 :導電線 704 :插塞 實施例 第2圖係繪示依據本發明之較佳實施例之一種直接 監視半導體製程優劣的掃瞄式電子顯微鏡。 本發明所揭露之掃瞄式電子顯微鏡，是一種利用被 動電壓反差的特性，以監視製程優劣之掃瞄式電子顯微 鏡。 請參照第2圖，一直接監視半導體製程優劣的掃瞄 式電子顯微鏡25〇，包括一真空腔體（Chamber)245，此真 空腔體245內含有一電子束放射槍（Electron Emission Gun)230、一晶片夾盤（Holding Chuck)210、以及一個偵 測器(DeteCt〇r)220。其中晶片夾盤210須接地（設備系統 電性接地；equipment system electrical GROUND)。 當電子束放射槍230產生一電子束230a，且此電子 束230a射向置放在晶片夾盤210上的晶片240時，依照 電子顯微鏡的操作原理，晶片240將產生許多表面電子 訊號230b，其中，此表面電子訊號230b譬如是二次電 子（Secondary Electron) ° 其中，產生電子束230a所使用之能量，譬如約略是 1至2千電子伏特（KeV)。 此表面電子訊號230b將會被位於約略是在晶片240 上方之偵測器220所接收，當夾盤210與偵測器220之 間具有一個夾角212約略爲60度的情形時，將最有利於 9 I- I ~ 11 y ‘ j* «In ^^^1^OJ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國@家標準（〇^)六4規格（210乂297公釐） 經濟部智慧財1局員工消費合作社印製 43 9〇96 4674twf.doc/008 五、發明説明（3 ) 偵測器220接收表面電子訊號230b，其中，圖中所繪示 之虛線260係表示水平線。而從偵測器220所接收到的 表面電子訊號230b，可得知晶片240的表面訊息。 第3圖係繪不弟2圖中1晶片240上所具有之測試 鍵200的結構示意圖。 請參照第3圖，當此測試鍵200爲一用以檢測金屬 線間或多晶矽線間是否發生橋接現象之梳型測試鍵結構 時，此測試鍵200包括一第一梳型結構200a與第二梳型 結構200b，其中，第一梳型結構200a與一測試墊201a 耦接，而第二梳型結構200b與一測試墊201b耦接，此 第一梳型結構2〇Oa、第二梳型結構200b與測試墊20U 及201b譬如是定義同一層金屬層或同一層多晶矽層而形 成的。 其中，此與第一梳型結構200a耦接的測試墊201a處 於一接地的狀態，此形成接地的方法，譬如是將此測試 墊201a與晶片240之基底形成接觸。而與第二梳型結構 200b耦接的測試墊201b則不使之接地，以維持在一可 電性浮動的狀態下。 此外，第一梳型結構200a與第二梳型結構200b，可 製作成具有不同的線寬，以及不同的線距(Pitch)的結構， 以明瞭在一系列不同線寬與線距的結構下，製程能力的 優劣。 請同時參照第2與3圖，當電子束放射槍230所產 生之電子束230a射向置放在晶片夾盤210上之晶片240 .^^1' n^i ^^^1 t. m mu ^#J (諳先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS) A4规格（210x297公釐） 經濟部智慧財產局員工消費合作社印提 4674twf.d〇c/00B Α7 Β7 五、發明説明（^ ) 的測試鍵200時，第一梳型結構200a與第二梳型結構 200b，將產生許多表面電子訊號230b，且此些表面電子 訊號230b將被偵測器220所接收。 當第一梳型結構200a與第二梳型結構200b沒有發生 橋接的現象時，由於與第一梳型結構200a耦接的測試墊 201a處於一接地的狀態，因此當第一梳型結構200a產生 表面電子訊號230b時，同時在第一梳型結構200a表面 因失去電子而產生之正電荷，將藉由接地端傳來的電子 中和而消失，而不至於在第一梳型結構200a的表面形成 正電場，並禁制之後表面電子訊號230b的產生，因此， 第一梳型結構200a表面所產生之表面電子訊號230b，其 強度與數目約略維持一定，因此偵測器220所接收到來 自第一梳型結構200a所產生之表面電子訊號230b，其訊 號強度將不會變化。 然而，與第二梳型結構200b耦接的測試墊201b並 非處於一接地的狀態，因此當第二梳型結構200b產生表 面電子訊號230b時，同時在第二梳型結構200b表面因 失去電子而產生之正電荷，將會累積在第二梳型結構200b 的表面，而在此表面形成一正電場，使得接下來第二梳 型結構200b的表面，因受此逐漸增大之正電場的牽制， 而越來越不易產生表面電子訊號230b，因此偵測器220 所接收到來自第二梳型結構200b所產生之表面電子訊號 230b，其訊號強度亦將越來越弱。 由此可知，當第一梳型結構2〇〇a與第二梳型結構200b (請先閱讀背面之注意事項再填寫本頁) 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 439096 A7 4674twf.doc/008 B7 五、發明説明（β) 沒有發生橋接的現象時，偵測器220所接收到，來自處 於接地狀態之第一梳型結構200a所產生之表面電子訊號 230b，將較來自處於非接地狀態之第二梳型結構200b所 產生之表面電子訊號230b，具有較大之強度，亦即，偵 測器220所接收到之測試鍵200的表面電子訊號230b， 具有明顯的強度對比。 反之，若當第一梳型結構200a與第二梳型結構200b 發生橋接的現象時，則原先處於可電性浮動狀態下的第 二梳型結構200b，將因橋接現象的發生，而使此第二梳 型結構200b亦處於接地的狀態，如此一來，第一梳型結 構200a與第二梳型結構200b所產生之表面電子訊號 230b，將具有約略相同之強度，亦即，偵測器220所接 收到之測試鍵200的表面電子訊號230b，並不具有明顯 強度對比。 因此，由測試鍵200的表面電子訊號230b是否具有 明顯強度對比的結果，可知曉此測試鍵200的優劣情形。 若位於此測試鍵200周圍之晶粒的結構，具有與此測試 鍵200相同的佈局時，則可由此測試鍵200的檢測結果， 推測此位於測試鍵200周圍之晶粒是否良好，進而更可 得知相關製程之優劣。 本發明之直接監視半導體製程優劣的掃瞄式電子顯 微鏡250，更可包括一影像顯示系統265，此影像顯示系 統265與偵測器220耦接，用以將偵測器220所接收之 表面電子訊號230b，轉換成影像。 i^n ^^^1 —^1 f. n^i ^^^1 ν— Η 03,-a (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國圉家標準（CNS ) A4規格（210X297公釐） 43 9。Μ 4674twf.doc/008 五、發明説明（（丨） (請先閱讀背面之注意事項再填寫本頁) 若第一梳型結構200a與第二梳型結構200b沒有發生 橋接的現象時，將可在影像顯示系統265中所顯示的影 像中，觀察到第一梳型結構200a與第二梳型結構200b， 具有明顯的亮度對比。 而當第一梳型結構2〇〇a與第二梳型結構200b發生橋 接的現象時，將可在影像顯示系統265中所顯示的影像 中，觀察到第一梳型結構200a與第二梳型結構200b，並 不具有明顯的亮。 本發明之直接監視半導體製程優劣的掃瞄式電子顯 微鏡250，更可包括一數據處理系統270，此數據處理系 統270與影像顯示系統265或偵測器220耦接，用於儲 存影像顯示系統265所觀察到之關於測試鍵200的對比 影像，以供後續比較。 經濟部智慧財產局8工消費合作社印製 此比較測試鍵200之對比影像所使用之方法，譬如 是製作一組標準試片，此標準試片係先經傳統所使用之 微探針量測，以確定其所具有之測試鍵200，爲經過良 好製程所製成的，然後利用本發明所揭露之掃瞄式電子 顯微鏡250，對之進行影像掃瞄，再將其對比影像以數 據處理系統270儲存。 然後將待測之晶片送入本發明所揭露之掃瞄式電子 顯微鏡250中，對晶片上之測試鍵200逐一進行影像掃 瞄，然後將此待測晶片掃瞄之對比影像，與已儲存於數 據處理系統270之標準試片的對比影像進行比較，則可 得知待測晶片之良好與否。 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） 經濟部智慧財產局員工消費合作社印製 43 9〇 五、發明説明（ίΜ 此影像比對之原理，與目前半導體所使用之缺陷掃 瞄儀器，譬如KLA，是十分相似的。 若此數據處理系統270具有足夠的記憶體，可以於 檢測時掌握影像之明暗對比，而存下一些有缺陷狀況的 _案例資料，以供往後參考，甚至可以編寫程式，來擷取 測試鍵200的幾個少部份或小部份區域進行比較，以獲 得更多有關製程優劣之資訊。 此外，本發明之直接監視半導體製程優劣的掃瞄式 電子顯微鏡250，還具有自動對焦系統（未繪示），可利用 晶片上之對準標誌（Alignment Mark)，以進行自動搜尋及 掃瞄特定區域之測試鍵200。 本發明之直接監視半導體製程優劣的掃瞄式電子顯 微鏡250還可設有CD ROM(未繪示），用以傳送元件每個 製程階段的測得的數據，以進行比較。 本發明之直接監視半導體製程優劣的掃瞄式電子顯 微鏡250，還可配有列印系統（未繪示），可將每個批號產 品的探測結果列印出來。 另外，晶片240上所具有之測試鍵200，除了第3圖 所顯示之用以檢測金屬線間橋接現象之梳型測試鍵結構 外，還包括譬如是用於檢測多晶矽電容器、多晶矽間之 橋接、內層多晶矽層間之橋接、接觸窗或介層窗之特性、 金屬線間之橋接、內層金屬層間橋接等與半導體製程優 劣相關之製程控制監視結構，亦即，目前半導體廠所使 用之製程控制監視結構，均於此列。 ^^1- ^^^1 ^^^1 —tn m s n^l 1^1 ^^^1 s-6 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 43 9〇 A7 4674twf.doc/008 D_ D / 五、發明説明（L)) 第4A圖係繪示用以檢測介電層特性之測試鍵結胃± 視示意圖，第4B圖則繪示第4A圖沿IV-IV方向之結構 剖面示意圖。 請同時參照第4A與4B圖，此用以檢測介電層特性 之測試鍵結構係在一導電層400的表面，形成一特性待 檢測之介電層4〇2，然後再於此介電層4〇2的表面形成 —導電層4〇4。其中，導電層400處在一接地的狀態下， 其形成接地的方法，譬如是將導電層400與晶片之基底 形成接觸，而導電層404則維持在一可電性浮動的狀態 下。 經濟部智慧財產局貝工消費合作社印製 Β% (請先聞讀背面之注意事項再填寫本頁) 此用以檢測介電層特性之測試鍵結構中的導電層 400，譬如是使用半導體基底、多晶矽層或金屬層，而導 電層404譬如是使用多晶矽層或金屬層，一般而言，此 導電層400與404爲半導體製程中先後使用之導電層。 而特性待檢測之介電層402則包括半導體製程中所會使 用到的介電層，譬如聞極氧化層（Gate Oxide Layer)、金 屬內介電層（Inter-Layer Dielectrics，ILD) '電容器介電 層、多晶砂間介電層（Inter-Poly Dielectrics，IPD)與金屬 間介電層（Inter-Metal Dielectrics，IMD)。 在進行檢測時，將具有此用以檢測介電層特性之測 試鍵結構的晶片，放入本發明之直接監視半導體製程優 劣的掃瞄式電子顯微鏡250中，若介電層402特性良好 時，導電層400與404將形成良好的電性絕緣，則進行 電子束掃瞄時，由於導電層400接地而導電層404處於 本紙張尺度適用中國國家標率（CNS ) A4規格（2! 0 X 297公釐） 43 43 A7 B7 4674twf.doc/008 五、發明説明（#) 電性浮動的狀態下’因此從掃瞄式電子顯微鏡250所觀 察到的導電層400與404的影像，將有強烈的明暗對比。 ----------装— (請先閱讀背面之注意事項再填寫本頁) 反之，若介電層402特性不佳，而使導電層400與404 不能形成良好的電性絕緣，則進行電子束掃瞄時，導電 層400與導電層404將處於具有相同的電位的狀態下， 因此從掃瞄式電子顯微鏡250所觀察到的導電層400與 404的影像，將不再有強烈的明暗對比。 第5圖係繪示用以檢測相鄰的不同導電層間是否發 生橋接現象的測試鍵結構上視示意圖。 請參照第5圖，此用以檢測相鄰的不同導電層間是 否發生橋接現象的測試鍵結構，係在一具有蜿蜒 (Meanders)圖案的導電線（Conductive Line)500 的上方， 形成與具有蜿蜒圖案的導電線500不同蜿蜒方向的另一 具有蜿蜒圖案的導電線502,而此具有蜿蜒圖案的導電 線500與502間，形成有與具有蜿蜒圖案的導電線502 相同圖案之具有絕緣特性的介電層，如此，具有蜿蜒圖 案的導電線500將因未被具有蜿蜒圖案的導電線502所 完全覆蓋，而裸露出部分的表面。 經濟部智慧財產局員工消費合作社印製 其中，具有蜿蜒圖案的導電線500處在一接地的狀 態下，其形成接地的方法，譬如是將具有蜿蜒圖案的導 電線5〇〇與晶片之基底形成接觸，而具有蜿蜒圖案的導 電線502則維持在一可電性浮動的狀態下。 此用以檢測相鄰的不同導電層間是否發生橋接現象 的測試鍵結構中的具有蜿蜒圖案的導電線500,譬如是 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 43 90 A7 4 6 7 4 twf . doc/ 0 0 8 五、發明説明（（Ο 指多晶矽導線、金屬導線，或是直接使用半導體基底， 而具有蜿蜒圖案的導電線502譬如是指多晶矽導線或金 屬導線，一般而言，此具有蜿蜒圖案的導電線500與502 爲半導體製程中先後使用之導電線。 在進行檢測時，將具有此用以檢測相鄰的不同導電 層間是否發生橋接現象的測試鍵結構的晶片，放入本發 明之直接監視半導體製程優劣的掃瞄式電子顯微鏡250 中，若具有蜿蜒圖案的導電線500與5〇2沒有發生橋接 現象時，具有蜿蜒圖案的導電線500與502將形成良好 的電性絕緣，則進行電子束掃瞄時，由於具有蜿蜒圖案 的導電線500接地而具有蜿蜒圖案的導電線5〇2處於電 性浮動的狀態下，因此從掃瞄式電子顯微鏡25〇所觀察 到的具有蜿蜒圖案的導電線500與502的影像，將有強 烈的明暗對比。 反之，若具有蜿蜒圖案的導電線500與502發生橋 接現象時，而使具有蜿蜒圖案的導電線5〇〇與5〇2不能 經濟部智慧財產局員工消費合作社印製 —^—'^^^1 ^^^1 ^^^1 i^l^i i^it —an 1·^— {請先鬩讀背面之注意事項再填寫本頁) 形成良好的電性絕緣，則進行電子束掃瞄時’具有蜿蜒 圖案的導電線500與502將處於具有相同的電位的狀態 下，因此從掃瞄式電子顯微鏡25〇所觀察到的具有蜿蜒 圖案的導電線5〇〇與5〇2的影像’將不再有強烈的明暗 對比。 第6圖係繪示用以檢測導電線連續性的測試鍵結構 上視示意圖。 請參照第6圖，此用以檢測導電線連續性的測試鍵 本紙張尺度適用中國國家標準（CNS ) A4規格< 210X297公羞） 43 43 經濟部智慧財產局員工消費合作社印製 4674twf.doc/008 A? B7____ 五、發明説明（（【） 結構，係定義一金屬層（圖未示）成一具有蜿蜒圖案的導 電線600，以及兩個分別與導電線600的終端(Terminates) 耦接的測試墊602與604，其中，測試墊602處在一接 地的狀態下，其形成接地的方法，譬如是將測試墊602 與晶片之基底形成接觸，而測試墊604則維持在一可電 性浮動的狀態下。 此用以檢測導電線連續性的測試鍵結構中的導電線 600以及兩個測試墊602與604，譬如是定義一多晶矽層 或金屬層而成的。 在進行檢測時，將具有此用以檢測導電線連續性的 測試鍵結構的晶片，放入本發明之直接監視半導體製程 優劣的掃瞄式電子顯微鏡250中，若具有蜿蜒圖案的導 電線600之連續性沒有異狀時，則具有蜿蜒圖案的導電 線600進行電子束掃瞄時，導電線600以及兩個測試墊 602與604將處於具有相同的電位的狀態下，因此從掃 瞄式電子顯微鏡250所見觀察到的導電線600以及兩個 測試墊602與604的影像，將沒有強烈的明暗對比。 反之，若具有蜿蜒圖案的導電線600之連續性發生 異狀時，亦即具有蜿蜒圖案的導電線600發生斷裂時， 則在進行電子束掃瞄時，從斷裂處至測試墊602之導電 線600的部分，與從斷裂處至測試墊604之導電線600 的部分，將因測試墊602處在一接地的狀態而測試墊604 維持在一可電性浮動的狀態下，造成掃瞄式電子顯微鏡 250中所觀察到的導電線600以及兩個測試墊602與604 ^^1. I - I Η - - - I -II ^^^1 ^^^1 ^^^1 n^i i ^^^1 ^^^1 ^^^1、一5J (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇Χ297公釐） 經濟部智慧財產局員工消費合作社印製 43 9096 4e74twf.d〇c/008 A1 B7 五、發明説明（〇 ) 的影像，將有強烈的明暗對比。 第7圖係繪示用以檢測接觸窗或介層窗特性的測試 鍵結構剖面示意圖。 請參照第7圖*此用以檢測接觸窗或介層窗特性的 測試鍵結構，係指相鄰兩導電線700與702間，以插塞 704耦接而成的蜿蜒結構，而導電線700的一端與測試 墊706耦接，導電線702的一端與測試墊708耦接。其 中，測試墊706處在一接地的狀態下，其形成接地的方 法，譬如是將測試墊706與晶片之基底形成接觸，而測 試墊708則維持在一可電性浮動的狀態下。 此用以檢測接觸窗或介層窗特性的測試鍵結構中的 導電線700與702，以及兩個測試墊706與708，譬如是 定義一多晶矽層或金屬層而成的。 在進行檢測時，將具有此用以檢測接觸窗或介層窗 的測試鍵結構的晶片，放入本發明之直接監視半導體製 程優劣的掃瞄式電子顯微鏡250中，若插塞704特性沒 有異狀時，則在進行電子束掃瞄時，導電線702以及兩 個測試墊706與708將處於具有相同的電位的狀態下， 因此從掃瞄式電子顯微鏡250所觀察到的導電線702影 像，將沒有強烈的明暗對比。 反之，若插塞704特性發生異狀時，亦即插塞704 特性發生開路（Opening)時，則在進行電子束掃瞄時，從 開路處至測試墊706之導電線702的部分，與從開路處 至測試墊708之導電線702的部分，將因測試墊706處 ml- ^^^1 ^^^1 ^^^1 ·ί·ί it^^-" ^^^1 ^^^1 In ^^^1 ^^^1 '一-SJ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中囷國家標準（CNS > A4規格（210X297公釐） 439096 4674twf.doc/008 A7 B7 經濟部智慧財產局負工消費合作社印製 五、發明説明（β) 在一接地的狀態而測試墊708維持在一可電性浮動的狀 態下，造成掃瞄式電子顯微鏡250中所觀察到的導電線 702影像，將有強烈的明暗對比。 此外，第4Α、4Β、5、6與7圖所顯示之結構，可製 作成具有不同的尺寸，如此將可明瞭在一系列不同尺寸 結構下，製程能力的優劣。 本發明係揭露一種直接監視半導體製程優劣的掃瞄 式電子顯微鏡，利用被動電壓反差效應，對具有一端接 地、一端電性浮動之用於製程控制監視之測試鍵進行掃 瞄，並由此測試鍵表面所產生之表面電子訊號的強弱， 或是此表面電子訊號的強弱所顯示出之影像對比，來判 定製作此測試鍵之相關製程的優劣。 利用本發明，可直接在生產線上進行製程檢測，因 此可降低產品生產所需之時間，或硏究發展所需的週期 時間。特別注意的是，目前尙無可以直接應用在線上之 特殊功能的機臺，故本發明實屬創見。 利用本發明，可直接在生產線上進行製程檢測，因 此可減少晶片遭受污染或損壞之情形。 本發明另一個特色是其所進行的檢測是一種非破壞 性的探測，因而可以應用在許多需要非破壞性探測的半 導體結構上。 由於這種利用影像結果來鑑定的方式非常淸楚明 顯，因而利用本發明，可以利用輕易而快速地完成製程 控制監視的工作。 20 --*J (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公釐） A7 B7 4 3 90 96 674twf .doc/008 五、發明説明（q) 本發明可應用在檢測目前半導體廠中使用的製程控 制監視結構之測試鍵，只要具有這種一端接地，一端浮 動的電路設計，均可利用本發明來完成檢測或硏發之工 作，例如多晶矽或金屬線距的大小系列監測製程能力的 各種結構，進而得知各階段製程的優劣情況。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾。因此本發明 之保護範圍當視後附之申請專利範圍所界定者爲準。 ----------.-4.— (請先鬩讀背面之注項再填寫本頁) *11. 經濟部智慧財產局員工消费合作社印製 21 本紙張尺度逍用中國國家標皁（CMS ) A4規格（210X297公釐>4 34Qft9 6 doc / Ο Ο 8 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention ([) The invention relates to a scanning electron microscope (Scanning Electron Microscope 'SEM) that directly monitors the advantages and disadvantages of semiconductor manufacturing processes. ) 'In particular, it relates to a scanning electron microscope that directly inspects a Process Control Monitoring (PCM) structure used to determine the pros and cons of a semiconductor process at each stage on the production line (In-Line). With the advancement of technology, semiconductor manufacturing has become one of the most important industries. However, in order to respond to different needs, the manufacturing process of semiconductors has become more and more complicated. Therefore, to produce high yield (Yield) and Low-cost chips have become increasingly difficult. Generally speaking, during the manufacturing process of semiconductor wafers, from wafer start to product completion, it often takes hundreds of process steps. If only the testing of the finished product before packaging is required, It is quite impossible to grasp the pros and cons of the entire process. Therefore, if you can get information on the pros and cons of the process at any time during the manufacturing process, you can not only grasp the process status, take timely improvement measures, or scrap the off-site wafers of bad processes. Effectively reduce production costs and shorten the time required for production. In order to obtain information on the pros and cons of the process at any time during the semiconductor wafer manufacturing process, a number of Test Keys are specially designed around the semiconductor die to monitor the pros and cons of each stage of the process. These tests Keys are commonly referred to as process control monitoring structures. In the process of semiconductor manufacturing, the items to be inspected are the characteristics of polycrystalline silicon capacitors, the characteristics of the gate oxide layer, the bridging situation between different polycrystalline silicon layers, the contact window (via) or the integration of the via (Integraty) situation, And bridging between metal lines in the same layer and adjacent layers ^^^ 1 ^ — > 1 J---tl ^ i J ^^^ 1 ^^^ 1 ^^^ 1 ^ —4 »--I (Please read the precautions on the back before filling out this page) This paper size applies the Chinese national standard (CNS > A4 size (210X297 mm) & printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economy 90 ^ 6 ^ Λ 7 4 6 7 4 twf.doc / 008 __ B7 V. Description of the invention (>), etc. For the testing of these test keys, it is generally done offline (0ff_Line), that is, the product must be moved outside the production line. Generally speaking, most of these test keys are tested using a micro-probe device. Figure 1 is a schematic diagram showing the traditional detection of bridges between metal wires. Please refer to Figure 1, a comb-type test key Structure 100, including a first comb structure 100a and a second comb structure 100b, wherein the first comb structure 100a is coupled to a test pad 101a, and the second comb structure 100b is coupled to a test pad 101b. The first comb structure 100a, the second comb structure 100b, and the test pads 10la and 10lb are formed by defining the same metal layer. The first comb structure 100a and the second comb structure 100 are formed. b There is no bridging phenomenon, that is, when the two comb structures 100a and 100b are not short-circuited, it can be measured through the detection of microprobes (Probe) 102a and 102b on the test pads 10la and 101b. There is considerable resistance between the first comb structure 100a and the second comb structure 100b. However, when a bridge occurs between the first comb structure 100a and the second comb structure 100b In the phenomenon, that is, when the two comb structures 100a and 100b are in a short circuit state, the first comb structure 100a can be measured through the detection of the microprobes 102a and 102b on the test pads 101a and 101b. The resistance 値 between the second comb structure 100b and the second comb structure 100b becomes relatively small. Since the comb test key structure 100 is located around the die, the comb type When the test key structure 100 does not bridge, the relative 4 ^^ 1 ^^^ 1 ^^^ 1 — ^ ff Jw HI ^^^ 1 ^^^ 1 ΐ, (Please read the precautions on the back before reading (Fill in this page) This paper applies the Chinese National Standard (CNS) Α4ίξ ^ & (210X297 mm) 43 9〇96 A7 4 6 7 4 twf.d〇c / 008 _ ^ __ 5. Description of the invention (>) ( Please read the notes on the back before filling in this page.) The ground also indicates that the crystals in the vicinity of it have no bridging phenomenon when defining the same metal layer, and vice versa. The inspection of the structure 100 can monitor the pros and cons of the related processes. However, this method of measuring the pros and cons of the process with micro-probe measurement, because the product must be moved outside the production line, is prone to delay the process time. In addition, once the wafer is removed from the production line for microprobe detection, the wafer is prone to unintended contamination, increasing the number of contaminated particles, or increasing wafer damage. Therefore, the present invention provides a scan that directly monitors the semiconductor process. A type electron microscope is used to improve the disadvantages of wafer contamination or wafer damage that are easy to occur when the microprobe is used to test the test keys of the wafer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention proposes a scanning electron microscope that directly monitors the pros and cons of a semiconductor process, and is used to detect a test key with a process control monitoring structure placed on a wafer for inference and production The pros and cons of the process related to the test key. The scanning electron microscope that directly monitors the pros and cons of the semiconductor process includes a vacuum cavity, an image display system, and a data processing system. The vacuum cavity includes a wafer chuck. The wafer chuck is provided with the above-mentioned wafer to be inspected, an electron beam emitting gun for generating an electron beam to the test key of the wafer to be inspected, and thereby generating a plurality of surface electronic signals, and a detector, It is used to detect these surface electronic signals β and the image display system is coupled to the detector to convert the surface electronic signals received by the detector into an image, a data processing system. 5 This paper size is applicable to China Standard (CNS) A4ilt grid (2 丨 〇 × 297 mm) 4 4674twf.d〇c / 008 A7 B7 Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the cooperative V. Invention description ((//) is coupled with the image display system and used to store the image displayed by the image display system. In addition, the test key is used to detect the bridge between polysilicon capacitors and polysilicon. Process control and monitoring structures related to the quality of semiconductor processes, such as bridges between layers of polycrystalline silicon, integration of contact windows or interlayer windows, bridges between metal lines, and bridges between inner metal layers, etc. The present invention discloses a scanning method that directly monitors the advantages and disadvantages of semiconductor processes. A sighting electron microscope uses the passive voltage contrast (PVC) effect to scan a test key for process control monitoring with a grounding end at one end which is electrically floating, and from this test the surface of the key The strength of the generated surface electronic signal, or the contrast of the image displayed by the strength of the surface electronic signal, can be used to determine the pros and cons of the relevant process for making this test key. With the present invention, the process inspection can be performed directly on the production line, so it can Reduce the time required for product production, or study the cycle time required for development ( It is particularly noteworthy that at present, there is no machine that can directly apply special functions on the line, so the present invention is really original. Using the present invention, the process detection can be directly performed on the production line, so the wafer can be reduced from being contaminated. Or damage. Another feature of the present invention is that the detection is a non-destructive detection, so it can be applied to many semiconductor structures that require non-destructive detection. Because of this use of imaging results The method of identification is very clear and obvious. Therefore, the invention can be used to complete the process easily and quickly. 6 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm > ^^ 1 'nn n ^^ 1 HI / l ^ i ^^ 1 1 ^ 1 ^^ 1 ^^ 1 ^ J. {Please read the notes on the back before filling out this page) 439〇96 4674twf * doc / 008 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau 8 Workers Printed by Consumer Cooperatives 5. Description of Invention (t) Control and monitoring work. The present invention can be used to test the test control structure of the process control and monitoring structure currently used in semiconductor factories. As long as there is such a circuit design with one end grounded and one end floating, the present invention can be used to complete the detection or burst work. For example, The polycrystalline silicon or metal line pitch series monitor the various structures of the process capability, and then learn the pros and cons of each stage of the process. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1 Schematic diagram showing the traditional detection of bridges between metal wires. Figure 2 shows a scanning electron microscope that directly monitors the pros and cons of a semiconductor process according to a preferred embodiment of the present invention. Figure 3 shows the second In the figure, the structural diagram of the test key 200 on the chip 240 is shown in FIG. 4A. FIG. 4A is a schematic top view of the test chain structure for detecting the characteristics of the dielectric layer. FIG. Schematic cross-sectional view of the structure; Figure 5 is a top view of a test key structure used to detect whether a bridge between different conductive layers is adjacent; Figure 6 is a test key structure used to detect the continuity of conductive wires Schematic diagram of the top view; and n-m In ^^^ 1 1. · ^^ 1 ^ TaJ {阅读 Please read the notes on the back before filling in this page) This paper size is applicable to Chinese national standards {CNS) A4 see the grid (210X297 Gongren) 439〇96 Described invention (ί) FIG. 7 shows a schematic cross-sectional line test key structure for detecting a contact window or vias characteristics. Description of the drawing marks: 100: comb-shaped test key structure 100a, 200a: first comb-shaped structure 100b, 200b: second comb-shaped structure 101a, 101b, 201a, 201b, 602, 604, 706, 708: test pad 102a , 102b: Microprobe 200: Test key 210: Wafer chuck 212: Angle 220: Detector 230: E-beam radiation gun 230a: E-beam 230b: Surface electronic signal 240: Wafer 245: Vacuum chamber intellectual property Printed by the Bureau's employee co-op ^^ 1 __---. ^^ 1 nm 1 J-HI ^^ 1--,-< (Please read the precautions on the back before filling out this page) 25〇 : Scanning electron microscope 2 60 for direct monitoring of the pros and cons of semiconductor processes. Horizontal line 265: Image display system 270: Data processing system 400, 404: Conductive layer 402: Dielectric layer This paper applies Chinese National Standard (CNS) A4 specifications (2 丨 0 X 297 mm) Printed on the 5 'invention description by the Zhengong Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (1) 500, 502, 600, 700, 702: Conductive wire 704: Plug embodiment 2 Shows the advantages and disadvantages of a direct monitoring semiconductor process according to a preferred embodiment of the present invention Scanning electron microscope. The scanning electron microscope disclosed in the present invention is a scanning electron microscope that uses the characteristics of the passive voltage contrast to monitor the pros and cons of the manufacturing process. Please refer to FIG. 2, a scanning electron microscope 25 for directly monitoring the pros and cons of a semiconductor process includes a vacuum chamber (Chamber) 245, and the vacuum chamber 245 contains an Electron Emission Gun 230, A wafer chuck (Holding Chuck) 210 and a detector (DeteCtor) 220. The wafer chuck 210 must be grounded (equipment system electrical ground; equipment system electrical ground). When the electron beam emitting gun 230 generates an electron beam 230a, and the electron beam 230a is directed to the wafer 240 placed on the wafer chuck 210, according to the operating principle of the electron microscope, the wafer 240 will generate many surface electronic signals 230b, of which The surface electronic signal 230b is, for example, Secondary Electron ° Among them, the energy used to generate the electron beam 230a is, for example, approximately 1 to 2 thousand electron volts (KeV). This surface electronic signal 230b will be received by the detector 220 located approximately above the chip 240. It will be most beneficial when there is an included angle 212 between the chuck 210 and the detector 220 of approximately 60 degrees. 9 I- I ~ 11 y 'j * «In ^^^ 1 ^ OJ (Please read the precautions on the back before filling this page) This paper size is applicable to China @ 家 标准 （〇 ^) 6 4 specifications (210 乂 297 (Mm) Printed by the Consumer Cooperative of the 1st Bureau of Wisdom and Finance of the Ministry of Economic Affairs 43 9〇96 4674twf.doc / 008 V. Description of the invention (3) The detector 220 receives the surface electronic signal 230b, of which the dashed line 260 shown in the figure The lines represent horizontal lines. The surface electronic signal 230b received from the detector 220 can know the surface information of the chip 240. FIG. 3 is a schematic diagram showing the structure of the test key 200 on the wafer 240 in FIG. 2. Please refer to FIG. 3, when the test key 200 is a comb-type test key structure for detecting whether a bridging phenomenon occurs between metal lines or polycrystalline silicon lines, the test key 200 includes a first comb-type structure 200a and a second The comb structure 200b, wherein the first comb structure 200a is coupled to a test pad 201a, and the second comb structure 200b is coupled to a test pad 201b. The first comb structure 200a, the second comb structure The structure 200b and the test pads 20U and 201b are formed, for example, by defining the same metal layer or the same polycrystalline silicon layer. Wherein, the test pad 201a coupled to the first comb structure 200a is in a grounded state, and the method for forming the ground is, for example, bringing the test pad 201a into contact with the substrate of the wafer 240. The test pad 201b, which is coupled to the second comb structure 200b, is not grounded to maintain a electrically floating state. In addition, the first comb-shaped structure 200a and the second comb-shaped structure 200b can be made into structures with different line widths and different pitches in order to make it clear that under a series of different line widths and line pitches , Pros and cons of process capability. Please refer to FIGS. 2 and 3 at the same time, when the electron beam 230a generated by the electron beam emitting gun 230 is directed toward the wafer 240 placed on the wafer chuck 210. ^^ 1 'n ^ i ^^^ 1 t. M mu ^ # J (谙 Please read the notes on the back before filling in this page) This paper size applies the Chinese National Standard (CNS) A4 size (210x297 mm). The Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, India 4674twf.d〇c / 00B Α7 Β7 5. When the test key 200 of the invention description (^), the first comb structure 200a and the second comb structure 200b will generate many surface electronic signals 230b, and these surface electronic signals 230b will be detected by the detector 220 Received. When the first comb structure 200a and the second comb structure 200b are not bridged, since the test pad 201a coupled to the first comb structure 200a is in a grounded state, when the first comb structure 200a is generated, When the surface electronic signal is 230b, the positive charge generated by the loss of electrons on the surface of the first comb structure 200a at the same time will be neutralized by the electrons transmitted from the ground terminal, and will not be on the surface of the first comb structure 200a. A positive electric field is formed and the generation of surface electronic signals 230b after the prohibition is generated. Therefore, the surface electronic signals 230b generated on the surface of the first comb structure 200a have a certain strength and number. Therefore, the detector 220 receives the signals from the first The surface electronic signal 230b generated by the comb structure 200a will not change its signal strength. However, the test pad 201b coupled to the second comb structure 200b is not in a grounded state. Therefore, when the second comb structure 200b generates a surface electronic signal 230b, at the same time, the surface of the second comb structure 200b loses electrons. The positive charge generated will accumulate on the surface of the second comb structure 200b, and a positive electric field will be formed on this surface, so that the surface of the second comb structure 200b will be restrained by the increasing positive electric field. As the surface electronic signal 230b becomes more and more difficult to generate, the detector 220 will receive the surface electronic signal 230b generated from the second comb structure 200b, and its signal strength will also become weaker. It can be seen that when the first comb structure 200a and the second comb structure 200b (please read the precautions on the back before filling in this page) The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 439096 A7 4674twf.doc / 008 B7 V. Description of the invention (β) When no bridging occurs, the detector 220 receives it from the first comb that is in the grounded state. The surface electronic signal 230b generated by the structure 200a will be stronger than the surface electronic signal 230b generated by the second comb structure 200b in an ungrounded state, that is, the test received by the detector 220 The electronic signal 230b on the surface of the key 200 has a clear intensity contrast. Conversely, if the bridging phenomenon occurs between the first comb structure 200a and the second comb structure 200b, the second comb structure 200b that was originally in an electrically floating state will be caused by the bridging phenomenon. The second comb structure 200b is also in a grounded state. In this way, the surface electronic signals 230b generated by the first comb structure 200a and the second comb structure 200b will have approximately the same strength, that is, the detector The surface electronic signal 230b of the test key 200 received by 220 does not have a significant intensity comparison. Therefore, whether the surface electronic signal 230b of the test key 200 has a significant intensity comparison result can know the pros and cons of the test key 200. If the structure of the die located around the test key 200 has the same layout as the test key 200, the test result of the test key 200 can be used to infer whether the die located around the test key 200 is good, and thus more Learn about the pros and cons of related processes. The scanning electron microscope 250 of the present invention for directly monitoring the advantages and disadvantages of the semiconductor manufacturing process may further include an image display system 265, which is coupled to the detector 220 for coupling surface electrons received by the detector 220 The signal 230b is converted into an image. i ^ n ^^^ 1 — ^ 1 f. n ^ i ^^^ 1 ν— Η 03, -a (Please read the precautions on the back before filling this page) This paper size is subject to the Chinese Standards (CNS) A4 size (210X297mm) 43 9. Ｍ 4674twf.doc / 008 5. Description of the invention ((丨) (Please read the notes on the back before filling this page) If the first comb structure 200a and the second comb structure 200b are not bridged, it will be possible. In the image displayed in the image display system 265, it is observed that the first comb structure 200a and the second comb structure 200b have a clear brightness contrast. When the first comb structure 200a and the second comb structure 200a When the structure 200b is bridging, the first comb structure 200a and the second comb structure 200b can be observed in the image displayed in the image display system 265, which does not have obvious brightness. Direct monitoring of the present invention The scanning electron microscope 250, which has advantages and disadvantages in the semiconductor manufacturing process, may further include a data processing system 270. The data processing system 270 is coupled to the image display system 265 or the detector 220, and is used for storing information observed by the image display system 265 The comparison image of the test key 200 is for subsequent comparison. The method used by the 8th Industrial Cooperative Cooperative of the Intellectual Property Bureau of the Ministry of Economics to print the comparison image of the comparison test key 200, for example, to produce a set of standards This standard test strip is first measured by a conventional microprobe to determine that the test key 200 is made by a good process, and then the scanning electron microscope disclosed in the present invention is used. 250, scan the image, and store the comparison image in the data processing system 270. Then, send the wafer to be tested into the scanning electron microscope 250 disclosed in the present invention, and test the keys 200 on the wafer one by one. Scan the image, and then compare the comparison image scanned by the chip under test with the comparison image of the standard test strip that has been stored in the data processing system 270, to find out whether the chip under test is good or not. Applicable to Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 43 905. Description of the invention (ίΜ The principle of this image comparison is compared with the current defects in semiconductors. Aiming instruments, such as KLA, are very similar. If this data processing system 270 has enough memory, it can grasp the contrast of light and dark of the image during inspection and save it Defective case data for future reference. You can even write a program to capture a few or a few areas of the test key 200 for comparison to get more information about the pros and cons of the process. The scanning electron microscope 250 of the present invention, which directly monitors the advantages and disadvantages of the semiconductor manufacturing process, also has an autofocus system (not shown). The alignment mark on the wafer can be used to automatically search and scan specific areas. Test key 200. The scanning electron microscope 250 of the present invention that directly monitors the pros and cons of a semiconductor process can also be provided with a CD ROM (not shown) for transmitting measured data of each process stage of the component for comparison. The scanning electronic microscope 250 of the present invention, which directly monitors the advantages and disadvantages of the semiconductor manufacturing process, can also be equipped with a printing system (not shown), which can print out the detection results of each batch of products. In addition, the test key 200 on the chip 240, in addition to the comb-type test key structure shown in FIG. 3, for detecting bridges between metal wires, includes, for example, polysilicon capacitors, bridges between polysilicon, Process control and monitoring structures related to the pros and cons of semiconductor processes, such as bridges between inner polysilicon layers, characteristics of contact windows or vias, bridges between metal lines, bridges between inner metal layers, etc., that is, process control currently used in semiconductor factories The monitoring structure is listed here. ^^ 1- ^^^ 1 ^^^ 1 —tn msn ^ l 1 ^ 1 ^^^ 1 s-6 (Please read the precautions on the back before filling this page) The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 43 9〇A7 4674twf.doc / 008 D_D / V. Description of the invention (L)) Figure 4A shows the test bond for measuring the characteristics of the dielectric layer. Figure 4B is a schematic cross-sectional view of the structure of Figure 4A along the IV-IV direction. Please refer to FIGS. 4A and 4B at the same time. The test key structure for detecting the characteristics of the dielectric layer is a surface of a conductive layer 400 to form a dielectric layer 402 whose characteristics are to be detected, and then the dielectric layer The surface of 402 is formed—the conductive layer 504. Wherein, the conductive layer 400 is grounded, and the method for forming the ground is, for example, bringing the conductive layer 400 into contact with the substrate of the wafer, and the conductive layer 404 is maintained in an electrically floating state. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative Co., Ltd. (Please read the precautions on the back before filling this page) This is a conductive layer 400 in the test key structure used to test the characteristics of the dielectric layer, such as using a semiconductor substrate , A polycrystalline silicon layer or a metal layer, and the conductive layer 404 is, for example, a polycrystalline silicon layer or a metal layer. Generally speaking, the conductive layers 400 and 404 are conductive layers used successively in a semiconductor process. The dielectric layer 402 whose characteristics are to be detected includes the dielectric layers used in the semiconductor manufacturing process, such as Gate Oxide Layer and Inter-Layer Dielectrics (ILD). Electrical layer, Inter-Poly Dielectrics (IPD) and Inter-Metal Dielectrics (IMD). During the inspection, a wafer having the test key structure for detecting the characteristics of the dielectric layer is placed in the scanning electron microscope 250 of the present invention, which directly monitors the pros and cons of the semiconductor process. If the characteristics of the dielectric layer 402 are good, The conductive layers 400 and 404 will form a good electrical insulation. When the electron beam scanning is performed, the conductive layer 404 is at the paper scale because the conductive layer 400 is grounded and the Chinese National Standard (CNS) A4 specification (2! 0 X 297) is applied. (Mm) 43 43 A7 B7 4674twf.doc / 008 V. Description of the invention (#) Electrically floating state 'Therefore, the images of the conductive layers 400 and 404 observed from the scanning electron microscope 250 will have a strong Light and dark contrast. ---------- Installation— (Please read the precautions on the back before filling this page) Conversely, if the characteristics of the dielectric layer 402 are not good, and the conductive layers 400 and 404 cannot form good electrical insulation , When the electron beam scanning is performed, the conductive layer 400 and the conductive layer 404 will be in the same potential state, so the images of the conductive layers 400 and 404 observed from the scanning electron microscope 250 will no longer have Strong light and dark contrast. FIG. 5 is a schematic top view of a test key structure for detecting whether a bridging phenomenon occurs between adjacent conductive layers. Please refer to FIG. 5. This test key structure for detecting whether a bridging phenomenon occurs between adjacent conductive layers is formed above a conductive line 500 with a meander pattern, forming and forming a conductive line. The serpentine patterned conductive line 500 has another serpentine patterned conductive line 502 in a different serpentine direction, and between this conductive line 500 and 502 with a serpentine pattern, a pattern having the same pattern as the serpentine patterned conductive line 502 is formed. The dielectric layer has an insulating property. In this way, the conductive wire 500 having the meandering pattern is not completely covered by the conductive wire 502 having the meandering pattern, and a part of the surface is exposed. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed the conductive wire 500 with a meandering pattern in a grounded state, and the method for forming the ground is, for example, connecting the conductive wire 500 with a meandering pattern to a wafer. The substrate is in contact, and the conductive line 502 with the meandering pattern is maintained in a state of being electrically floating. This is used to test whether there is a bridge phenomenon between adjacent conductive layers. The conductive wire 500 with a meandering pattern in the test key structure, for example, this paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 43 90 A7 4 6 7 4 twf. Doc / 0 0 8 V. Description of the invention ((0 means polycrystalline silicon wire, metal wire, or directly using a semiconductor substrate, and the conductive wire 502 with a meandering pattern, such as polycrystalline silicon wire or metal wire In general, the conductive lines 500 and 502 with a meandering pattern are conductive lines used in the semiconductor manufacturing process. When testing, there will be a test key to detect whether a bridge phenomenon occurs between adjacent conductive layers. A wafer with a structure is placed in the scanning electron microscope 250 of the present invention for directly monitoring the pros and cons of a semiconductor process. If the conductive wire 500 having a meandering pattern is not bridged with 502, the conductive wire 500 having a meandering pattern 500 It will form a good electrical insulation with 502. When the electron beam scanning is performed, the conductive line 500 with a meandering pattern is grounded and the The conductive wire 502 is in an electrically floating state, so the images of the conductive wires 500 and 502 with a meandering pattern observed from the scanning electron microscope 25 will have a strong light and dark contrast. Conversely, if it has When the conductive lines 500 and 502 of the meandering pattern are bridged, the conductive wires 500 and 502 having the meandering pattern cannot be printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs — ^ — '^^^ 1 ^ ^^ 1 ^^^ 1 i ^ l ^ ii ^ it —an 1 · ^ — {Please read the precautions on the reverse side before filling out this page) To form a good electrical insulation, you have to The meandering pattern of the conductive lines 500 and 502 will be at the same potential. Therefore, the images of the meandering pattern of the conductive lines 500 and 502 viewed from the scanning electron microscope 250 will be There is no longer a strong light-dark contrast. Figure 6 is a schematic top view of the test key structure used to detect the continuity of the conductive wire. Please refer to Figure 6, this test key used to detect the continuity of the conductive wire China National Standard (CNS) A4 Specification < 210X297 Public Shame) 43 43 Printed by the Consumers ’Cooperative of the Ministry of Economic Affairs of the Ministry of Finance 4674twf.doc / 008 A? B7____ V. Description of the invention (() Structure defines a metal layer (not shown) into a conductive wire 600 with a meandering pattern, and two Test pads 602 and 604 respectively coupled to terminals of the conductive wire 600. The test pad 602 is in a grounded state, and a method for forming a ground, such as forming the test pad 602 and a substrate of a wafer Contact, and the test pad 604 is maintained in an electrically floating state. The conductive wire 600 and the two test pads 602 and 604 in the test key structure for detecting the continuity of the conductive wire are defined by, for example, a polycrystalline silicon layer or a metal layer. During the inspection, a wafer having the test key structure for detecting the continuity of the conductive wire is placed in the scanning electron microscope 250 of the direct monitoring semiconductor process of the present invention. If the conductive wire 600 has a meandering pattern, When the continuity is not abnormal, when the conductive wire 600 with a meandering pattern is scanned by the electron beam, the conductive wire 600 and the two test pads 602 and 604 will be in the same potential state. The image of the conductive wire 600 and the two test pads 602 and 604 seen by the electron microscope 250 will not have a strong light and dark contrast. Conversely, if the continuity of the conductive wire 600 having a meandering pattern is abnormal, that is, when the conductive wire 600 having a meandering pattern is broken, then when the electron beam scanning is performed, from the break to the test pad 602 The portion of the conductive wire 600 and the portion of the conductive wire 600 from the fracture to the test pad 604 will be maintained in a state where the test pad 604 is electrically floating because the test pad 602 is in a grounded state, causing scanning. Conductive wire 600 and two test pads 602 and 604 as observed in a type electron microscope 250 ^^ 1. I-I Η---I -II ^^^ 1 ^^^ 1 ^^^ 1 n ^ ii ^ ^^ 1 ^^^ 1 ^^^ 1, 5J (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (21〇 × 297mm) Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives 43 9096 4e74twf.doc / 008 A1 B7 V. The image of the invention description (〇) will have a strong light and dark contrast. FIG. 7 is a schematic cross-sectional view of a test key structure for detecting the characteristics of a contact window or an interlayer window. Please refer to Figure 7 * This test key structure used to detect the characteristics of contact windows or interlayer windows refers to the meandering structure formed by coupling 704 between two adjacent conductive wires 700 and 702, and the conductive wires One end of 700 is coupled to the test pad 706, and one end of the conductive wire 702 is coupled to the test pad 708. Among them, the test pad 706 is in a grounded state, which forms a method of grounding. For example, the test pad 706 is brought into contact with the substrate of the wafer, and the test pad 708 is maintained in an electrically floating state. The conductive wires 700 and 702 and the two test pads 706 and 708 in the test key structure for detecting the characteristics of a contact window or an interlayer window are formed by defining a polycrystalline silicon layer or a metal layer, for example. During the inspection, a wafer having the test key structure for detecting a contact window or an interlayer window is placed in the scanning electron microscope 250 of the present invention that directly monitors the pros and cons of the semiconductor process. If the characteristics of the plug 704 are not different, In this state, during the electron beam scanning, the conductive wire 702 and the two test pads 706 and 708 will be at the same potential. Therefore, the image of the conductive wire 702 observed from the scanning electron microscope 250, There will be no strong contrast between light and dark. Conversely, if the characteristics of the plug 704 are abnormal, that is, when the opening of the plug 704 characteristic occurs, the portion of the conductive wire 702 from the open circuit to the test pad 706 and The part of the conductive line 702 from the open circuit to the test pad 708 will be caused by ml- ^^^ 1 ^^^ 1 ^^^ 1 · ί · ί it ^^-" ^^^ 1 ^^^ 1 In ^^^ 1 ^^^ 1 '一 -SJ (Please read the precautions on the reverse side before filling out this page) This paper size applies to the China National Standard (CNS > A4 size (210X297 mm) 439096 4674twf.doc / 008 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (β) The test pad 708 is maintained in a grounded state while being electrically floating, resulting in the scanning electron microscope 250 The observed image of the conductive line 702 will have a strong light and dark contrast. In addition, the structures shown in Figures 4A, 4B, 5, 6 and 7 can be made with different sizes, so it will be clear in a series of different The advantages and disadvantages of the process capability under the size structure. The present invention discloses a scanning type that directly monitors the advantages and disadvantages of a semiconductor process. The sub-microscope uses the passive voltage contrast effect to scan the test key for process control monitoring with one end grounded and one end electrically floating, and thereby test the strength of the surface electronic signal generated by the key surface, or the surface The contrast of the image displayed by the strength of the electronic signal is used to determine the pros and cons of the relevant process for making this test key. With the present invention, the process inspection can be performed directly on the production line, so the time required for product production can be reduced, or the development can be studied The required cycle time. It is particularly noted that at present, there is no machine that can directly apply special functions on the line, so the present invention is really original. Using the present invention, the process inspection can be directly performed on the production line, so the wafer can be reduced. Contamination or damage. Another feature of the present invention is that the detection is a non-destructive detection, so it can be applied to many semiconductor structures that require non-destructive detection. Because of the use of imaging results to identify The method is very clear and obvious, so using the invention, it can be used easily and quickly 20-* J (Please read the notes on the back before filling this page) This paper size is applicable to China National Standards (CNS) A4 specifications (210X297 mm) A7 B7 4 3 90 96 674twf .doc / 008 V. Description of the invention (q) The present invention can be used to test the test key of the process control and monitoring structure currently used in semiconductor factories. As long as it has such a circuit design with one end grounded and one end floating, the present invention can be used To complete the inspection or bursting work, such as polycrystalline silicon or metal line spacing series to monitor the various structures of the process capability, and then learn the pros and cons of each stage of the process. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. ----------.- 4.— (Please read the notes on the back before filling out this page) * 11. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 21 This paper is used in China Standard Soap (CMS) A4 Specification (210X297mm >