經濟部中央標準局員工消費合作社印掣 4443 1 5 五、發明説明（/ ) (一) 發明領域： 本發明係有關1獅於掃描電子顯微娜像檢測 之半導雔元件之測試結構，對於次微米半導體元件與 一些特殊半導體元件結構，利用掃插電子顯微鏡 (SEM ; Scanning election microscope)量測臨界尺寸之 元件圖案時，由於將聚集在半導體絕緣層上的電荷輸 通掉，所以不會造成SEM影像變形、扭曲。 (二) 發明背景： 製造積館電路，首先在政晶片上形成半導體元件， 接下來，在元件上形成多層金屬連線網，並與其活性 元素(active element)接觸及連線以製造出所需的電路。 說明如下：首先，沈積第一絕緣層在分開的元件上， 再利用活性離子蝕刻(RIE ; Reactive»Ion-Etching)技術 在此絕緣層上形成一接觸窗，然後再沈積導截材料在 該接觸窗上，接下來，利用RIE技術蝕刻該導體材料， 用以在元件接觸區之間形成第一金靥連線；接下來再 沈積第二絕緣層，以及第二導體層，利用活性離子蝕 刻技術製作第二金屬連線在第二絕緣層上，並且，經 由接觸窗到第一層上。視稹體電路的複雜度而言，通 常需交替沈積2-4層金屬層以製作成完整的金靥連線， 並連接外部接腳形成元整的矽晶片。 一般而言，需要極緊密的空間控制，才能在次微米 範圍內製作高集密度的電路元件；在製程過程條件 中’微小的變因條件，即可造成巨大的空間變因；因 „ i------ΐτ (請先閱讀背面之注意事項再填寫"頁) ϋ度適财國财料（CNS) A4規格（2獻297公- 4 443 彳 5 a? B7 經濟部中央螵準局員工消費合作社印褽 五、發明説明（二） 此，最後需借由髙靈敏度的檢測方法去確定所設計電 路元件圖案的尺寸和結構。 對於檢測次微米尺寸範圍的圖案，掃描電子顯微鋳 (SEM > Scanning Electron Microscope)是最可行的工 具。因爲光學顯微鏡，受限於其工作原理，其乃是利 用光波做爲探測工具，而對於次微米元件而言，將無 法淸楚的將元件圖案精確顯現，除此，SEM亦能顯示 製程過程中的缺點（例如：經由飩刻接觸窗時而產生 的碎片或堆積物......等等），而光學顯微鏡(Optical microscopy)則無法銜陋fj。 SEM之運作原理主要是將待測樣品置放在一眞空反 應室內，並利用電子束撞擊該待測樣品以顯示出該樣 品之表面影像，一般而言，被檢測的樣品表面範圍在 SEM內必需要有電性接地。主要是输導由撞擊電子束 聚集在樣品表面上的電子，以避免再撞擊的電子束與 聚集在樣品表面上的電子之間相互的干擾，而造成 SEM顯示的影像扭曲變形》早期的SEM具有一較小的 反應室，用以接受較小的樣品，該樣品經由傳導性良 好的銀膠貼放在一鋁座上，形成良好的接地；因此， 當樣品的絕緣層（例如：Si〇2或光阻）爲一曝露受探測 表面層時*則在樣品表面會形成區域充電（電子堆 積），特別是爲了提髙SEM影像解析度時，需提高電 子束之加速電壓，該區域充電現像則更加明顯，易加 造成影像歪曲變形。爲了解決該問題，一般是在樣品 ---r r— II---- 良一------ HI τ ίΊ-s (請先閱讀背面之注意事項再填寫本頁) 本紙浪尺度適用中画國家標準（CNS ) A4規格（210X 297公釐） 444315 A7 經濟部中央標策局員工消费合作社印裝 五、發明説明（二） 放入顯微鏡做檢測前，先在樣品表面上濺鍍一層黃金 薄膜，以提供一條電子放電的路徑。請參考美國專利 第5,460,034號由Herrick等人所掲露的結果，量测 AlGaAs/GaAs時，若沈積約60埃一100埃的黃金薄膜在 樣品之絕緣外層上，則可減少充電現象。 以目前的技術而言，已經允許較大樣品放入SEM 內，例如：完成部份製程步驟的整個晶片可先被SEM 檢測之後，再回到生產線上繼續完成製程步驟。SEM 可檢測光阻影像或與蝕刻圖形檢測出任何在製程過程 中的殘餘物或碎片。在製程過程中重覆的檢測製程步 驟*較易掌握產品的品質》但，爲了要檢測每一非導 性層結構則必需在一非導性材質上鍍上一層金膜或其 它導體膜，而此步驟將改變受測元件結構，所以我們 要在不影響受檢測元件結構之前提下，又能输導堆積 於絕緣層上的電子以防止樣品充電造成SEM呈現的影 像扭曲變形情形下來使用SEM 〇 —般而言’無法利用SEM正確檢測及測量積體電路 元件小方塊(dice)的圖案，主要是受限於積館電路中ρ-π 接面和絕緣層，因爲p-n接面和絕緣層的位能障，阻礙 了其堆積電子接地連接，而使得電子堆積充電現象發 生而影響到SEM圖像。除此，來自SEM電子束的電 子，若使元件區域（例如：場效電晶體閘極）充電， 嚴重的*甚至將毀壞閘極底下的閘氧化層，所以唯有 解決此一充電現象才能使用SEM。請參考美國專利第 ____5_____ 本紙張尺度顧中關家標準（CNS > Α4· ( 210X297公瘦) ~ -ft - - ί —I------ 作^--- -—[ - i In ^ (請先閣讀背面之注意事項再填寫本f ) 4443 1 5 A7 1______ B7 經濟部中央標隼局員工消費合作社印策 五、發明説明（丄） 5,3糾,268號，由Lur等人揭露出一種利用高能量離子佈 植時，處理充電的方法，主要係利用在佈植前，先在 樣品上鍍上一層鈦金屬層薄膜，再行離子佈植，之後 再利用乾蝕刻或濕化學蝕刻技術移去該鈦金靥層薄 膜。顯然，該方法不適合SEM檢測具有金靥線/絕緣 層多層交互沈積結構的半導體元件圖案。 (三)發明的簡單說明： 本發明的主要目的提供一種用於掃描電子顯微 鏡(SEM)影像檢測之半導體元件測試結構，首先，在一 基板上沈積一中間介電層(ILD ; Inter Layer Didectrive)，然後在ILD層上開一接觸窗，並露出部份 基板，在接觸窗內沈積傳導層，之後，再沈積第一金 屬層在ILD及接觸窗上；再沈積一絕緣層，並在絕緣層 上開一接觸窗口，露出部份第一金屬層，除此，基板 的表面與S£M接地線相連；由此，聚集在ILD絕緣層上 的電荷，將會利用其接觸窗內的傳導層，形成一傳導 通道，將聚集ftILD表面上的電荷疏通掉。 本發明的另一目的在於提供一種用於SEM影像_ 之半導體元件測試結構；基板經由一接點與SEM接地 線連接；在基板上形成閘極氧化層，在閘極氧化層上 形成無攙雜的第一複晶矽層，經由微影蝕刻技術在閘 極氧化層和第一複晶矽層上形成一埋藏式接觸窗口； 並露出部份基板，該接觸窗上再沈積一複晶矽層，複 晶矽層充滿接觸窗內，利用微影蝕刻技術，選擇性的 (請先閱讀背面之注意事項再填寫本頁Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4443 1 5 V. Description of the invention (/) (I) Field of the invention: The present invention relates to the test structure of a semiconducting element for the detection of a scanning electron microscope image. For sub-micron semiconductor devices and some special semiconductor device structures, when a critical-size device pattern is measured using a scanning electron microscope (SEM; Scanning election microscope), the charges accumulated on the semiconductor insulating layer are transmitted, so they will not cause SEM images are distorted and distorted. (II) Background of the Invention: To manufacture a building circuit, a semiconductor element is first formed on a political wafer. Next, a multilayer metal connection network is formed on the element, and it is contacted with and connected to the active element to produce the required Circuit. The description is as follows: first, a first insulating layer is deposited on a separate component, and then a contact window is formed on the insulating layer by using reactive ion etching (RIE; Reactive »Ion-Etching) technology, and then a guide material is deposited on the contact On the window, next, the conductive material is etched using RIE technology to form a first Au-bond connection between the contact areas of the element; next, a second insulating layer and a second conductive layer are deposited, using active ion etching technology A second metal wire is fabricated on the second insulating layer, and is passed onto the first layer through the contact window. Depending on the complexity of the body circuit, it is usually necessary to alternately deposit 2-4 metal layers to make a complete gold wire, and connect external pins to form a complete silicon chip. Generally speaking, extremely tight space control is required to produce high-density circuit components in the sub-micron range; in the process conditions, 'small variable conditions can cause huge spatial variables; because „i- ----- ΐτ (Please read the precautions on the back before filling in the " page) ϋ Degrees of wealth and wealth (CNS) A4 specifications (2 offer 297-4 443 彳 5 a? B7 Central Ministry of Economic Affairs Employees' Cooperatives of the Bureau of the People's Republic of China 5. Description of Invention (2) Therefore, the size and structure of the designed circuit element pattern must be determined by the method of “sensitivity detection.” For the detection of patterns in the sub-micron size range, scanning electron microscopy (SEM > Scanning Electron Microscope) is the most feasible tool. Because the optical microscope is limited by its working principle, it uses light waves as a detection tool, and for sub-micron components, it will not be able to understand the component. In addition to the accurate pattern display, in addition, SEM can also show the defects in the process (such as: fragments or deposits produced by engraving the contact window ... etc.), and optical microscopy (Optical mi croscopy) cannot be used as a fj. The operating principle of SEM is mainly to place the sample to be tested in an empty reaction chamber, and use an electron beam to strike the sample to be displayed to display the surface image of the sample. Generally speaking, it is tested The surface area of the sample must be electrically grounded in the SEM. It is mainly to conduct the electrons collected on the sample surface by the impacting electron beam to avoid mutual interference between the re-impacted electron beam and the electrons collected on the sample surface. "The distortion of the image displayed by the SEM" Early SEM had a smaller reaction chamber to accept a smaller sample, which was placed on an aluminum base via a good conductive silver glue to form a good ground ; Therefore, when the sample's insulating layer (such as SiO2 or photoresist) is an exposed surface layer *, area charging (electron accumulation) will form on the sample surface, especially to improve the SEM image resolution It is necessary to increase the acceleration voltage of the electron beam, and the charging phenomenon in this area is more obvious, which will easily cause distortion and deformation of the image. In order to solve this problem, it is generally in the sample --- rr- II- --- Liangyi ------ HI τ ίΊ-s (Please read the notes on the back before filling in this page) The paper scale is applicable to the National Standard for Chinese Painting (CNS) A4 (210X 297 mm) 444315 A7 Economy Printed by the Consumer Cooperatives of the Ministry of Standards and Standards of the People's Republic of China. 5. Description of Invention (2) Before putting into the microscope for testing, a gold film is sputtered on the surface of the sample to provide a path for electronic discharge. According to the results disclosed by Herrick et al., When measuring AlGaAs / GaAs, if a gold film of about 60 angstroms to 100 angstroms is deposited on the insulating outer layer of the sample, the charging phenomenon can be reduced. According to the current technology, larger samples have been allowed to be placed in the SEM. For example, the entire wafer that has completed part of the process steps can be inspected by the SEM before returning to the production line to continue the process steps. SEM can detect photoresist images or etched patterns to detect any residue or debris during the process. Repeated inspection process steps during the manufacturing process * It is easier to grasp the quality of the product. "However, in order to detect each non-conductive layer structure, a non-conductive material must be plated with a gold film or other conductive film, and This step will change the structure of the device under test, so we need to lift it before it affects the structure of the device under test, and can conduct electrons deposited on the insulating layer to prevent the distortion of the image presented by the SEM when the sample is charged. SEM is used. -Generally speaking, the pattern of dice of integrated circuit components cannot be detected and measured correctly by SEM, which is mainly limited by the ρ-π junction and insulation layer in the museum circuit, because the pn junction and insulation layer Potential barriers prevent the stacked electrons from connecting to ground, which causes the electrons to accumulate and charge, which affects the SEM image. In addition, if the electrons from the SEM electron beam charge the element area (such as the field effect transistor gate), the gate oxide layer under the gate will be severely destroyed, so it can only be used if the charging phenomenon is solved. SEM. Please refer to U.S. Patent No. ____5_____ Guzhongguan Standard for Paper Size (CNS > Α4 · (210X297 male thin) ~ -ft--ί —I ------ 作 ^ --- -— [-i In ^ (Please read the precautions on the back before filling in this f) 4443 1 5 A7 1______ B7 Imprint by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the Invention (印) No. 5,3, No. 268, by Lur Et al. Revealed a method of processing and charging when using high-energy ion implantation, mainly using a titanium metal layer film on the sample before implantation, and then ion implantation, and then dry etching or The wet chemical etching technique removes the titanium Au film. Obviously, this method is not suitable for SEM inspection of semiconductor element patterns with Au / wire multilayer insulation deposition structure. (3) Brief description of the invention: The main purpose of the present invention is to provide A semiconductor element test structure for scanning electron microscope (SEM) image inspection. First, an intermediate dielectric layer (ILD; Inter Layer Didectrive) is deposited on a substrate, then a contact window is opened on the ILD layer, and the exposed portion is exposed. Copies of substrates in contact windows A conductive layer is deposited, and then a first metal layer is deposited on the ILD and the contact window; an insulating layer is deposited, and a contact window is opened on the insulating layer to expose a portion of the first metal layer. In addition, the surface of the substrate and The S £ M ground wire is connected; thus, the charge accumulated on the ILD insulation layer will use its conductive layer in the contact window to form a conductive channel to clear the charge on the surface of the accumulated ftILD. Another aspect of the invention The purpose is to provide a semiconductor device test structure for SEM image_; the substrate is connected to the SEM ground line through a contact; a gate oxide layer is formed on the substrate, and a first doped polycrystalline silicon is formed on the gate oxide layer Layer, forming a buried contact window on the gate oxide layer and the first polycrystalline silicon layer by lithography etching technology; and exposing part of the substrate, a polycrystalline silicon layer is deposited on the contact window, and the polycrystalline silicon layer is full Inside the contact window, using lithographic etching technology, selective (Please read the precautions on the back before filling in this page
1T 本紙張尺度適用中國國家揉準（CNS ) A4规格（210 X 297公釐） ,經濟部中央嘌準局員工消资合作社印絮 4443 1 5 A7 __ B7 五、發明説明（） 保留部份複晶矽層，以形成複晶矽線條，在複晶矽線 條和部份閘極氧化層上再沈稹一絕緣層，並利用微影 蝕刻技術在絕緣層上開一接觸窗，露出部份複晶砍 層；當SEM檢測絕緣層上的接觸窗口尺寸時，有利電 子經由埋藏式接觸窗口傳導到SEM接地上。 本發明的另一目的嫌提供一種用於SEM影像檢測 之半導體元件測試結構；此待測試結構（含有導電圖 樣）可連接額外導電區域以疏導由於充電現象所堆積 的電荷，而此待測結構可構建於晶片切割消耗區（元 件完成後，由於切割晶片所消耗掉的區域）或晶片中 的測試區。 本發明的另一目的在於提供一種用於SEM影像檢測 之半導體元件測試結構；以SEM來檢測用蝕刻形成的 接觸窗口的品質。 (四)圖示的簡單說明： 圖(1)係爲矽晶片上視示意圖。 圖(2)係爲本發明一種用於SEM影像檢測之半導體元件 測試結構獅圖。 圖(3a)和(3b)係爲本發明一種用於SEM影像檢測之半導 體元件測試結構上視示意圖。 圖(4)係爲本發明一種用於SEM影像檢測之半導髏元件 測試結構窗湎圖。 圖(5a)和(5b>係爲本發明一種用於SEM影像檢測之半導 體元件測試結構上視示意圖》 u --丨： - - - I II τ Ά--I 11 I Τ. (請先聞讀背面之注意事項再填寫本頁} 本纸張尺度適用中國囤家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 4443 1 5 五、發明説明（) 發明的詳細說明： 首先，請參考圖一所示，係說明在砂晶片基板10表面上 形成半導體元件，其元件圖案包括一規則排列的積體電路 元件小方塊(dice)62，各種的測試結構同時在小方塊62之間 的狹窄區域60中形成，因爲區域60乃可消耗之元件間切割 區域，當製程完成後，切開狹窄區域仰，即可將每個積體 電路元件小方塊(dice)分開。一般而言，是用SEM來檢測積 體職元件結構之尺寸和結働密集度。 請參考圖2及圖3 A和3 B所示，係爲本發明第一個實 施例*係說明於一 P型矽基板10 (晶片），矽晶片基板10 經由歐姆電接點8接到SEM接地線上，歐姆電接點8製作 在矽晶片基板10的背面上，首先，在用來當作SEM檢測之 矽晶片基板10上，沈積一絕緣層82，然後用活性離子蝕刻 在絕緣層82上，開接觸窗口L、Μ、N、Ο、P，並露出部份 基板10，L、Ν，Ρ接觸窗口下的露出基板10部位爲n+型區 域，而Μ、0下的獬出基板10部位則爲p+型1[域，位於接觸 窗口L、Ν、Ρ下的η+型區域，與ρ型基板形成p-η接面，由 於ρ-η接面的形成將阻止電子流向接地而形成電子堆積充電 現象，而於Μ、0接觸窗口區域則可經由Ρ+區域而將電子輸 通至接雌》而不致發生充電驗- 請參考圖3Α，我們使用SEM來檢測接觸窗口，將發現 由於L、Ν、Ρ下的p-η接面，導致的充電現象，將造成L、 Ν、Ρ與Μ、〇的明暗度不同，而易於辨識此間隔式的明暗 ____8_；_____ 本紙張尺度適用中國國家‘準（CNS ) Α4規格U10X297公釐） " (請先閱讀背面之注意事項再填寫本頁) 訂1T This paper size is applicable to China National Standards (CNS) A4 (210 X 297 mm), printed by the Consumer Purchasing Cooperative of the Central Purification Bureau of the Ministry of Economic Affairs 4443 1 5 A7 __ B7 5. Description of the invention () A crystalline silicon layer is formed to form a polycrystalline silicon line. An insulating layer is further deposited on the polycrystalline silicon line and a part of the gate oxide layer, and a contact window is opened on the insulating layer using a lithography etching technique to expose a part of the polycrystalline silicon line. Crystal cut layer; when the SEM detects the size of the contact window on the insulating layer, favorable electrons are conducted to the SEM ground through the buried contact window. Another object of the present invention is to provide a semiconductor device test structure for SEM image detection; the structure to be tested (including conductive patterns) can be connected to an additional conductive region to dissipate the charge accumulated due to the charging phenomenon, and the structure to be tested can be Built in the wafer dicing consumption area (the area consumed by dicing the wafer after the component is completed) or the test area in the wafer. Another object of the present invention is to provide a semiconductor device test structure for SEM image inspection; use SEM to inspect the quality of a contact window formed by etching. (IV) Brief description of the figure: Figure (1) is a schematic diagram of the top view of a silicon wafer. Figure (2) is a lion diagram of a semiconductor device test structure for SEM image inspection of the present invention. Figures (3a) and (3b) are schematic top views of a semiconductor device test structure for SEM image inspection according to the present invention. Figure (4) is a window view of a test structure of a semi-conductive cross element for SEM image detection according to the present invention. Figures (5a) and (5b > are schematic top views of a semiconductor device test structure for SEM image inspection according to the present invention "u-丨:---I II τ Ά--I 11 I Τ. (Please listen first Please read the notes on the back and fill in this page again} This paper size is applicable to the Chinese Standard for Storehouse (CNS) A4 (210X297mm) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4443 1 5 V. Description of the invention () Detailed description: First, please refer to FIG. 1 to describe the formation of semiconductor elements on the surface of the sand wafer substrate 10. The element pattern includes a regularly arranged integrated circuit element dice 62. Various test structures are simultaneously The narrow area 60 between the small blocks 62 is formed because the area 60 is a consumable cutting area between the components. After the process is completed, the narrow area is cut to separate each integrated circuit component dice. In general, SEM is used to measure the size and crust density of the integrated component structure. Please refer to FIG. 2 and FIGS. 3 A and 3 B, which is the first embodiment of the present invention. P-type silicon substrate 10 (chip), silicon The chip substrate 10 is connected to the SEM ground line through an ohmic electrical contact 8. The ohmic electrical contact 8 is fabricated on the back of the silicon wafer substrate 10. First, an insulating layer is deposited on the silicon wafer substrate 10 used for SEM inspection. 82, and then use active ion etching on the insulating layer 82 to open the contact windows L, M, N, 0, and P, and expose part of the substrate 10, L, N, P. The exposed substrate 10 under the contact window is an n + type region , And the substrate 10 at M and 0 is a p + type 1 [domain, which is located in the η + type region under the contact windows L, N, and P, and forms a p-η junction with the ρ-type substrate. The formation of the junction will prevent the electrons from flowing to the ground and form the phenomenon of electron accumulation and charging, while the contact window area at M and 0 can pass the electrons to the female through the P + region "without the charging test-please refer to Figure 3A, We use SEM to detect the contact window. We will find that the charging phenomenon due to the p-η junction under L, N, and P will cause the lightness and darkness of L, Ν, and P to be different from M and 〇, and it is easy to identify this interval. The type of light and shade ____8_; _____ This paper size applies to China's National Standard (CNS) Α4 Specifications U10X297 mm) " (Please read the precautions on the back before filling this page) Order
^I 經濟部中央標準局員工消费合作社印f 4443 1 5 Λ7 A ； ____ B7 五、發明説明（7) 接觸窗口，所代表之不同的n+型ffi域與p+型區域，以及有 無殘留物於接觸窗口中》 請參考圖3B，則由於接觸窗口並不是蝕刻的非常好， 以致有殘留物於接觸窗口中，則將發生電荷堆積充電現 象，而使用SEM來檢測接觸窗口的圖案，無法分辨出明 暗，即L、N、P與μ、〇的明暗度相同》 請參考圖4及圖5Α和5Β，係爲本發明第二個實施例 (利用與第1例同樣的原理來檢測接觸窗口），係說明， 於一 Ρ型矽基板10 (晶片），矽晶片基板10經由歐姆電接 點8接到SEM接地線上，歐姆電接點製作在矽晶片基板10 的背面，首先，在用來當作SEM檢測之矽晶片基板1(ί的區 域上沈積一矽化金屬餍84,通常是矽化鈦（TiSii)，但也 可以是矽化鎢、矽化鉬、矽化鉅、矽化白金、矽化鈷等材 料，然後再沈積一絕緣層82於矽化金屬層84上，利用活性 離子蝕刻在絕緣層82上，開接觸窗口L、Μ、N、Ο、P，露 出部份矽化金屬層84 ,而L·、Ν、Ρ接觸窗口下的基板10區 域爲η +型區域，而Μ、0下的麵10區域則爲ρ+型區域。 請參考圖5Α所示，當以SEM檢測接觸窗口時，將看到 相等明暗度的圖案，而與其窗口下的基板10區域爲ιΓ型區 域或Ρ+型區域，此乃是因爲在各接觸窗口(L、Μ、Ν、Ο、 Ρ)的電子堆積，可由矽化金屬層84與其下的矽晶片基板 10，經由歐姆電接點8接到SEM接地線上放電，而得到解 決。 9 ' I! - I 1IH - t HI -I ! I ^ i/ϋ 11! 1--I - - —t^i {請先閲讀背面之注意事項再填寫表I ) 本紙乐尺度適用中國國家標準（CNS ) Α4規格U i 0 X 297公釐） 4 443 1 5 a? 87 經濟部中央樣準局員工消費合作杜印掣 五、發明説明（，/ ) 請參考圖5B，則由於位於接觸窗口下的露出部份妙化 金靥層84被蝕刻物所穿透，而露出部份矽晶片基板10，貝!1 接觸窗口L、N、P下的基板10區域將形成p-η接面導致充電 現象。而使得以SEM來檢測接觸窗口時，將造成L、N、P 窗口與Μ、0窗口的明暗度不同，而可辨識位於接觸窗口下 的η+型區域與ρ+型面域。 以下係以Ρ型矽晶片基板之實施例來閨述本發明，而 非限制本發明，並且熟知半導髏技藝之人士皆能明瞭，適 當而作些微的改變及調整，仍將不失本發明之要義所在， 並不脫離本發明之精神和範圍。 (請先閲讀背面之注意事項再填寫本頁) 訂 气！ 本紙張尺度適用中CNS) Α4規格（21〇χ297公餐^ I Consumption Cooperative of Employees of the Central Standards Bureau of the Ministry of Economic Affairs f 4443 1 5 Λ7 A; ____ B7 V. Description of the invention (7) The contact window, which represents the different n + type ffi domains and p + types, and whether there are residues in contact In the window >> Please refer to Figure 3B. Because the contact window is not very well etched, so that there is a residue in the contact window, a charge accumulation and charging phenomenon will occur, and the pattern of the contact window cannot be distinguished by using SEM. That is, the lightness and darkness of L, N, P are the same as those of μ and 0. Please refer to FIG. 4 and FIGS. 5A and 5B, which is the second embodiment of the present invention (using the same principle as the first example to detect the contact window), It is explained that, on a P-type silicon substrate 10 (wafer), the silicon wafer substrate 10 is connected to the SEM ground line through an ohmic contact 8. The ohmic contact is made on the back of the silicon wafer substrate 10. First, it is used as A silicon silicide metal 84, usually TiSii, is deposited on the silicon wafer substrate 1 (the area detected by SEM), but it can also be tungsten silicide, molybdenum silicide, silicide giant, platinum silicide, cobalt silicide and other materials, and then Sedimentary one The edge layer 82 is on the silicided metal layer 84, and the active layer is etched on the insulating layer 82 to open the contact windows L, M, N, 0, and P to expose a part of the silicided metal layer 84, and L ·, N, and P contact the windows. The area of the lower substrate 10 is an η + type area, and the area of the surface 10 under M and 0 is a ρ + type area. Please refer to FIG. 5A. When the contact window is detected by SEM, a pattern with equal lightness and darkness will be seen. The area of the substrate 10 under the window is a ιΓ-type region or a P + -type region. This is because the electrons in each contact window (L, M, N, 0, and P) can be deposited by the silicided metal layer 84 and below. The silicon wafer substrate 10 is connected to the SEM ground line through the ohmic contact 8 to discharge and is resolved. 9 'I!-I 1IH-t HI -I! I ^ i / ϋ 11! 1--I----t ^ i {Please read the notes on the back before filling in Form I) The paper scale is applicable to the Chinese National Standard (CNS) Α4 specification U i 0 X 297 mm) 4 443 1 5 a? 87 Central Procurement Bureau of the Ministry of Economic Affairs employee consumption Cooperation Du Yinhua V. Description of the invention (, /) Please refer to FIG. 5B, because the exposed metal layer 84 under the contact window is covered by The etched material penetrates and exposes a part of the silicon wafer substrate 10. The region of the substrate 10 under the contact windows L, N, and P will form a p-η junction and cause charging. When the SEM is used to detect the contact window, the lightness and darkness of the L, N, and P windows are different from those of the M and 0 windows, and the η + type region and the ρ + type region under the contact window can be identified. The following is an example of the P-type silicon wafer substrate to describe the present invention, but not to limit the present invention, and those who are familiar with the technology of semi-conducting crossbones will understand that appropriate changes and adjustments will still be made without losing the present invention. The gist of the invention does not depart from the spirit and scope of the present invention. (Please read the notes on the back before filling out this page) This paper size applies to CNS) Α4 size (21〇 × 297 meals)