CN102353697A - Defect on-line assessment method - Google Patents
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- CN102353697A CN102353697A CN2011102542716A CN201110254271A CN102353697A CN 102353697 A CN102353697 A CN 102353697A CN 2011102542716 A CN2011102542716 A CN 2011102542716A CN 201110254271 A CN201110254271 A CN 201110254271A CN 102353697 A CN102353697 A CN 102353697A
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Abstract
The invention discloses a defect on-line assessment method and is used for assessing nanometer-level defects such as whisker defects which are generated for metal deposits on a semiconductor substrate. The method at least comprises the following steps of: acquiring a surface roughness reference value for defect assessment; measuring the surface roughness of the semiconductor substrate to be measured; and comparing the surface roughness of the semiconductor substrate to be measured with the surface roughness reference value. By adoption of the defect on-line assessment method, labor resources can be saved, detection time can be reduced, the on-line assessment of the whisker defects is realized, and on-line defect information feedback is obtained, so that product yield is improved.
Description
Technical field
The present invention relates to the semiconductor fabrication process technical field, relate in particular to a kind of assessment method of semiconductor element whisker defective.
Background technology
Because integrated circuit is by ten hundreds of mostly, size needs just can watch the solid-state electronic element that obtains to combine by microscope, therefore can be described as microelectronic element again.If there is defective (defect), the electronic device failure of microelectronic element formation thus will be caused in the above-mentioned microelectronic element.And, when the semiconductor design specification is dwindled, improve and keep semiconductor technology yield difficulty more, and defective is for influencing one of important key of technology yield.Therefore, the Measurement and analysis of defective has significant relationship for the lifting of integrated circuit fine ratio of product.
In the semiconductor fabrication process process,, for example be that polycrystalline tungsten grid bottom can produce unnecessary nanoscale defective usually at the grid of MOS transistor; It for example is whisker (whisker) defective; This causes grid and connector short circuit, or short circuit between two plain conductors, or short circuit between two metal gates.The generation of whisker is because the misgrowth of metal material (like tungsten, aluminium, titanium, tungsten nitride or titanium nitride).More particularly, whisker is the thorn shape that produced by the misgrowth of metal material or the jut of dihedral.The reason that whisker produces is because some impurity that exists in the tungsten or the unevenness of metallic crystalline structure cause.Usually under two kinds of situation, produce, the one, after certain heat was accumulated stress, this whisker can occur; Another kind is that very thick metal film produces (for example greater than 1.5 μ m).
Existing in order to detect the defective in the semiconductor element; When carrying out the defects detection of semiconductor element, begin from the upper strata successively down to carry out etch process according to its order, the lower floor that makes defectiveness place layering one by one exposes; And each layer carried out observation analysis, up to proceeding to orlop.Yet, along with the increase of semiconductor integrated level, use said method check and analysis semiconductor element defective, will be difficult further especially for analyzing the defective that FEOL the caused whisker defective of grid and connector short circuit (as cause).Like application number is the one Chinese patent application of 200510023151.X; Method for affirming fatal fault in a kind of deep submicron semiconductor device is disclosed; Through the sample that will observe is carried out corrosion treatment; To obtain to be fit to sample surfaces with sem observation; This method need be carried out corrosion treatment to sample in advance; Complex procedures, and the method is not real-time online test method, slow usually to the defective feedback that occurs in the semiconductor devices production run.
And up to now, the production scene nearly all is to lean on artificial judgment to the detection of whisker.For this extremely small whisker defective; In the present semiconductor fabrication process process; Traditional mass measurement requires at test sample or produces the technology that a large amount of collection data are produced with explanation on the chip to satisfy the demands; Generally all be to take casual inspection; Obtain figure; For example from the chip slice map, choose 30 test points, carry out artificial judgment.Therefore, traditional method was both lost time, labor intensive, and have the limitation of artificial judgment.
Therefore, be badly in need of a kind of method, the risk that occurs whisker on the semiconductor devices metal deposit is carried out online (in-line) test and appraisal with reliable mode, obtain real-time whisker defective evaluating result.In this, should notice that the risk that whisker occurs is not limited to above-mentioned tungsten, also possibly appear on other metals such as aluminium, titanium, tungsten nitride or titanium nitride.
Summary of the invention
In order to realize online test and appraisal defective; Understand information this purpose of production technology and semiconductor device characteristic in real time; The present invention proposes a kind of method of online test and appraisal defective, is applicable to the whisker defective of metal gate or the whisker defective that is produced at semiconductor technology back segment metal connecting line.
A kind of method of online test and appraisal defective, the nanoscale defective that metal deposit produces on the Semiconductor substrate that is used to test and assess, said method comprises:
Obtain the surfaceness reference value of the defective that is used to test and assess;
Measure the surfaceness of Semiconductor substrate to be measured;
The surfaceness and the said surfaceness reference value of Semiconductor substrate to be measured are compared.
Optional, the said surfaceness reference value of obtaining the defective that is used to test and assess comprises:
Semiconductor substrate is provided;
Said Semiconductor substrate is carried out the electrical parameter test;
Test the surfaceness of said Semiconductor substrate;
Electrical parameter test result and surface roughness value are carried out data processing, obtain the surfaceness reference value.
Optional, the said surfaceness reference value of obtaining the defective that is used to test and assess comprises from the known Semiconductor substrate sample that does not produce defective obtaining.
Optional, said data processing comprises the least square fitting processing.
Optional, said electrical parameter test is carried out through on-line parameter test or selection test.
Optional, said electrical parameter test comprises open test or short-circuit test.
Optional, the nanoscale defective that produces on the said metal deposit is the whisker defective.
Optional, the metal material of said generation whisker defective comprises tungsten, aluminium, titanium, tungsten nitride or titanium nitride.
Optional, said surfaceness obtains through CD-SEM.
Optional, said surfaceness can be live width surfaceness, right line limit surfaceness, or left line limit surfaceness.
Compared with prior art, the present invention has the following advantages:
1. through the measure surface roughness whisker defective of testing and assessing, can make producers utilize existing measurement means just can accurately know the whisker defective in the semiconductor devices production run;
2. through on-line measurement, make that producers are instant on production line to understand the whisker defective that semiconductor devices produces in making, and take correction measure at once, avoided the semiconductor devices manufacturing after accomplishing the reliability measurement that will carry out;
3. detection time of manpower that can be limited and cost less; Need not detect the whisker defective like this through the pattern of test section; Only need be to its whisker defective of just can testing and assessing of its surfaceness of surface test after the plated metal sediment; Obtain the whisker defective that produces in the semiconductor fabrication process process effectively, thereby improve the product yield.
Description of drawings
Fig. 1 is the schematic flow sheet of the online test and appraisal defective of the present invention;
Fig. 2 is the surfaceness reference value schematic flow sheet that the present invention obtains the defective that is used to test and assess;
Fig. 3 is the synoptic diagram that produces the whisker defective between one embodiment of the invention test and appraisal metal gates and the connector;
Fig. 4 a and Fig. 4 b are the high-resolution SEM figure that the present invention measures the live width surfaceness, and wherein Fig. 4 a is normal no whisker defective, and Fig. 4 b is the improper whisker defective that has;
Fig. 5 a and Fig. 5 b are the high-resolution SEM figure that the present invention measures right line limit surfaceness, and wherein Fig. 5 a is normal no whisker defective, and Fig. 5 b is the improper whisker defective that has;
Fig. 6 a and Fig. 6 b are the high-resolution SEM figure of measurement of left line of the present invention limit surfaceness, and wherein Fig. 6 a is normal no whisker defective, and Fig. 6 b is the improper whisker defective that has.
Embodiment
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following disclosed practical implementation.
Surfaceness is to be used to describe the most frequently used parameter of surface microscopic topographic, and it has reflected the microcosmos geometric shape error of surface of the work, for example can be the parameter of reflection nao-and micro relief altitude response or spaced features.Said surfaceness be mainly used in to the line limit coarse (Line Edge Roughness, LER) or live width coarse (Line Width Roughness, LWR) sign of degree.If the line limit is coarse or live width is coarse bigger, may have a strong impact on the yield and the output usefulness of semiconductor devices production technology.In Precision Machining and manufacturing, along with the requirement to quality of work piece surface is more and more higher, the accurate measurement of Part Surface Roughness seems particularly important.
The detection of aforesaid coarse phenomenon be evaluated at particular importance in the production process of semiconductor.Usually; Can utilize surface roughness tester, for example be that electron beam critical dimension detection (electron-based CD metrology tool) mode is carried out, for example; CD scanning electron microscope (CD-Scanning Electron Microscope, CD-SEM) imaging technique.
To such an extent as to surfaceness generally is meant the bent out-of-flatness of line spring of the hachure pattern of the patterning that produces through photoetching process the live width uneven degree that fluctuates is arranged.Its unit is nanometer or dust.The standard of surfaceness representes with root mean square, it be certain plane to be detected measurement numerical value square the square root of mean value.
Particularly, the live width surfaceness is 3 σ values of the live width in the given surveyed area, can calculate according to following formula, but those skilled in the art should be understood that and can also adopt other account forms to obtain surfaceness:
In the formula, LWR is the live width surfaceness, CD
iBe the line width values on the i bar scan wheel profile, CD is the live width mean value on all n bar scan wheel profiles, and n is the sum of scan wheel profile.
As previously mentioned, for the defective in the testing film such as whisker, those skilled in the art expect adopting the shape of the section of aforesaid detection sample directly to observe usually, have determined whether the whisker defective with this.The creative proposition of the present inventor can utilize nanoscale defective on the method test and appraisal Semiconductor substrate that detects roughness of film, for example is the whisker defective.The present invention utilizes the method that detects surfaceness to detect the whisker defective of metal gate; For example be to cause between metal gate and the connector or the whisker defective of short circuit between metal gates and the grid, the whisker defective that possibly cause short circuit between the plain conductor that is produced at semiconductor technology back segment metal connecting line also is applicable to method of the present invention.The method of this detection surfaceness only is used to detect to the coarse phenomenon in line limit or the coarse phenomenon of live width of photoengraving pattern on the Semiconductor substrate in the past usually.That is to say that the present invention utilizes the means of existing detection surfaceness to realize online test and appraisal whisker defective, and the defect information that produces in the production process of semiconductor is fed back in real time, can effectively improve the yield of semiconductor devices.
Next, the present invention utilizes synoptic diagram to be described in detail, and when the embodiment of the invention was detailed, for ease of explanation, said synoptic diagram was an instance, and it should not limit the scope of the present invention's protection at this.
As shown in Figure 1, Fig. 1 is the schematic flow sheet of the online test and appraisal defective of the present invention, and the nanoscale defective that metal deposit produces on the Semiconductor substrate that is used to test and assess for example is the whisker defective, comprises step S1, obtains the surfaceness reference value of the defective that is used to test and assess; Step S2 measures the surfaceness of Semiconductor substrate to be measured; Step S3 compares the surfaceness and the said surfaceness reference value of Semiconductor substrate to be measured.
Through said method, if the surfaceness of said Semiconductor substrate to be measured is lower than said surfaceness reference value, there is not the nanoscale defective in Semiconductor substrate then to be measured; Otherwise if the surfaceness of said Semiconductor substrate to be measured is higher than said surfaceness reference value, there is the nanoscale defective in Semiconductor substrate then to be measured.
Wherein, obtain the surfaceness reference value of the defective that is used to test and assess among the step S1, can obtain through two kinds of diverse ways.Method 1, the surfaceness reference value of obtaining the defective that is used to test and assess among the step S1 specifically comprises: step S101 provides Semiconductor substrate; Step S102 carries out the electrical parameter test to said Semiconductor substrate; Step S103 tests the surfaceness of said Semiconductor substrate; Step S104 carries out data processing with electrical parameter test result and surface roughness value, obtains the surfaceness reference value.
Among the above-mentioned steps S104 test is obtained surface roughness value and carry out data processing; Can be; Set up the relation between electrical parameter and the surface roughness value; Can adopt short-circuit test such as said electrical parameter measurement; Such as the current value between the conductive material that passes through the test adjacent conductive layer; The surfaceness and the current corresponding value of diverse location on the wafer are marked in the same form; Use least square fitting surfaceness and electrical parameter test result, set up relation each other.Wherein, least square method is a mathematical optimization technology, and it seeks the optimal function coupling of data through the quadratic sum of minimize error.
Method 2 obtains from the known Semiconductor substrate sample that produces the whisker defective that has no guts.
Though the present invention provides above-mentioned two kinds of methods that obtain the surfaceness reference value, is not limited thereto.
Need to prove; Be formed with metal deposit on the aforesaid semiconductor substrate; And be formed with the material layer that is used to constitute semiconductor devices on the said Semiconductor substrate, such as the gate electrode layer that is used to form MOS transistor, common said metal deposit is positioned on the said gate electrode layer.
The test of aforementioned electric mathematic(al) parameter can be the on-line parameter test of in fabrication of semiconductor device, carrying out, or the selection of after the semiconductor devices manufacturing is accomplished, carrying out test.Certainly, those skilled in the art are scrutable to be, along with the raising of integrated circuit complexity, it is good more in the semiconductor device manufacture process, more early to carry out the on-line parameter test.
Wherein, The test of the electrical parameter of above-mentioned Semiconductor substrate comprises open circuit or short-circuit test, gate threshold voltage test, leakage current test etc.; Specific to the present invention; Adopt the open circuit or the short circuit of inspection signal path integrality to test; According to electrical parameter open circuit or short-circuit test result; And further obtain the surfaceness of these Semiconductor substrate, the numerical value of electrical parameter test result and surfaceness is carried out data processing, the surfaceness reference value of the defective that obtains to be used to test and assess.
Please refer to Fig. 3, Fig. 3 is the synoptic diagram that produces the whisker defective between metal gates and the connector.The defective of the MOS transistor metal gates that the present invention will form on the Semiconductor substrate with test and appraisal for example is that the whisker defective that produces between metal polycrystalline tungsten grid and the connector is that example describes.Among Fig. 3, form MOS transistor on the Semiconductor substrate 1, comprise substrate 10, grid 12, connector 14.Wherein grid is polycrystalline tungsten grid, and this Semiconductor substrate to be measured produces at polycrystalline tungsten grid place a unnecessary whisker defective 16 is arranged, and this excrescent whisker defective causes the short circuit of polycrystalline tungsten grid and connector.Certain method of the present invention whisker defective between metal gates and the grid that also can be applied to test and assess, or the whisker defective between two plain conductors occurring of semiconductor technology back segment.And the risk that whisker occurs is not limited to above-mentioned tungsten, also possibly appear on other metals such as aluminium, titanium, tungsten nitride or titanium nitride.
Further specify the method for the online test and appraisal defective of the present invention below in conjunction with Fig. 1, Fig. 2 and Fig. 3.
At first, step S1 obtains the surfaceness reference value of the defective that is used to test and assess.
In conjunction with Fig. 2,, adopt preceding method 1 to obtain the surfaceness reference value of test and appraisal defective as one embodiment of the present of invention.Particularly, the surfaceness reference value of obtaining the defective that is used to test and assess among the step S1 comprises: step S101 provides Semiconductor substrate; Step S102 carries out the electrical parameter test to said Semiconductor substrate; Step S103 tests the surfaceness of said Semiconductor substrate; Step S104 carries out data processing with electrical parameter test result and surface roughness value, obtains the surfaceness reference value.
Wherein, step S101 provides Semiconductor substrate.From a certain batch Semiconductor substrate, choosing sample tests; For example can inspect 3-6 sample by random samples; Wherein choosing of test point can be adopted the mode of choosing that has standard point in the technology now; For example be 5 points or 9 points; Certainly it should be noted that the diverse location that take into account crystal circle center and edge of choosing of said test point.Need to prove; Be formed with metal deposit on the said Semiconductor substrate; And be formed with the material layer that is used to constitute semiconductor devices on the said Semiconductor substrate, such as the gate electrode layer that is used to form MOS transistor, common said metal deposit is positioned on the said gate electrode layer.
Step S102 carries out the electrical parameter test to said Semiconductor substrate sample.Electrical parameter test comprises open circuit or short-circuit test, gate threshold voltage test, leakage current test etc., in the present embodiment, through choosing above-mentioned test point, tests adopting open circuit/short circuit of checking the signal path integrality between metal gates and the connector.
Step S103, the surfaceness of testing said Semiconductor substrate sample.
Step S104 carries out data processing with electrical parameter test result and surface roughness value, obtains the surfaceness reference value.According to aforesaid test result, set up the relation between electrical parameter and the surfaceness, through least square fitting, the two is carried out data processing, according to the scope that electrical parameter test on the technology can be tolerated, confirm the surfaceness reference value.Need to prove: the surface of above-mentioned test is consistent with the surface of carrying out electrical parameter test also here, promptly the electrical parameter result defective with surfaceness between be associated, can reflect through surfaceness.
In the present embodiment, for example be r1=11, r2=10.8, r3=10.7, wherein r1 represents the live width surfaceness, and r2 represents right line limit surfaceness, and r3 represents left line limit surfaceness.That is to say that three above-mentioned r values are exactly to be used to test and assess the surfaceness reference value of defective.Specifically, saidly set up the relation between electrical parameter and the surfaceness through least square fitting, promptly think the live width surfaceness less than 11 the normal zero defect of representative, opposite live width surfaceness is greater than the improper defectiveness of 11 representative.
As another embodiment of the present invention, adopt preceding method 2 to obtain to be used to the surfaceness reference value of defective of testing and assessing, that is, from the known Semiconductor substrate sample that does not produce the whisker defective, obtain surfaceness.Wherein, can adopt the way of any known detection whisker defective, obtain not produce the Semiconductor substrate sample of whisker defective.For example, through removing each layer on the semiconductor element in regular turn, like modes such as employing etching, corrosion, and in regular turn each layer performed an analysis, this kind detection method belongs to the technology of well known to a person skilled in the art, repeats no more at this.
Certainly; Those skilled in the art will be appreciated that; According to said method 2; Saidly from the known Semiconductor substrate sample that does not produce the whisker defective, obtaining surfaceness as the surfaceness reference value, is not that surfaceness with the sample of no whisker defective is directly as the surfaceness reference value usually.
Preset admissible error range for example can be the scope of 10%-15% on the general technology board, need be with the surfaceness come-up 10%-15% numerical value afterwards of the sample of no whisker defective as the surfaceness reference value.That is to say that in this surfaceness reference value error range, just thinking does not have the whisker defective.Yet; This error range can further combine electrical parameter test or yield result to adjust, for example, and in the scope of preset error 15%; Find that electrical parameter test failure or yield are low; Then can tighten this error range, for example be adjusted into 10%, certainly; If in the scope of error 10%; Find that the electrical parameter test is still defective or yield is low, then can further adjust, for example be adjusted into 9%.That is to say; Above-mentioned according to the test and assess surfaceness reference value of defective of method 2 being used to of obtaining; Its error range can dynamically be adjusted according to electrical parameter test result or yield, with obtain process for fabrication of semiconductor device the surfaceness that can accept.
Next, step S2 measures the surfaceness of Semiconductor substrate to be measured.Usually, after formation is easy to generate the material layer of whisker, carry out the measurement of surfaceness, and under two kinds of situation, be easy to generate whisker usually, the one, after certain heat was accumulated stress, this whisker can occur; Another kind is that very thick metal film is prone to produce (for example greater than 1.5 μ m).
At last, step S3 is according to the test and assess surfaceness reference value of defective of step S1 being used to of being obtained, and the semiconductor substrate surface roughness to be measured that obtains of step S2, and the two compares, the whisker defective of the Semiconductor substrate to be measured of testing and assessing.If the surfaceness of said Semiconductor substrate to be measured is lower than said surfaceness reference value, there is not the nanoscale defective in Semiconductor substrate then to be measured; Otherwise if the surfaceness of said Semiconductor substrate to be measured is higher than said surfaceness reference value, there is the nanoscale defective in Semiconductor substrate then to be measured.
For instance, compare with r1 respectively, y, y ' are compared with r2 respectively, z, z ' are compared with r3 respectively through x, the x ' that will measure among the step S2.According to comparative result, can recognize that satisfy above-mentioned surfaceness reference value, SEM figure shown in Fig. 4 a, Fig. 5 a and Fig. 6 a is normal no whisker defective; On the contrary, do not satisfy above-mentioned surfaceness reference value, the SEM figure shown in Fig. 4 b, Fig. 5 b and Fig. 6 b is the improper whisker defective that has, like whisker defective D1, D2, D3, D4 among the figure.
Therefore, in Fig. 4 b, Fig. 5 b and Fig. 6 b, exist to cause grid and connector short risk.That is to say; Method through the online detection defective of the present invention; Whisker defective between metal gates and the connector can be in time, be detected exactly; Make the producers can be according to this evaluating result in manufacture process; Whether decision is discarded on production line with the Semiconductor substrate of making; Thereby avoided the Semiconductor substrate manufacturing accomplish after the reliability measurement that will carry out of institute, have non-destructive and real-time, improve Semiconductor substrate production yield simultaneously.
Though present embodiment; Be to have obtained live width surface roughness value and a left side/right line limit surface roughness value simultaneously; With this whisker defective of testing and assessing; But those skilled in the art are scrutable be; According to above-mentioned three measured values; Be live width surface roughness value, right line limit surface roughness value and left line limit surface roughness value, wherein any one or a plurality of measurement results, the whisker defective of all can testing and assessing according to this.
According to one embodiment of the invention; Semiconductor substrate 1 to be measured is positioned over the detection board that is used for measure surface roughness; It for example is the CD scanning electron microscope; (CD-Scanning Electron Microscope; CD-SEM), this CD-SEM detects board and is equipped with a transmitter, a detecting device and a data processing operation unit at least.Then, produce high order focusing electron beam scanning aimed semiconductor substrate by transmitter, detecting device is through collecting secondary electron and producing the electronic image of describing the aimed semiconductor substrate.To measure the surface roughness value that Semiconductor substrate to be measured obtains at last; Compare analysis with the test and assess surfaceness reference value of defective of being used to of database storage in the data processing operation unit, wherein have the surfaceness reference value of being obtained according to preceding method 1,2 in this database.Through the surfaceness of data processing operation unit comparison object Semiconductor substrate and the result of reference value; Whether this aimed semiconductor substrate that finally is used to test and assess exists the whisker defective; Like this, producers can determine to discard whether on line this wafer according to this real-time feedback information.
In the above embodiment of the present invention; Be to be that example illustrates to detect the whisker defective that produces between metal gates and the connector; Certain method of the present invention also can be applied to detect the whisker defective between metal gates and the grid, or the whisker defective between two plain conductors.And; The whisker defective that the misgrowth of metal material causes heats in the time of for example can be through thin film deposition, heating (preventing to remove resist with oxygen plasma) during the resist ashing; Heat by laser radiation during with annealing, all can produce unnecessary whisker defective.
To sum up, the present invention provides a kind of method of online test and appraisal whisker defective, can make producers utilize existing measure surface roughness just can accurately test and assess and the whisker defective whether occur in the Semiconductor substrate production run; Like this, through on-line measurement, make that producers are instant on production line to understand the whisker defective that Semiconductor substrate is made, and take correction measure at once, avoided the Semiconductor substrate manufacturing after accomplishing the reliability measurement that will carry out; The present invention can be limited manpower and the detection time of cost less, obtain the whisker defective that produces in the semiconductor fabrication process process effectively, thereby improve the product yield.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification; Therefore; Every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection domain of technical scheme of the present invention according to technical spirit of the present invention.
Claims (10)
1. the method for an online test and appraisal defective, the nanoscale defective that metal deposit produces on the Semiconductor substrate that is used to test and assess is characterized in that, comprising:
Obtain the surfaceness reference value of the defective that is used to test and assess;
Measure the surfaceness of Semiconductor substrate to be measured;
The surfaceness and the said surfaceness reference value of Semiconductor substrate to be measured are compared.
2. assessment method as claimed in claim 1 is characterized in that, the said surfaceness reference value of obtaining the defective that is used for testing and assessing is to obtain from the known Semiconductor substrate sample that does not produce defective.
3. assessment method as claimed in claim 1 is characterized in that, the said surfaceness reference value of obtaining the defective that is used to test and assess comprises:
Semiconductor substrate is provided;
Said Semiconductor substrate is carried out the electrical parameter test;
Test the surfaceness of said Semiconductor substrate;
Electrical parameter test result and surface roughness value are carried out data processing, obtain the surfaceness reference value.
4. like each described assessment method in the claim 3, it is characterized in that said data processing comprises with least square fitting to be handled.
5. assessment method as claimed in claim 3 is characterized in that, said electrical parameter test is carried out through on-line parameter test or selection test.
6. assessment method as claimed in claim 3 is characterized in that, said electrical parameter test comprises open test or short-circuit test.
7. assessment method as claimed in claim 1 is characterized in that, said nanoscale defective is the whisker defective that produces on the metal deposit.
8. assessment method as claimed in claim 7 is characterized in that, the metal material of said generation whisker defective comprises tungsten, aluminium, titanium, tungsten nitride or titanium nitride.
9. like each described assessment method in the claim 1～8, it is characterized in that said surfaceness obtains through CD-SEM.
10. like each described assessment method in the claim 1～8, it is characterized in that said surfaceness comprises live width surfaceness, right line limit surfaceness or left line limit surfaceness.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108036736A (en) * | 2017-12-06 | 2018-05-15 | 长江存储科技有限责任公司 | Groove curvature measuring method and device, defects count Forecasting Methodology and device |
| CN109916363A (en) * | 2019-02-01 | 2019-06-21 | 天津中环领先材料技术有限公司 | A kind of IC class polished silicon wafer fault detection method |
| CN110870590A (en) * | 2018-08-14 | 2020-03-10 | 常州市派腾电子技术服务有限公司 | Smoking device, electronic cigarette and control method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1158414A (en) * | 1996-02-29 | 1997-09-03 | 中国科学院上海光学精密机械研究所 | Detecting system and method for surface microstructure |
| CN1472528A (en) * | 2002-07-29 | 2004-02-04 | 崔铉镐 | System and method for preventing mistakes in optical inspection |
| JP2004363223A (en) * | 2003-06-03 | 2004-12-24 | Seiko Epson Corp | Equipment, system, method, and program for defect inspection |
| WO2005008223A2 (en) * | 2003-07-18 | 2005-01-27 | Applied Materials Israel, Ltd. | Methods for defect detection and process monitoring based on sem images |
| US20080273193A1 (en) * | 2007-05-02 | 2008-11-06 | Hitachi High-Technologies Corporation | Pattern defect inspection apparatus and method |
| CN102053106A (en) * | 2009-11-09 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Defect detection method |
| WO2011083540A1 (en) * | 2010-01-05 | 2011-07-14 | 株式会社日立ハイテクノロジーズ | Method and device for testing defect using sem |
-
2011
- 2011-08-31 CN CN201110254271.6A patent/CN102353697B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1158414A (en) * | 1996-02-29 | 1997-09-03 | 中国科学院上海光学精密机械研究所 | Detecting system and method for surface microstructure |
| CN1472528A (en) * | 2002-07-29 | 2004-02-04 | 崔铉镐 | System and method for preventing mistakes in optical inspection |
| JP2004363223A (en) * | 2003-06-03 | 2004-12-24 | Seiko Epson Corp | Equipment, system, method, and program for defect inspection |
| WO2005008223A2 (en) * | 2003-07-18 | 2005-01-27 | Applied Materials Israel, Ltd. | Methods for defect detection and process monitoring based on sem images |
| US20080273193A1 (en) * | 2007-05-02 | 2008-11-06 | Hitachi High-Technologies Corporation | Pattern defect inspection apparatus and method |
| CN102053106A (en) * | 2009-11-09 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Defect detection method |
| WO2011083540A1 (en) * | 2010-01-05 | 2011-07-14 | 株式会社日立ハイテクノロジーズ | Method and device for testing defect using sem |
Non-Patent Citations (1)
| Title |
|---|
| 张泰昌: ""表面缺陷与表面粗糙度的区分及其评定"", 《工业计量》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108036736A (en) * | 2017-12-06 | 2018-05-15 | 长江存储科技有限责任公司 | Groove curvature measuring method and device, defects count Forecasting Methodology and device |
| CN108036736B (en) * | 2017-12-06 | 2020-03-13 | 长江存储科技有限责任公司 | Groove curvature measuring method and device and defect number predicting method and device |
| CN110870590A (en) * | 2018-08-14 | 2020-03-10 | 常州市派腾电子技术服务有限公司 | Smoking device, electronic cigarette and control method |
| CN110870590B (en) * | 2018-08-14 | 2022-04-29 | 常州市派腾电子技术服务有限公司 | Smoking device, electronic cigarette and control method |
| CN109916363A (en) * | 2019-02-01 | 2019-06-21 | 天津中环领先材料技术有限公司 | A kind of IC class polished silicon wafer fault detection method |
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