TW437070B - Capacitor with a high-ε-dielectric or a ferro-electricum according to fin-stack-principle and production method - Google Patents

Capacitor with a high-ε-dielectric or a ferro-electricum according to fin-stack-principle and production method Download PDF

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Publication number
TW437070B
TW437070B TW088114492A TW88114492A TW437070B TW 437070 B TW437070 B TW 437070B TW 088114492 A TW088114492 A TW 088114492A TW 88114492 A TW88114492 A TW 88114492A TW 437070 B TW437070 B TW 437070B
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Taiwan
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layer
capacitor
scope
patent application
dielectric
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TW088114492A
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Chinese (zh)
Inventor
Gerrit Lange
Till Schlosser
Martin Franosch
Hermann Wendt
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Siemens Ag
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/033Making the capacitor or connections thereto the capacitor extending over the transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Capacitor with a high-ε-dielectric or a ferro-electric capacitor-dielectric (9), one electrode of the capacitor contains nuble metal and several lamellae (61), which are inter-connected through a support-structure (7) and also connected with a supporter if necessary. The support-structure can be arranged on one or several outer-edges of said lamellae, or it can extends in the inner through the lamellae. The production process can be carried out through the deposition of a layer-sequence with alternative lower and higher etching-rate (if necessary with an etching-stop-layer in the lower region), etching to the layer-structure, construction of the support-structure, and selective removeal of the layers with higher etching-rate.

Description

43 J〇7〇 A7 B7 · 經濟部智恶財產局員工消費合作社印製 五、發明説明( f ) 1 1 本 發 明 傜 關 於 一 種 積 m 電 路 中 之 電 容 器 t 其 第 一 電極 1 ! 含 有 貴 金 屬 電 容 器 介 電 質 是 一 種 高 e 介 電 質 或 __- 種鐵 I 1 電 皙 諳 1 先 1 在 許 多 積 £曲 m 半 m 體 電 路 (例如, D R A Μ電路或A / D轉換 閱 讀 1 背 1 器 )中需要電容器。 提高積體密度是- -種首要之目標, ώ 之 1 m 盡 可 能 髙 之 電 容 或 足 以 符 合 需 求 之 電 容 須 以 取 小 之空 注 意 事 1 1 間 m 求 來 達 成 Ο 此 種 問 題 特 別 曰 疋 發 生 在 DRAM -電路中, 項 1 填 1 其 中 每 記 憶 胞 都 具 有 —' 値 12 m 電 容 器 和 —1 © & 擇 電晶 寫 本 U 體 可 供 每 一 記 億 m 使 用 之 面 積 持 續 地 降 低 〇 同 時 為了 頁 r '^· 1 1 可 靠 地 儲 存 電 荷 且 可 區 別 此 種 m 持 Μ 讀 出 之 資 訊 則記 1 I 億 電 容 器 須 保 持 某 種 程 度 之 最 小 電 容 量 Ο 此 種 最 小 電容 1 1 量 百 前 大 約 是 2 5 f F 〇 i 訂 為 了 減 小 電 容 器 之 空 間 需 求 » 則 可 使 用 較 高 介 電 率 1 I (P e r mi 11 i V it y )之 順 電 質 (高e介電質) 〇 在 記 億 體 配置 1 1 中 最 好 曰 疋 使 用 所 謂 "堆鏟” 電 容 器 (記億胞之電容器配置 1 I 在 所 屬 之 選 擇 電 晶 體 πμ. 之 上 方 )〇 記憶胞(其 使 用 順 電 性材 [ •今 料 作 為 電 容 器 介 電 質)在選取電源電壓時會損失其上所 ] 1 儲 存 之 電 荷 » 因 此 亦 損 失 其 所 儲 存 之 資 訊 〇 此 外 'JS ^ 1 記 億 胞 由 於 殘 餘 之 漏 電 流 而 必 須 持 續 地 重 新 寫 入 (更新 1 1 (Γ e f re s h ) 時間) 反 之 使 用 m 電 性 材 料 作 為 電 容 器介 1 電 質 可 由 於 Aff- 鐵 電 質 之 不 同 之 極 化 方 向 而 形 成 一 種 永 久性 1 記 億 體 (FRAM) 9 其 在 選 取 電 源 電 壓 時 不 會 遣 失 其 資 訊且 1 亦 不 須 持 鐘 地 重 新 寫 人 〇 記 億 胞 之 殘 餘 之 漏 電 流 不 會影 1 -1 m 所 儲 存 之 信 號 〇 1 I 3 1 1 1 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 經濟部智慧財產局員工消費合作社印製 43 7〇7〇 u A7 ___B7 五、發明説明(> ) 各種不同之高ε介電質和鐵電質在文獻中已為人所知 ,這些材料例如鈦酸緦鋇(B S Τ ),鈦酸缌(S Τ )或鈦酸錯 鉛(ΡΖΤ)ι .其它之鐵電性聚合物和順電性聚合物及其它 類似物質。 雖然上述笸些材料具有所期望之電性,但其重要性實 際上仍然是有限的。一種重要之原因是:上述這些材料 不可輕易地用在半導體配置中。這些材料之製造是由濺 镀或沈積程序來達成,其在含氣之大氣中需要較高之溫 度。這樣所造成之結果是:一些在半導體技術中作為電 極材料用之導電性材料(例如,多晶矽,鋁或_)是不適 當的,因為它們在此種條件不會被氣化。因此至少第一 電極通常是由一種含有貴金屬(例如,鉑,釕)之材料所 製成,,但這些新的電極材料就半導體技術而言是較不為 人所知之物質。它們較不易沈積且只有在較小之層厚度 時才可令人滿意地被結構化。此外,它們是可被氧透過 的,這樣所造成之結果是:在電容器介電質製造期間位 於深處之結構會被氣化且在第一電極和選擇電晶體之間 不能確保有足夠之接觸區。因此一種位於電容器介電質 下方之位障是需要的,此種位障可抑制氣之擴散。 在DE19640448中描述一種記億胞,其中第一電極和此 種至選擇電晶體所用之連接結構之間的位障接面是由氮 化作用所産生。在DE-OS 196 40244中描述一種電容器, 其具有高e介電質或鐵電性介電質,其中第一電極是由 電極核心和較薄之含有貴金屬之層所構'成,電極核心是 -4 - 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) ----j----.1一 裝------„訂------ (請先閲讀背面之注意事項再填寫本頁) Q A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明( ) 1 1 由 連 接 結 構 或 氧 化 位 障 之 材 料 所 構 成 〇 這 樣 所 具 有 之 m 1 ί 點 疋 α 有 一 種 較 搏 之 含 有 貴 金 屬 之 層 必 須 被 結 構 化 〇 1 所 有 具 有 高 ε 介 質 或 鐵 電 性 介 電 質 之 電 容 器 是 共 产—、 請 1 先 1 用 的 > 其 設 有 一 種 在 原 理 上 疋 平 面 之 第 — 電 極 配 置 0 間 讀 1 1 在 IJ S 558 1 4 3 β中在電極核心之表面上施加- -種薄的 背 面 1 I 之 1 铂 層 以 作 為 上 述 技 術 之 電 容 器 之 第 一 電 極 ΰ 可 能 時 亦 可 注 意 1 事 1 在 形 成 第 — 和 第 二 電 極 之 前 製 成 此 種 高 e 介 電 質 以 作 為 項 再 1 — 種 裸 露 之 結 構 * 即 1 電 極 形 成 在 介 電 質 之 側 壁 〇 填 寫 本 J 裝 本 發 明 之 巨 的 疋 在 一 種 具 有 高 ε 介 電 質 或 鐵 電 性 或 介 *頁 1 1 電 質 之 電 容 器 中 進 步 降 低 空 間 需 求 本 發 明 亦 提 供 —' J 1 I 種 簡 易 之 能 以 —^* 般 製 程 來 進 行 之 此 種 電 容 器 之 製 法 〇 1 i 此 種 的 疋 以 _ 專 利 範 圍 第 1 項 之 特 散 中 所 述 之 電 1 訂 1 容 器 或 第 7 項 i 第 13 項 之 特 徽 中 所 述 之 製 造 方 法 來 達 成。 在 本 發 明 中 * 第 一 電 極 含 有 至 少 二 個 互 相 隔 開 之 薄 Η 1 1 t 此 二 値 薄 Η 基 本 上 平 行 於 承 載 體 表 面 且 經 由 —. 種 支 撑 1 I 結 構 而 互 相 連 接 〇 電 容 器 之 有 效 表 面 較 此 種 承 載 體 表 面 1 1 大 很 多 〇 j 第 一 電 極 之 幾 何 結 構 m 為 一 種 所 謂 鰭 狀 堆 疊 式 電 容 器 1 之 形 式 * 其 由 m 雜 之 多 晶 矽 所 構 成 〇 此 種 鳍 狀 堆 S 式 電 i 容 器 例 如 在 ΕΡ 4 15 5 3 0 Β 1 , E P 7 7 96 56 Α2 ΕΡ 756 3 26 A 1 Ί 及 在 仍 未 掲 示 之 DE 專 利 案 號 198 2 1 S 1 0 .5 1 1982 1776 .5 和 I i 19 82 17 77 ,3 中 已 有 描 述 〇 例 如 有 下 述 之 基 本 形 式 : 1 1 A ) 在 薄 Η 之 一 個 或 二 個 相 鄰 側 面 上 之 位 於 外 部 之 支 撑 1 I 結 構 〇 - 5 - 1 1 I ! 本紙張尺度適用中國國家標準(CNS ) A4規格(2丨Ο X 297公釐) 切 07σ Α7 ___Β7 五、發明説明(4 )43 J〇7〇A7 B7 · Printed by the Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs. 5. Description of the Invention (f) 1 1 The present invention relates to a capacitor t in a product circuit. Its first electrode 1! The electric substance is a high-e dielectric or __- iron I 1 electric 谙 1 first 1 in many products 曲 m m half m body circuit (for example, DRA Μ circuit or A / D conversion read 1 back 1 device) Capacitors are required. Increasing the density of the product is a primary goal. The 1m capacitor as much as possible or a capacitor that is sufficient to meet the demand must be achieved by taking a small amount of attention. 1 1m is required to achieve 0. This kind of problem occurs especially In the DRAM-circuit, item 1 is filled with 1 where each memory cell has — '値 12 m capacitor and —1 © & electrified crystal writing U-body area that can be used for each 100 million m is continuously reduced. Page r '^ · 1 1 Reliable storage of charge and can distinguish this type of information. M Read the information read 1 billion capacitors must maintain a certain level of minimum capacitance 〇 Such a minimum capacitance 1 1 about a hundred years ago is 2 5 f F 〇i order to reduce the space requirement of the capacitor »you can use a higher dielectric constant 1 I (Per mi 11 i V it y) paraelectric (high e dielectric) 〇 in the record billion It is best to use so-called " stack shovel 'capacitors in the body configuration 1 1 (Capacitor configuration of 1 billion cells is 1 I above the selected transistor πμ.) 0 Memory cells (which use paraelectric materials [• This material is used as the capacitor dielectric) will lose its power when selecting the power supply voltage ] 1 Stored charge »Therefore, it also loses its stored information. In addition, 'JS ^ 1 The billion cells must be continuously rewritten due to the residual leakage current (update 1 1 (Γ ef re sh) time) Instead use m Electrical materials are used as capacitor dielectrics. 1 Electrical materials can form a permanent 1 due to the different polarization directions of Aff-ferroelectrics. 1 FRAM 9 It does not lose its information when selecting the power supply voltage and 1 also It is not necessary to rewrite the time. The residual leakage current of 0 billion cells will not affect the stored signal of 1 -1 m. 0 1 I 3 1 1 1 This paper size applies to China National Standard (CNS) A4 specification (210X297) %) Staff of Intellectual Property Bureau, Ministry of Economic Affairs Printed by Fei Cooperative 43 7〇〇〇u A7 ___B7 V. Description of the invention (>) Various high ε dielectric and ferroelectric materials are known in the literature. These materials such as barium hafnium titanate (BS T), thorium titanate (ST) or lead titanate (PZT). Other ferroelectric polymers and paraelectric polymers and other similar substances. Although some of these materials have the desired electrical properties, their importance is actually limited. One important reason is that these materials cannot be easily used in semiconductor configurations. The manufacture of these materials is achieved by sputtering or deposition procedures, which require higher temperatures in a gaseous atmosphere. As a result, some conductive materials (e.g., polycrystalline silicon, aluminum, or silicon) used as electrode materials in semiconductor technology are inappropriate because they are not gasified under such conditions. Therefore, at least the first electrode is usually made of a material containing a precious metal (for example, platinum, ruthenium), but these new electrode materials are a lesser known substance in terms of semiconductor technology. They are less difficult to deposit and can be satisfactorily structured only at small layer thicknesses. In addition, they are permeable to oxygen, which has the consequence that structures that are located deep during the manufacture of the capacitor dielectric are vaporized and that sufficient contact cannot be ensured between the first electrode and the selected transistor Area. Therefore, a barrier below the dielectric of the capacitor is needed. This barrier can suppress the diffusion of gas. In DE19640448, a billion cell is described in which the barrier interface between the first electrode and the connection structure used to select the transistor is generated by nitrogenation. A capacitor is described in DE-OS 196 40244, which has a high-e dielectric or a ferroelectric dielectric. The first electrode is composed of an electrode core and a thin layer containing a precious metal. The electrode core is -4-This paper size is applicable to China National Standard (CNS) A4 specification (210X 297mm) ---- j ----. 1 one pack -------- „Order ------ (Please (Please read the notes on the back before filling in this page) Q A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () 1 1 It is composed of the material of the connection structure or oxidation barrier 〇 This has m 1 ί Point 疋 α There is a kind of layer containing precious metals that must be structured. All capacitors with high ε dielectric or ferroelectric dielectric are communist—, please use first and first; it is provided with a In principle, the first plane of the plane-electrode configuration 0 read 1 1 in IJ S 558 1 4 3 β on the surface of the electrode core--a kind of thin back 1 I The first layer of platinum is used as the first electrode of the capacitor of the above technology. 注意 It is also possible to pay attention to one thing. Before the formation of the first and second electrodes, such a high-e dielectric is used as a term. Structure * That is, 1 electrode is formed on the side wall of the dielectric. Fill out this article. The giant of the present invention is in a capacitor with high ε dielectric or ferroelectricity or dielectric. * Page 1 The invention also provides — 'J 1 I a simple method for making such capacitors that can be performed in a ^ * general process. 0 1 i This type of electricity is described in the special issue of item 1 of the patent scope. Order 1 container or the manufacturing method described in item 7 i item 13 special emblem. In the present invention * the first electrode contains at least two thin films 隔开 1 1 t, which are substantially parallel to the surface of the carrier and are connected to each other via-. 1 supporting structure 〇 effective surface of the capacitor It is much larger than the surface 1 1 of this carrier. 0 The geometry of the first electrode m is a form of a so-called fin-shaped stacked capacitor 1. It is composed of m polycrystalline silicon. This fin-shaped S-type electric container For example, in EP 4 15 5 3 0 Β1, EP 7 7 96 56 Α2 EP 756 3 26 A 1 Ί and DE patent case number 198 2 1 S 1 0 .5 1 1982 1776 .5 and I i It has been described in 19 82 17 77,3. For example, it has the following basic form: 1 1 A) The external support 1 I structure on one or two adjacent sides of the sheet. 0-5-1 1 I ! This paper size applies to China National Standard (CNS) A4 specification (2 丨 〇 X 297 mm) cut 07σ Α7 ___ Β7 V. Description of the invention (4)

而 個有 三所 在在 1) \J B C 於 位 之 上 是 常 通 構 結 撑 支 之 β ώ 口 〇 外 構於 結位 撑之 支上 之面 7J外iAnd there are three places in the 1) \ J B C position is the β-port of the regular support structure 〇 Outer structure on the support structure 7J 外 i

訂 化 氣 用 使 可 亦 a 但 構 . 結料 撑材 支之 之極 部電 内一 於第 位作 之用 片合 薄適 由 S& 經恃 DIA 器種 容此 電由 ε 是 高佳 在較 用極 使電 料二 材第 些 , 這知 -所 料人 材為 之已 屬中 金器 貴容 有雷 含 質 它霄 其锶 及或 之 當 #成一 構第 Μ 適!;而 {匕J質 晶 其,電 m夕夕 S 由 鐵 PTL 或 亦 質 ,屬八" 成金e * ^高 它 所Lr由 料 藉 材),是 之IN極 Θ1ΤΙ电 相 二 極y第 電I,之 器 第Η容 0料電 如 例 之 餘 其 體 戟 ΊΙΕ- 承 點 接 之 用 極 電 1 第 -131- 種 i 有 。含 離可 1cm 相 載 極承 I φϋΠΓ 蓋構 覆結 層ί# 離支 隔或 種 Η 一 薄 以之 是方 面下 表最 含 第 之 屬 金 之 面 表 體 JE- 承A ^ 有ί 蓋 覆 卽份 /1- TSP, 二 含 。包 區體 觸載 接承 性 C 電中 種胞 一 億 成記 形AM I R 可 D 保在 確用 以使 ’是 rfi .二二 接較 之器 述容 上電 蓋種 覆此 H. ί 上其h 由 £ 其且 ΕίΛί化 „ 佳一X D較® S 點 Π 之接Jif 例 體此 f 晶 。障 電接位 。連氣 體相之 晶極性 霞 -ί Β 可玲 ΙξΐΓ 擇一導 選第種 S 與 一 M0而有 之點具 靨接中 所之域 其述區 (請先閲讀背面之注意事項再填寫本頁) y装. -3 經濟部智慧財產局員工消費合作杜印製 成 構 所 物 似 類體 或載 鎮承 -在 矽須 晶 , 多極 ,電 鈦一 由第 是成 如數 例了 份為 部 含 包 可 其 era 隔 umu 種 列 序 層 1I3U 種 一 生 産 上 及 層 之 成 構 所 料 材 之 點屬 接金 式貴 入有 埋含 種由 1 I 一 種 有一 含有 中含 層地 離替 隔交 , 其 層 , 擇 選 可腸 料金 材種 CJWU- 種 一 二用 第使 中是 LN ΙΙϋ 其佳 ,較 層 0 之刻 成蝕 構被 所而 料料 材材 t— tUnU 8 β二一 第第 由對 種地 一 性 例 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 經濟部智慈財產局員工消費合作社印製The use of customized gas can also be a structure. The pole of the supporting material support is a thin film suitable for use by S & Warp DIA devices. Compared with the second material of the electric material, this knows that the expected human resource is already in the goldsmith's equipment. It has a thunderous quality, its strontium, and or when it is # 成 一 构 第 M! ; {{JJ quality crystal, electric m Xixi S by iron PTL or equivalent, belongs to eight " into gold e * ^ Gao it Lr borrowed from the material), is the IN pole Θ1Τ1 electric phase second pole y Electricity I, the electric capacity of the device is 0. In addition to the electric power, its body is Ί イ Ε- the pole is connected to the pole electricity 1 -131- species i have. Containing 1cm phase-bearing pole bearing I φϋΠΓ Cover structure covering layer ί # Libraries or seeds 薄 One thin is the aspect The following table contains the most gold surface body JE- Cheng A ^ Yes Servings / 1- TSP, two containing. Enveloping body contacting and receiving C. The seed cell is 100 million in the form of AM IR, which can be used to ensure that it is 'rfi.' Its h is from £ and its ΕίΛί 化 „Jiayi XD is connected to the Jif instance of this S f crystal. The barrier is connected. The polarity of the crystal connected to the gas phase Xia-ί Β 可 玲 ΙξΐΓ Choose the first one S and an M0 have a connection point between the field and the description area (please read the precautions on the back before filling out this page). Y. Resembles like a body or a load bearing-in silicon whisker, multi-pole, electro-titanium, made by the first example such as several parts, including the can be separated by its umu species sequence layer 1I3U species, the production of upper and lower layers The structure of the material is gold-plated, expensive, embedded, and seeded. It consists of 1 I, one with a middle layer, and is separated from the other. The layer, choose the intestable gold material type CJWU- one, two, and the second is LN. ΙΙϋ It's better, compared with layer 0, the material is t-tUnU 8 β21 First by the farming type Example This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

五、發明説明( Γ ) 1 1 如 1 A ] 或 T i )作為第二種材料。 1 I 在 支 撑 結 構 位 於 外 部 之 此 種 實 施 形 式 中 » 須 對 上 述 之 1 1 廢 序 列 進 行 結 構 化 直 至 承 載 體 為 止 > 以 便 形 成 —* 種 具 有 ,-請 I 1 邊 線 之 層 結 構 〇 須 在 至 少 _. 痼 邊 線 上 産 生 此 種 支 撑 閲 讀 1 ί 结 構 1 此 時 可 待 別 使 用 種 非 等 向 性 傾 斜 式 之 蒸 發 過 程 背 ώ 之 1 或 共 形 (C on f 0 r m )之沈積過程及隨後之非等向性蝕刻以形 ί [ 1 成 種 間 隔 層 (S pa c e Γ ) 〇 在 第 二 種 方 式 中 然 後 須 對 此 層 爭 項 再 1 結 構 中 之 開 Π 進 行 刻 9 以 便 使 這 層 之 表 面 露 出 且 利 填 寫 本 ) 苯 I 闬 種 選 擇 性 蝕 刻 可 使 這 層 由 第 二 材 料 中 去 除 〇 _頁 1 I 上 述 之 開 □ 可 位 於 層 結 構 之 邊 緣 使 此 處 形 成 此 種 支 1 1 m 結 構 所 用 之 層 (或間隔層(S P a c e r )) 以 及 情 況 需 要 時 此 1 1 種 層 結 構 之 邊 緣 區 域 都 可 被 去 除 0 1 訂 1 I 此 種 開 口 另 - 方 面 可 兀 金 産 生 於 此 種 層 結 構 之 内 部 ( 特 別 是 中 央 )中。 這樣可在第二種材料被蝕刻去除時確 1 1 保 有 一 種 特 別 高 之 穩 定 性 這 是 因 為 此 種 支 撑 結 構 是 存 1 I 在 於 支 撑 架 之 所 有 位 於 外 部 之 邊 緣 上 〇 由 第 二 種 材 料 所 1 ί 構 成 之 m. 層 因 此 可 非 常 薄 * 例 如 20 30 n m 〇 ) y 1 上 述 之 開 口 亦 可 設 置 在 層 結 構 之 内 部 中 或 穿 過 内 部 t 1 ΐ 使 丨比 開 α 將 此 種 層 結 構 切 割 成 二 部 份 » 每 —► 部 份 都 用 作 ϊ 1 電 容 器 之 第 電 極 〇 換 言 之 ♦ 一 開 始 卽 須 産 生 此 種 層 結 .1 構 t 使 其 具 有 由 二 痼 相 龃 之 電 容 器 所 形 成 之 橫 向 尺 寸 S 1 • 1 妖 /、、、 後 在 形 成 上 述 開 P 時 此 種 層 結 構 被 分 為 - 値 電 極 0 每 1 i · 電 極 在 三 個 逄 緣 (外部側面) 上 設 置 — 種 支 撑 結 構 這 1 樣 同 樣 可 確 保 種 良 好 之 7 機 械 穩 定 性 〇 1 1 [ i I 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) A7 B7 經濟部智祛財產局員工消費合作杜印製 五、發明説明( y ) 1 1 在 本 發 明 之 另 一 實 施 形 式 中 > 此 支 結 構 形 成 在 電 極 1 • J | 之 内 部 〇 因 此 就 像 第 — 實 施 形 式 —- 樣 此 種 層 序 列 曰 7E 形 成 1 在 承 載 體 上 在 層 序 列 中 形 成 開 η 且 較 佳 曰 疋 m 第 —- 種 材 請 1 先 1 料 填 入 > 以 便 茌 開 □ 中 産 生 一 種 支 撑 結 構 〇 然 後 非 等 向 閱 讀 1 I 性 地 依 據 FJ1 將 産 生 之 電 極 之 大 小 而 對 一 種 層 結 構 來 對 此 背 dj 之 1 種 層 序 列 進 行 蝕 刻 由 第 —- 和 第 二 材 料 所 構 成 之 層 裸 露 注 意 1 I 事 1 在 外 部 邊 緣 0 藉 助 於 一 種 可 選 擇 性 地 對 第 --- 材 料 和 支 撑 項 再 1 結 構 而 進 行 之 蝕 刻 來 去 除 這 些 由 第 二 材 料 所 構 成 之 層 〇 填 寫 本 \ ) 装 於 曰 疋 使 用 種 具 有 等 向 性 成 份 之 蝕 刻 m 程 〇 這 些 殘 留 之 頁 1 ί 由 第 一 材 料 所 構 成 之 層 以 及 此 種 使 IS 層 電 性 相 連 接 所 1 [ ί 用 之 支 撑 結 構 共 同 形 成 第 一 電 極 〇 1 1 在 産 生 第 電 極 之 後 在 所 有 之 實 施 形 式 中 在 第 電 極 I 1 丁 上 施 加 —* 種 Ία 问 e 介 電 質 或 鐵 電 質 1 其 上 産 生 ___- 種 反 電 極 1 I 1 於 是 可 镇 満 此 種 介 於 薄 Η 之 間 的 中 空 空 間 〇 1 1 可 施 加 一 種 蝕 刻 停 止 層 以 作 為 此 種 層 序 列 之 最 下 層 或 [ I 最 下 之 第 二 層 〇 此 種 蝕 刻 停 止 層 可 在 此 種 由 第 二 種 材 料 l I 所 構 成 之 層 之 選 擇 性 等 向 或 蝕 刻 之 前 1 之 後 或 同 時 而 被 i 1 去 除 0 層 序 列 之 此 種 鄰 接 於 蝕 刻 停 止 層 之 層 較 佳 是 一 種 1 由 第 -- 種 材 料 所 構 成 之 層 〇 形 成 此 種 層 結 構 所 用 之 蝕 刻 \ 1 程 序 同 樣 可 像 産 生 上 述 開 Π 時 一 樣 在 二 個 或 値 牲 刻 步 "I 驟 中 完 成 * 其 中 第 — 独 刻 步 驟 是 選 擇 性 地 對 刻 停 止 層 I 來 進 行 種 可 能 存 在 於 承 載 體 中 之 接 frtDf 觸 孔 或 位 障 或 承 1 載 體 表 面 本 身 曰 7H 藉 由 本 方 法 而 特 別 良 好 地 受 到 保 護 〇 因 ] 此 1 ”使用- -種蝕刻停止層是否有月 是 和 第 一 及 第 二 種 1 8 I 1 1 1 本紙張尺度適用中國國家標準(CNS ) A4規格(21 OX 297公釐} 切 〇7〇 λ7 __Β7_ 五、發明説明(7 ) 材料,位障以及承載體表面等之選擇有關 層序列(P t,A 1 _)之形成例如可藉由濺鍍或Μ由C V D方法 來逹成可使用一種以C 1 2 , A r , S i C 1 4或P C 13 來進 行之R I E方法來對此種由P t和A 1所構成之層序列進行非 等向性之蝕刻。對A 1所進行之選擇性等向式蝕刻是以 H a P 0 4 / Η Ν Ο 3 / Η 2 0或H C 1來進行,於是在蝕刻速率比 牵少是1: 100。鈦能以NH4〇H/H2〇2等向性地且選擇 件地對一種含有貴金屬之層而被蝕刻。此種對由氧化砂 所構成之承載體表面所具有之選擇性是S1: 100。 本發明以下將依據圖式和實施例來詳述。 圖式簡單説明如下: 第1-4圖 基板之横切面,本方法之第一實施例依據 一種D R A Μ記憶胞而在此橫切面上作説明。 第5 - 6圖 第二實施例。 第7-12圖 第三實施例 第1 3 - 1 4圖 第四實施例。 第1 5 - 1 9圖 第五實施例。 第20-24圖 第六實施例。 —ilf m 1^1^1 1^.HL ^11 fl^ll (請先閲讀背面之注意事項再填寫本頁) 經濟部智葸財產局員工消費合作杜印製 如線 例元 1字 板有 基具 。其 2 ( 靥體 離晶 隔電 種擇 一 選 加些 施一 上有 1 含 板其 基 , 在板 : 基 圖矽 1 種 第一 是 第在料鎬 )(材化 線平性矽 元整雷或 位被導鈦 和須以化 )0 圖離 4 隔 如入 例填 ” 之置 淮開谁己9 隔 摻須_ 化 氧 由 是 如 例 層 孔 觸 接 些 鎮孔 蜀 , 矽接 晶些 多 一5. Description of the invention (Γ) 1 1 such as 1 A] or T i) as the second material. 1 I in such an implementation form where the supporting structure is located externally »The above 1 1 waste sequence must be structured until the carrier > so as to form-* species with,-please the layer structure of the edge of I 1 at least _. This kind of support is produced on the edge of the reading 1 ί Structure 1 At this time, it is possible to use a non-isotropic tilting evaporation process or the conformal (C on f 0 rm) deposition process and subsequent Anisotropic etching takes the form of [1 species of spacer layer (Space Γ) 〇 In the second method, the contention of this layer must then be engraved in the structure 9 to make the surface of this layer (Exposed and easy to fill in this) Benzene I A type of selective etching can remove this layer from the second material. ○ Page 1 I The above opening can be located on the edge of the layer structure to form this branch 1 1 m structure. Layer (or spacer layer (SP acer)) When circumstances require this 11 seed layer structure of the edge area are may be removed 01 Order 1 I This kind of opening another - aspects may Wu gold produced in this seed layer structure of the inner part (especially the center) in the. In this way, when the second material is etched and removed, 1 1 maintains a particularly high stability. This is because this support structure is stored 1 I lies on all the outer edges of the support frame. 0 is made of the second material. ί The m. layer of the structure can therefore be very thin * For example 20 30 nm 〇) y 1 The above openings can also be provided in the interior of the layer structure or pass through the interior t 1 ΐ so that the layer structure is cut into α than α Two parts »Each—► part is used as the first electrode of a capacitor. In other words, ♦ Such a layering must be produced at the beginning. 1 Structure t such that it has a lateral dimension S formed by a two-phase capacitor. 1 • 1 demon / ,,, and this layer structure is divided into the following when the above-mentioned opening P is formed-値 electrode 0 every 1 i · The electrode is arranged on three ridge edges (outer side)-the same kind of supporting structure Can ensure good 7 mechanical stability 〇1 1 [i I This paper size applies to Chinese National Standards (CNS) A4 specifications (210X 297 mm) A7 B7 Printed by the Intellectual Property Office of the Ministry of Economic Affairs on employee consumption cooperation 5. Production Description (y) 1 1 In another embodiment of the invention > This branch structure is formed inside the electrode 1 • J | so it is like the first embodiment-like this layer sequence 7E formation 1 is formed on the carrier in the layer sequence η and preferably 疋 m. The first seed material, please fill in the material first> in order to create a support structure in the opening □ and then read non-isotropically 1 according to the size of the electrode that FJ1 will produce. A layer structure is used to etch a layer sequence of this back dj. The layer composed of the first and second materials is exposed. Note 1 I matter 1 is on the outer edge 0 with the aid of an optional Hezhi The support is further etched by the structure to remove these layers made of the second material. Fill in this \) Installed in an etching process with an isotropic composition. These residual pages 1 ί by the first The layer made of materials and this electrically connected IS layer 1 [ί The supporting structure used together forms the first electrode 0 1 1 After the second electrode is generated, it is applied to the first electrode I 1 in all embodiments. — * Ία ask e Dielectric or ferroelectric 1 ___- kind of counter electrode 1 I 1 can be used to suppress this hollow space between thin 〇 0 1 1 An etch stop layer can be applied Take this as the lowest layer of this layer sequence or [I the second lowest layer. This etch stop layer may be before or after selective selective isotropic or etching of such a layer composed of the second material l I or While being i 1 The layer adjacent to the etch stop layer in the 0-layer sequence is preferably a 1-layer made of the first material. 0 The etching used to form this layer structure is also similar to the above-mentioned opening process. The same step is completed in two or two steps " I * * Among them, the first step is to selectively stop the engraving stop layer I to perform a contact frtDf contact hole or barrier or bearing that may exist in the carrier. 1 The surface of the carrier itself is 7H. This method is particularly well protected by this method. 0]] 1 "Use-whether there is a type of etching stop layer and the first and second types. 1 8 I 1 1 1 This paper size applies to China National Standard (CNS) A4 specification (21 OX 297 mm) cut 〇07〇λ7 __Β7_ V. Description of the invention (7) Selection of materials, barriers and surface of the carrier, etc. related to the layer sequence (P t, A 1 _) Formation can be performed, for example, by sputtering or M by a CVD method. The R I E method using C 1 2, Ar, Si C 1 4 or P C 13 performs anisotropic etching of this layer sequence consisting of P t and A 1. The selective isotropic etching of A 1 is performed with H a P 0 4 / Η Ν Ο 3 / Η 2 0 or H C 1, so the etch rate is 1: 100 less than the draw rate. Titanium can be etched isotropically and selectively with a layer containing a noble metal at NH4OH / H2O2. This selectivity to the surface of the carrier made of oxidized sand is S1: 100. The present invention will be described in detail below with reference to the drawings and embodiments. The diagram is briefly explained as follows: Figs. 1-4 A cross-section of a substrate. The first embodiment of the method is described on this cross-section based on a DRAM memory cell. Figures 5-6 Second embodiment. Figs. 7-12 Third Embodiment Figs. 1 3-14 Fig. 4 A fourth embodiment. Figures 1 5-1 9 The fifth embodiment. 20-24 Figure Sixth embodiment. —Ilf m 1 ^ 1 ^ 1 1 ^ .HL ^ 11 fl ^ ll (Please read the notes on the back before filling out this page) Employees' cooperation in the Intellectual Property Bureau of the Ministry of Economic Affairs, printed as a line example 1 word board Base. The 2 (carcass ion crystal isolation type selection, plus some applications, there are 1 on the plate and its base, on the plate: the base silicon 1 is the first material pick) (materialization line flat silicon element integration) The thunder or bit is guided by titanium and must be chemically treated.) 0 Figures and 4 separated as shown in the example. "Huaikai who has 9 separated dosing. _ Oxygen is contacted by some holes, such as a few holes, silicon bonding. Some more one

濁 氐 構®鈦丨 Η接 其 0且§使0L 且 成 中 孔 氮 基 逹 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 4S ?〇 A7 B7 經濟部智惡財產局員工消費合作社印製 五、發明説明(ί ) ί 1 板 中 m 擇 雷 晶 ϋ 之 源 極 / 汲 極 區 〇 較 佳 曰 疋 在 接 觸 孔 3 之 1 „[ 上 部 中 配 置 一 種 位 障 4, 其可仰制氣之擴散。 此種位障 1 [ 之 製 造 方 法 例 如 茌 D E -1.94 4 0 2 46 > D E -1 96 40 44 8中己 請 先 1 1 為 人 所 知 在 此 種 承 載 體 之 表 面 上 現 在 施 加 —*- 種 層 序 列 m 讀 1 背 1 其 含 有 交 替 地 配 置 之 層 6 1 (由 含 有 貴 金 屬 之 第 __. 種 材 ιέ 之 料 所 構 成 )及層6 2 (由第二種材料所構成) 〇 第 一 種 材 料 注 意 事 1 1 例 如 由 鉑 所 構 成 而 第 -, 種 材 料 是 由 鋁 所 構 成 0 m. 些 層 可 項 1 盲 接 依 順 序 地 利 用 一 種 濺 鍍 設 備 來 施 加 t 其 中 只 有 m 填 寫 本 X ) '衣 (t a r κ e t)須 更 換 且 可 調 整 此 種 濺 鍍 過 程 之 參 數 〇 在 本 實 頁 --· 1 I 旃 例 中 第 二 種 材 料 必 須 可 選 擇 性 地 對 第 一 種 材 料 及 對 承 1 I 載 體 表 而 2 而 被 蝕 刻 1 但 不 可 對 位 障 材 料 選 擇 性 地 被 独 1 1 刻 r> 在 本 實 施 例 中 直 接 在 承 載 體 表 面 上 施 加 一 種 由 第 一 1 訂 種 材 料 所 構 成 之 層 t 此 種 層 序 列 之 取 上 層 是 由 第 一 種 材 1 1 料 所 構 成 0 1 1 第 2 圖 然 後 使 用 — 種 遮 罩 藉 由 非 等 向 性 蝕 刻 而 由 此 1 | 種 層 序 列 形 成 一 種 層 結 構 6 , 其橫向尺寸即為所欲製造 1 之 電 容 器 Μ 大 小 (包括至少在- -側面上所固定之前置 } 量 V ) 在 與 此 相 垂 直 橫 向 方 向 中 此 種 層 結 構 之 延 伸 量 較 1 J 佳 是 等 於 電 容 器 薄 Η 之 大 小 〇 隔離層2 之表面裸露於 1 r 層 結 構 之 旁 !·· 此 種 蝕 刻 過 程 可 使 用 C ! 2 1 Ar 9 Si C 1 4 或 ( PC I : i -Ί 層7 較佳是由第- -種材料以共形方式沈積而成 1 1 其 中 層 厚 度 是 在 10 - 1 0 0 n m 之 範 圍 中 〇 適 當 之 沈 積 方 法 1 例 如 是 C V D η J 第 3 圖 由 第 — 種 材 料 沈 積 而 成 之 層 Μ 由 等 向 性 之 回 I -1 0- 1 1 [ [ 本紙張尺度適用t國國家標準(CNS > A4規格(2丨Ο X 297公釐) 437〇7〇 A7 ____B7 _ 五、發明説明(9 ) (請先閱讀背面之注意事項再填寫本頁) 蝕刻而在層結構6之側壁上形成一種間隔層7 。非等向 件之轴刻可藉由醆镀蝕刻來進行。然後使用一種徹影術 所商生之遮罩藉由非等向性之蝕刻而對此種具有間隔層 7之層結構進行結構化,使得在一刨面上此間隔層7和 層结構6之一部份(即,先前所決定之前置量V)被去除 .、在此刨而上此種層結構於是具有一種邊線,鉛層6 i 之表而以及鋁層62裸露在此邊緣上。換言之,此層結 構中之一個開口(其位於此結構之一個側面上)須被蝕刻 。仍保存之間隔層7是一種支撑結構。 第4圖:由第二種材料構成之層& 2是藉由一種具有 等向性成份之蝕刻步驟來去除,此種蝕刻過程對這些由 第一材料,支撑結構7和承載體表面2所構成之層進行 侵触位障4是被第一'種材料所構成之最下層所保護。 以I比種方式而形成第一電極,其是由互柑隔離之薄Η 6 ,及支撑結構7所構成。支撑結構7使這些薄Η6,在 機械上及電性上互相連接且與承載體表面相連接。至接 點3, 4之接觸作用是由最下方之電容器薄Η來達成。電 容器介電質9 (其由高ε介電質或鐵電質所構成)是以習 經濟部智慧財產局員工消費合作社印製 知之方法沈積而成。所使用之高溫過程不會使位於深處 之結構被氣化,這是因為氣經由位障4之擴散作用已被 防lh 最後,施加一層導電層以形成反電極1 〇。 第4圖頭示另一種製作在承載體中之結構,此種結構 在安裝電容器時是存在於DRAM -電路中。第一電極. 7形成記億電容器之所謂記憶節點。第一電極經由其下 一 1 1 — 本紙張尺度適用中國國家標準(CMS ) A4g ( 2[0X297公釐) 43?C/7〇 A7 B7 經濟部智慈財產局員工消費合作社印製 五、發明説明( ) 1 1 方 之 接 觸 區 3 (其 設 有 上 述 之 擴 散 位 障 4 :(而與 選 擇 電 曰 B曰 體 1 '1 I 之 源 栩 / 汲 極 區 1 1相 連 接 〇 選 擇 電 晶 體 1 2之 另 __h 源 極 / 1 汲 極 區 1 2是 經 由 位 元 線 接 觸 區 1 4而 與 埋 入 式 位 元 線 15相 請 I 先 1 連 接 Γ. 較 佳 是 二 傾 相 m 之 記 億 胞 具 有 値 共 同 之 位 元 線 閱 讀 1 背 i 接 觸 區 埋 入 式 位 元 線 1 5和 位 元 線 接 觸 區 14是 由 隔 離 層 面 I 之 1 2 所 圍 嬈 〇 在 選 擇 電 晶 體 之 源 極 / 汲 極 區 1 1和 12之 間 配 注 意 1 I 事 1 置 通 道 區 16 閘 極 介 電 質 (未顯示)和 —- 種 作 為 字 兀 線 17 項 再 1 用 之 蘭 極 電 極 〇 字 元 線 17和位 元 線 接 觸 區 1 4分別 由 摻 雜 寫 ) 本 4^- 1 之 多 晶 矽 所 構 成 位 元 線 15是 由 揍 雜 之 多 晶 砂 t 砂 化 物 .頁 、_-· 1 1 或 鎢 所 構 成 Ο 在 源 極 / 汲 極 區 11之 遠 離 位 元線1 5之側面 1 1 1 上 設 置 — 種 隔 離 結 構 (例如, -種以隔離材料填人之平坦 1 1 式 溝 渠 1 8 )以便使相鄰之選擇電晶體對( pa i r )之間形成 I 玎 隔 離 作 用 i'l 1 就 下 述 之 實 施 例 而 言 曰 疋 由 第 1 圖 所 示 之 結 構 開 始 0 1 1 第 5 圖 (第二實施例) 另 一 種 可 能 性 是 藉 由 導 電 層 1 I (待別是由第- -種材料) 之 非 等 向 性 傾 斜 式 蒸 發 而 在 層 1 結 構 6 之 側 壁 上 産 生 上 述 之 連 接 部 份 〇 於 是 由 層 序 列 6 1 ) Γ t 6 ^藉由非等向性之蝕刻而産生- -種層結構6 其 橫 向 1 ί 之 尺 寸 即 為 所 欲 製 成 之 電 容 器 薄 Η 〇 於 是 在 此 種 層 結 構 i ! 之 - 個 或 二 個 連 接 邊 緣 上 在 一 預 定 之 角 度 下 使 鉛 蒸 發 1 1 其 中 在 大 約 10 -4 Pa(帕) 時 使 用 — 種 電 子 柬 Μ 發 作 用 〇 須 ! 1 形 成 一 種 層 厚 度 大 約 是 10 -100 n id 之 支 結 構 7 , 由第- 1 和 第 一 種 材 料 所 構 成 之 各 層 之 表 面 裸 露 在 相 面 對 之 連 接 1 表 而 上 Λ m 表 示 : 不 須 對 一 個 開 Ρ 進 行 蝕 刻 卽 可 存 在 一 1 12 1 1 1 1 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 切〇7〇 A7 __B7_ 五、發明説明(") (請先閱讀背面之注意事項再填寫本頁) 禪輩剮開稗之層結構。但亦可在整面上(因此,不須使 用徹影術)進行一種短暫之非等向性蝕刻,以便在水平 而卜.去除一種可能是很薄之齡層。 第β圖:由第二種材料所構成之層6 2是以一種具有 等向件成份之蝕刻過程來去除,其對這些由第一種材料 ,支挖結構7和承載體表面2所構成之各層進行侵蝕。 位障彳是被此種由第一種材料所構成之最下層所保護。 以此種方式來形成第一電極,其是由互相隔開之薄Η 6 i 及安撐結構7所構成。支撑結構7使這些薄片6 i在機 槭上及電性上互相連接且與承載體表面相連接。至接點 3, 4之接觸作用是經由最下方之電容器薄Η來逹成。然 後以習知之方法來沈積此種由高ε介電質或鐵電質9所 構成之電容器介電質。此處所使用之高溫過程不會使位 於深處之結構被氣化,這是因為氧經由位障4之擴散作 用已被防It。最後,沈積一種導電層以形成反電極1 〇。 使用在DRAM記億胞時當然可在基板中製成此種只顯示在 第4圖中之結構且在所有其它實施例時同樣可製成此種 結構 經濟部智慧財產局員工消費合作社印製 第7圖:在第3實施例中,支撑結構形成在層結構6 之所有連接邊綠上。此外,將描述一種蝕刻停止層(其 基本上可使用在所有之實施例中)之使用。在承載體(其 如第1圖所述包括:矽基板,隔離層2, —種具有位障 4之接點3)上施加一種層序列,其具有交替配置之層6〇_ (由第一種材料構成)及另一層62 (由第二種材料構成)。 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 437〇7〇 Μ B7 經濟部智慧財產局員工消費合作社印製 五、發明説明 ( ) 1 1 由 第 —-- 種 材 料 構 成 之 層 直 接 位 於 承 載 體 表 商 上 〇 若 不 用 1 '1 | 此 種 由 第 二 種 材 料 所 構 成 之 取 下 層 9 則 亦 可 施 加 一 種 蝕 1 刻 停 il: 層 5 . 即, 最下方之第= 二層不是由第二種材料構成 f—'、 請 1 I 1 而 由 另 — 種 材 料 (第— •和第二種材料都可選擇招 E 11 ί 閱 if 1 脅 1 對 此 種 材 料 而 被 蝕 刻 )所構成。 第- -種材料例5丨 ]是餡, 面 之 m 二 種 材 料 曰 疋 A t (鋁) 且 蝕 刻 ίψ 止 層 5 曰 疋 由 TE0S 或 氮 化 物 注 意 1 ί 事 1 所 構 成 〇 此 外 > 種 R u 0/T i -層序列是適用的。 這些層 項 再 J ] 可 由 濺 鍍 過 程 來 形 成 〇 在 本 實 施 例 中 此 層 序 列 之 取 上 層 寫 本 / 、裝 是 由 第 種 材 料 所 構 成 ΰ 頁 i 1 第 8 圖 : 妖 /IS-1 後 使 用 種 遮 罩 藉 由 非 等 向 性 之 f虫 刻 而 由 1 | 1比 種 層 序 列 (包括此蝕刻停止層5 )形成- -種層結構6 t 於 1 1 是 情 況 須 要 時 以 二 値 或 三 個 蝕 刻 步 驟 來 對 蝕 刻 停 止 層 5 1 訂 I I 進 行 蝕 刻 〇 此 種 等 向 性 之 蝕 刻 能 以 濺 鍍 言虫 刻 法 來 進 行 〇 就 此 種 蝕 刻 停 ih 層 之 蝕 刻 而 言 可 使 用 一 般 之 方 法 〇 隔 離 1 1 層 2 之 表 而 裸 露 在 層 結 構 6 之 旁 〇 1 | 第 9 圖 在 整 艏 配 置 上 以 丑 户·、 形 方 式 (c on f 0 「m )施加- 1 ί \ 種 由 第 種 材 料 所 構 成 之 層 7 〇 這樣可使層結構6 之所 } \ 有 連 接 邊 線 被 此 層 7 所 覆 JOl. Ο i f 第 1 0 圖 藉 肋 於 整 面 之 非 等 向 性 蝕 刻 而 由 層 7 來 對 — t ί 種 間 隔 層 (5 P a c e r ) 進 行 蝕 刻 〇 間 隔 層 形 成 上 述 之 支 撑 結 1 構 7 ,, 然後使闬- -種光罩而對層結構中之開口 8 進行蝕刻 1 I > 此 種 開 P 8 可 使 這 由 第 一 種 和 第 二 種 材 料 所 構 成 之 1 1 層 之 表 而 裸 露 出 來 〇 在 本 實 施 例 中 此 開 P 疋 位 於 此 結 構 [ 1 之 内 部 中 〇 於 白 aH 首 先 在 種 非 等 向 性 之 独 刻 步 驟 中 對 此 1 1 -1 4- 1 1 1 i 本紙張尺度適用中國國家標準(CNS ) Α4規格{ 2丨0Χ297公釐) A7 B7 437〇7〇 五、發明説明(β ) 種層序列進行蝕刻直至蝕刻停止層5為止。 (請先間讀背面之注意事項再填寫本頁) 第1 1.圖:然後在一種具有等向性成份之蝕刻步驟中選 擇件地對第一種材料來去除上述之蝕刻停止層5 f,由第 二種材料所構成之層6 2是以一種具有等向性成份之蝕 刻步驟來去除,此種蝕刻步驟會侵蝕這些由第一種材料 所構成之層但不侵牲此支撑結構7 (可以在蝕刻停止層5 去除之前,之後或同時以此種方式來製成一種含有 眚金屣之第一電極。支撑結構7使電極之所有外側上之 薄Η 6 !在機槭上及電性上互相連接。至接點3 , 4之電 件接觸作用是藉由電極最下方之蒲Η (其可靠地S蓋著 此種接點)來逹成。在形成此開口 8時最下方之薄Η被 蝕刻或過(ο ν e r )蝕刻以及因此而發生接觸不良此種危險 性時都可藉由蝕刻停止層5之使用而排除。 第12圖:然後就像先前之例子一樣製成電容器(産生 電容器介電質及反電極)。 經濟部智慧財產局員工消費合作社印製 第]3圖:在第四實施例中第一電極具有一種如EP 0779656A2中口所示之幾何形式。該文件第7至14圖中 所述之製造方法基本上可採用,其中此接點(該文件以2 3 表示)設有一種位障且層序列及支撑結構之材料以及所 使闬之蝕刻過程可依據本發明來改變。由第1圖開始, 層序列被蝕刻至層結構6 ,其覆蓋二個相鄰之接點3,3 ’ 巨其横向大小是二個相鄱之電容器(或其薄Μ )之大小。 在靥結構6之邊緣上産生一種間隔層7以作為支撑結構 。適當之蝕刻過程及沈積過程已說明在第一實施例中。 -1 5 -本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) 43?〇7〇 υ A7 B7 五、發明説明(4 ) 隔離層2表而裸露在層結構6和支if結構7之外部。 第1 4圖:使用一種由撤影術所産生之遮罩,刖層結構 β藉由開口之非等向性蝕刻而制分成二個部份區域,此 二値部份蕻由一種間隙而互相隔開。隔離層2之表面裸 露在此間隙之區域中。此二痼部份區域具有此種層序列 之各靥之已裸露的表面。殘留之間隔層7是供每一艏部 份區域用之支撑結構7。由第二種材料所構成之層6 2是 以一種具有等向性成份之蝕刻步驟來去除,此種蝕刻步 驟會侵蝕這®由第一種材料,支撑結構?及承載體表面 2所構成之層。位障4是由第一種材料所構成之最下層 來保護,..以此種方式可形成二痼相鄰之第一電極,其是 由互相隔開之薄Η 6 i及支撑結構7所構成且相互間是 藉由間隙所隔開。支撑結構7使電容器之薄片6 i在三 個側面上及在機械上和電性上互相連接大且與承載體表 而相連接。至接點3 , 4接觸作用是藉由電容器最下方之 薄(=1來達成。以習知方法來施加此種由高ε介電質或鐵 霄質9所構成之電容器介電質。所使用之高溫過程不會 使位於深處之結構被氣化,因為氣經由位障4 , 4 ’之擴 經濟部智慧財產局員工消費合作社印製 ^^1 1— - I ^^^1 ^^^1 ^^^1 .^1^1 . ^^^1 ^^^1 ^^^1 ^^^1 ^^^1----- J«. (請先閱讀背面之注意事項再填寫本頁) 散已被防丨h。最後,施加一種導電層以形成反電極1 〇。 在以下之實施例(第5及第6 )中,電容器之各薄Η是 藉由一種在内部延伸之支撑結構在機槭上及電性上互相 連接。相同之參考符號會用在目前之例子中;只有這些 和先前已詳述之方法不同之處才會説明。 第15圖:在隔離層2上形成一種例如由TEOS或氮化物 -1 6 -本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)Turbidity structure titanium is connected to 0 and § makes 0L and mesoporous nitrogen-based. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 4S? 〇A7 B7 Intellectual Property Office of the Ministry of Economic Affairs Printed by the Employee Consumer Cooperative Co., Ltd. 5. Description of invention (ί) ί 1 Source / drain region of m-selective crystal in the board. Preferably, a contact barrier 3 is placed in the upper part of the contact hole 3. The diffusion of gas can be relied on. The manufacturing method of this type of barrier 1 [for example, 茌 DE -1.94 4 0 2 46 > DE -1 96 40 44 8 Now applied on the surface — *-seed layer sequence m read 1 back 1 which contains alternately arranged layers 6 1 (consisting of the __. Seed material containing precious metals) and layer 6 2 (by the second Material composition) 〇 The first material attention 1 1 For example, it is composed of platinum and the first-, the material is composed of aluminum 0 m. Some layers can be item 1 Blindly follow Use a sputtering equipment to apply t, of which only m is filled in this X) 'Cloth (tar κ et) must be replaced and the parameters of this sputtering process can be adjusted. In this real page-· 1 I The two materials must be able to be selectively etched on the first material and on the carrier surface, but the carrier material cannot be selectively etched, but the barrier material cannot be selectively etched in the present embodiment. A layer t made of the first 1 order material is applied on the surface of the body. The upper layer of this layer sequence is made of the first material 1 1 material 0 1 1 The second picture is then used-a mask by non Isotropic etching results in a layer structure 6 from this 1 | layer sequence, whose lateral dimension is the size of the capacitor M to be manufactured 1 (including the amount V at least before being fixed on the-side). Extension of this layer structure in the vertical transverse direction of this phase 1 J is preferably equal to the size of the capacitor thin layer. 0 The surface of the isolation layer 2 is exposed next to the 1 r layer structure! ... This etching process can use C! 2 1 Ar 9 Si C 1 4 or (PC I: i- Ί Layer 7 is preferably deposited in conformal manner from the first-1 material, where the layer thickness is in the range of 10-100 nm. Appropriate deposition method 1 For example, CVD η J Figure 3 The first layer of material M is deposited by the isotropic return I -1 0- 1 1 [[This paper size applies to national standards (CNS > A4 specifications (2 丨 〇 X 297 mm) 437〇 7〇A7 ____B7 _ V. Description of the Invention (9) (Please read the precautions on the back before filling this page) Etching forms a spacer layer 7 on the sidewall of the layer structure 6. Axial engraving of non-isotropic parts can be performed by holmium etching. Then a mask created by shadowing is used to structure the layer structure with the spacer layer 7 by anisotropic etching, so that the spacer layer 7 and the layer structure 6 A part (that is, the previously determined previous amount V) is removed. The layer structure on this plane then has an edge, the surface of the lead layer 6 i and the aluminum layer 62 are exposed on this edge. In other words, an opening in the layer structure (which is on one side of the structure) must be etched. The remaining spacer layer 7 is a supporting structure. Figure 4: The layer made of the second material & 2 is removed by an etching step with an isotropic composition. This etching process is made of the first material, the support structure 7 and the surface 2 of the carrier. The layer constituting the invasion barrier 4 is protected by the lowest layer made of the first material. The first electrode is formed in an I ratio manner, which is composed of a thin layer 6 isolated from each other and a support structure 7. The supporting structure 7 connects these thin cymbals 6 mechanically and electrically to each other and to the surface of the carrier. The contact to the contacts 3, 4 is achieved by the thinnest capacitor. The capacitor dielectric 9 (consisting of a high-ε dielectric or ferroelectric) is deposited by a method known to the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The high-temperature process used does not vaporize the structure located in the deep, because the diffusion of gas through the barrier 4 has been prevented for 1 h. Finally, a conductive layer is applied to form the counter electrode 10. Figure 4 shows another structure made in the carrier. This structure exists in the DRAM-circuit when the capacitor is mounted. The first electrode. 7 forms a so-called memory node of a billion capacitor. The first electrode passes its next 1 1 — This paper size applies the Chinese National Standard (CMS) A4g (2 [0X297 mm) 43? C / 70A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs Explanation () 1 1 Fang's contact area 3 (which is provided with the above-mentioned diffusion barrier 4: (and is connected to the source electrode / drain region 1 1 of the selected body B 1 body 1 '1 I 0 selected transistor 1) 2 of the other __h source / 1 drain region 1 2 is through the bit line contact region 14 and phase with the embedded bit line 15 please I connect 1 first Γ. The dip phase m The cell has a common bit line reading 1. The back contact area is embedded with the bit line 15 and the bit line contact area 14 is surrounded by the isolation layer I 1 2. In selecting the source / sink of the transistor Polar region 1 Note 1 1 between 12 and 1 event 1 channel region 16 gate dielectric (not shown) ) And --- a kind of blue electrode used as the 17th item of the word line 1 the word line 17 and the bit line contact area 14 are written by doping) the bit line 15 made of polycrystalline silicon of 4 ^ -1 It is composed of doped polycrystalline sand t sand. Page, _- · 1 1 or tungsten 〇 It is set on the side of the source / drain region 11 away from the bit line 1 5 1 1 1 — an isolation structure (For example, a flat 1 1 type trench 18 filled with insulating material) so that adjacent selective transistor pairs (pa ir) form I 玎 isolation i′l 1 according to the following embodiment The words 疋 start from the structure shown in Figure 1 0 1 1 Figure 5 (Second Embodiment) Another possibility is through the anisotropy of the conductive layer 1 I (to be different from the-material) (The inclined connection evaporates to generate the above-mentioned connecting part on the side wall of the layer 1 structure 6. Therefore, the layer sequence 6 1) t 6 ^ produced by non-isotropic etching--seed layer structure 6 whose size in the lateral direction 1 ί is the desired thin capacitor Η so 〇-in this layer structure i or two Lead evaporates at a predetermined angle on the edge of the connection 1 1 which is used at about 10 -4 Pa (Pa)-a kind of electron beam is generated 0 must! 1 forms a branch with a layer thickness of about 10 -100 n id Structure 7, the surface of each layer composed of the first-1 and the first material is exposed on the facing connection 1 and Λ m indicates that: there is no need to etch an opening. There may be a 1 12 1 1 1 1 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) cut 〇〇〇〇7 __B7_ 5. Description of invention (") (Please read the precautions on the back before filling this page) Its layer structure. However, a brief anisotropic etch can also be performed on the entire surface (thus, no shadowing is required) in order to remove a potentially thin age layer at a horizontal level. Figure β: The layer 62 made of the second material is removed by an etching process with an isotropic component. These layers are made of the first material, the support structure 7 and the surface 2 of the carrier. The layers are eroded. The barrier is protected by the lowest layer of this first material. The first electrode is formed in this way, and is composed of a thin Η 6 i and a support structure 7 which are separated from each other. The supporting structure 7 connects the sheets 6 i to each other both electrically and electrically and to the surface of the carrier. The contact to the contacts 3, 4 is formed by the capacitor thin film at the bottom. Such a capacitor dielectric composed of a high ε dielectric or a ferroelectric 9 is then deposited in a conventional manner. The high temperature process used here does not vaporize the structure located deep, because the diffusion of oxygen through the barrier 4 is prevented from it. Finally, a conductive layer is deposited to form the counter electrode 10. When used in DRAM memory cell, of course, the structure shown in Figure 4 can be made in the substrate, and it can also be made in all other embodiments. This structure is printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives. Figure 7: In the third embodiment, the supporting structure is formed on all the connecting edges of the layer structure 6 green. In addition, the use of an etch stop layer, which can be used in substantially all embodiments, will be described. A layer sequence is applied to a carrier (which includes a silicon substrate, an isolation layer 2, and a contact 3 with a barrier 4 as described in FIG. 1), which have alternately arranged layers 6〇_ (from the first One material) and another layer 62 (consisting of a second material). This paper size applies the Chinese National Standard (CNS) A4 specification (210X297mm) 437〇7〇Μ B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () The layer is directly on the surface of the carrier. If 1 '1 | is not used, this type of the lower layer 9 made of the second material can also be applied with an etch 1 etch stop: layer 5. That is, the bottommost = The second layer is not composed of the second material f— ', please 1 I 1 and the other material (the first and second materials can choose to recruit E 11 ί see if 1 threat 1 to this material and be Etching). The first-material example 5 丨] is stuffing, the surface of the two materials is 疋 A t (aluminum) and etched ψψ stop layer 5 疋 疋 is composed of TE0S or nitride Note 1 ί Thing 1 〇 In addition > species R u 0 / T i -layer sequences are applicable. These layer items can be formed by the sputtering process. In this embodiment, the upper layer of this layer sequence is taken from / and the package is composed of the first material. Page i 1 Figure 8: Use after the demon / IS-1 The seed mask is formed by a non-isotropic f engraving from a 1 | 1 ratio seed layer sequence (including this etch stop layer 5)--seed layer structure 6 t where 1 1 is two or three when the situation requires Etching step to etch the etch stop layer 5 1 Order II. This isotropic etch can be performed by sputtering method. For this type of etch stop ih layer etching, general methods can be used. Isolation 1 1 The table of layer 2 is exposed beside the layer structure 6 〇1 | The figure 9 is applied in an ugly manner (c on f 0 "m) on the overall arrangement-1 ί \ species by the first material The layer 7 is constructed so that the layer structure 6 can be placed} \ There are connecting edges covered by this layer 7 JOl. 〇 Figure 10 shows if layer 10 is used to etch a spacer layer (5 Pacer) by using anisotropic etching on the entire surface. The spacer layer forms the support structure 1 described above, and then闬--a mask is used to etch the opening 8 in the layer structure 1 I > This opening P 8 can make the surface of the 1 1 layer composed of the first and second materials exposed. In the present embodiment, the opening P 疋 is located in the interior of the structure [1] Yu Bai aH. First, this is done in a non-isotropic step. 1 1 -1 4- 1 1 1 i This paper size applies to China Standard (CNS) A4 specification {2 丨 0 × 297 mm) A7 B7 437〇705. Description of the invention (β) The layer sequence is etched until the etch stop layer 5. (Please read the precautions on the back first and then fill out this page) Figure 1 1. Figure: Then select the first material to remove the above-mentioned etch stop layer 5 f in an etching step with isotropic composition, The layer 62 made of the second material is removed by an etching step with an isotropic composition. This etching step will erode the layers made of the first material but not the support structure 7 ( A first electrode containing rhenium can be made in this way before, after, or at the same time as the etching stop layer 5 is removed. The support structure 7 makes thin Η on all outer sides of the electrode 6! The upper part is connected to each other. The contact of the electrical parts to the contacts 3, 4 is formed by the bottom of the electrode (which reliably covers S contacts). The thinnest part when forming this opening 8 The risk of 危险 being etched or over-etched (ο ν er) and consequently poor contact can be ruled out by using the etch stop layer 5. Figure 12: The capacitor is then made like the previous example ( Generate capacitor dielectric and counter electrode). Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives] Figure 3: In the fourth embodiment, the first electrode has a geometric form as shown in the mouth of EP 0779656A2. The manufacturing method described in Figures 7 to 14 of this document is basically It can be used, where the contact (the document is indicated by 2 3) is provided with a barrier, the material of the layer sequence and the support structure, and the etching process of the plutonium can be changed according to the present invention. Starting from Figure 1, the layer The sequence is etched to the layer structure 6, which covers two adjacent contacts 3, 3 '. Its lateral size is the size of two adjacent capacitors (or its thin M). A kind of edge is generated on the edge of the rhenium structure 6. The spacer layer 7 is used as a supporting structure. The appropriate etching process and deposition process have been described in the first embodiment. 1-5-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 43? 07 〇υ A7 B7 V. Description of the invention (4) The isolation layer 2 is exposed on the outside of the layer structure 6 and the branch if structure 7. Figure 14: Using a mask produced by shadow removal, the layer structure β Divided into two by anisotropic etching of the opening The two regions are separated from each other by a gap. The surface of the isolation layer 2 is exposed in the region of the gap. The two regions have exposed surfaces of each layer of this layer sequence. The remaining spacer layer 7 is a supporting structure 7 for each part of the region. The layer 62 made of the second material is removed by an etching step with an isotropic composition, which will erode This ® is composed of the first material, the support structure? And the carrier surface 2. The barrier 4 is protected by the lowest layer of the first material. In this way, two adjacent sides can be formed. The first electrode is composed of thin Η 6 i and support structure 7 which are separated from each other and is separated by a gap. The support structure 7 enables the thin sheet 6 i of the capacitor to be connected to each other on three sides, mechanically and electrically, and to the surface of the carrier body. The contact to the contacts 3, 4 is achieved by the thinnest (= 1 of the capacitor). The capacitor dielectric of high ε dielectric or iron matrix 9 is applied by conventional methods. The high temperature process used will not gasify the structure located in the deep, because the gas is printed through the barriers 4, 4 '. ^ 1 ^^^ 1. ^ 1 ^ 1. ^^^ 1 ^^^ 1 ^^^ 1 ^^^ 1 ^^^ 1 ----- J «. (Please read the notes on the back before filling This page) has been prevented. Finally, a conductive layer is applied to form the counter electrode 10. In the following embodiments (5th and 6th), each thin layer of the capacitor is extended by an internal The supporting structure is electrically and electrically connected to each other. The same reference symbols will be used in the current example; only these differences from the previously detailed methods will be explained. Figure 15: On the isolation layer 2 Formed by, for example, TEOS or Nitride-1 6-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)

Is 經濟部智慧財產局員工消費合作杜印製 437^α __Β7_ 五、發明説明(β ) 構成之蝕刻停lh層5 (厚度大約是5 0 n in)以作為此種層序 列之最下層,> 此種層序列之位於最下層之上之此層就像 最..h層一樣是一種由第二種材料所構成之層6 2 ,但此 二層亦可由第一種材料構成。 第1 6圖:在此種層序列中對一個開口進行蝕刻直到蝕 刻停出層β為出,,可使用一種如上所述之以含有氯之氣 體來丨隹行之蝕刻過程《在第二飩刻步驟中是以C 2 F e / C H h夾對蝕刻停止層5進行蝕刻旦使接點之位障層4 裸露出來...須選取此種蝕刻.步驟,使位障不會受到損害 開口中镇入第一種材料,較佳是在此種層序列之水平 表面上亦沈積第一種材料。 第1 ?圖··然後在一種非等向性之選擇性地對此蝕刻停 lh層所進行之蝕刻過程中使層序列6 1 , 6 2結構化成層 結構<5。 第1 8圖:如上述一般來對簿K 6 i進行一種淸除式(free) 蝕刻.其中此種蝕刻是選擇性地對第一種材料和對蝕刻 停11:層來進行。在使用鈦時,例如可使用N Η 4 0 H / H 2 0 2 來谁行之濕式化學蝕刻,其選擇性對以鉑作為蝕刻停止 曆時至少是1 : 1. 0 0目.在以氮化物作為蝕刻停止層時至少 是"I : 1 0 0。 第1 9圖:触刻停[h層可保存在承載體上,特別是當一 種由第二材料構成之層6 2配置在其上時更是如此。電 容器是藉由高e介電質9或鐵電質形成於裸露之表面上 以及産生反電極1 0而形成。 Ί7- (請先閱讀背面之注意事項再填爲本頁) 本纸張尺度適用中國國家標準(CNS ) A4規格(2丨OX 297公釐) B7 經濟部智慧財產局員工消費合作社印製Is Consumption Cooperation of Employees of Intellectual Property Bureau of the Ministry of Economic Affairs, printed 437 ^ α __Β7_ V. Etching stop lh layer 5 (thickness about 50 n in) composed of invention description (β) as the lowest layer of this layer sequence, & gt This layer sequence is located above the lowest layer. This layer is just like the most ..h layer is a layer made of the second material 6 2, but these two layers can also be made of the first material. Figure 16: In this layer sequence, an opening is etched until the etch stop layer β is out, and an etching process using a gas containing chlorine as described above can be used. In the engraving step, the etching stop layer 5 is etched with a C 2 F e / CH h clip to expose the barrier layer 4 of the contact ... This etching must be selected. The step is to prevent the barrier from being damaged. In the first material, it is preferred that the first material is also deposited on the horizontal surface of such a layer sequence. Figure 1 ··· Then the layer sequence 6 1, 6 2 is structured into a layer structure < 5 in an anisotropic selective etching process for this etching stop layer. Fig. 18: A free etching is performed on the book K 6 i as described above, wherein this etching is performed selectively on the first material and on the etch stop 11: layer. When using titanium, for example, N Η 4 0 H / H 2 0 2 can be used for wet chemical etching, and its selectivity for platinum as an etching stop lasts at least 1: 1. 0 0 mesh. In nitrogen When the compound is used as an etch stop layer, it is at least " I: 1 0 0. Figure 19: Touch-cut stop [h layer can be stored on the carrier, especially when a layer 62 made of a second material is arranged on it. The capacitor is formed by forming a high-e dielectric 9 or a ferroelectric on an exposed surface and generating a counter electrode 10. Ί7- (Please read the notes on the back before filling in this page) This paper size applies to China National Standard (CNS) A4 (2 丨 OX 297mm) B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

五、發明説明( 1 y ) 1 1 笔 20 圖 在 第 6 實 施 例 中 » 使 用 -^ 種 蝕 刻 停 止 層 (TE0S 1 ^ 1 [ 氤 化 的 )作為此種層序列之最下方第二 :層。 f 於 承 載 asth m 上 施 加 種 層 序 列 > 其 F7 取 下 層 疋 一 種 由 第 一 請 1 1 種 材 料 所 構 成 之 層 6 .而最下方第二層是- -種蝕刻停止 閱 讀 1 背 1 壩 5 , 忱種層序列上方交替地施加這些由第-- -(β 3 —) 和 第 1¾ 之 二 種 材 料 (6 2 >所構成之層。 注 意 1 1 事 1 第 2 1 圖 在 此 種 層 序 列 中 對 „- 値 開 Ρ 進 行 蝕 刻 停 止 層 XF\ 再 ί ·\ 5 為 ih 此 處 可 使 用 一 種 以 含 有 氣 之 氣 體 來 進 行 之 R I E 填 寫 ) 裝 渦 稈 1-i 在 第 二 η 刻 步 驟 中 以 C ; F 6 /C H F 3 來 對 此 蝕 刻 停 ' 頁 、W 1 j (Η 層 5 進 行 蝕 刻 ♦ 使 此 開 □ 中 可 裸 露 出 此 種 由 第 —' 種 材 1 Ι 料 所 構 成 之 最 下 層 之 表 面 〇 此 種 蝕 刻 步 驟 是 選 擇 性 地 對 1 1 第 一 種 材 料 來 進 行 此 開 P 中 是 以 第 一 種 材 料 植 入 較 ! 訂 1 I 佳 疋 在 1比 種 層 序 列 之 水 平 表 面 上 沈 積 第 一 種 材 料 0 第 22 圖 ; 然 後 在 ™- 種 非 等 向 性 之 蝕 刻 過 程 中 使 層 序 列 1 1 6 , 6 2 (包括此蝕刻停止層5 )被結構化成層結構6 ύ 可 1 1 能 時 可 進 行 與 此 相 關 之 多 値 独 刻 步 驟 0 承 載 體 表 面 2 裸 \ 露 於 層 結 構 之 旁 〇 Γ 第 2 3 圖 就 像 上 述 樣 對 薄 片 6 ^進行- -種自由蝕刻, 1 1 其 中 此 種 蝕 刻 曰 疋 選 擇 性 地 對 第 種 材 料 來 進 行 〇 相 對 於 ί I 触 剌 停 [h 層 之 )¾ 擇 性 是 不 須 要 的 〇 蝕 刻 停 止 暦 5 同 樣 須 Ί 被 去 除 〇 適 當 之 用 於 TE0S 和 氛 化 物 之 等 向 性 蝕 刻 過 rn W- 對 I 丨比 行 業 之 專 家 而 言 是 熟 悉 的 Λ 因 此 可 製 成 第 電 極 0 薄 i I Η 6 1 經由支撑結構而在機械上和電性上互相連接, 與 I 連 接 結 構 3 , 4之 接 觸 作 用 疋 藉 由 最 下 層 之 薄 片 來 達 成 〇 I -1 8 " I I I I 本紙張尺度適用中國國家標準(CNS > A4規格(2丨0 X 297公尨) 4W〇7〇 Λ7 B7 五、發明説明(q ) (請先閲讀背面之注意事項再填寫本頁) 因此介於支撐結構和接點之間的欠(de-)對準是不重量 的。不使用一種蝕刻停止層時亦可對最下方之薄片進行 蝕刻而此位障4可能受傷害。 第24圓:電容器是藉由高ε介電質9和鐵電質形成於 裸露之表面上以及產生反電極10而被製成。 符號之說明 1 基板 2 隔離層 3,3, 接觸孔 4,4, 位障 5 蝕刻停止層 6 層結構 7 間隔層 8 開口 9 鐵電質 10 反電極 11,12 源極/汲極區 14 位元線接觸區 15 位元線 16 通道區 17 字元線 18 溝渠 6卜62 層 -19- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) Α4規格(2丨0 X 297公釐)V. Description of the invention (1 y) 1 1 pen 20 drawings In the sixth embodiment »--etch stop layer (TE0S 1 ^ 1 [氤 化 的)] is used as the bottom second layer of this layer sequence. f Apply the seed layer sequence on the bearing asth m> Its F7 takes off the layer 疋 a layer made of 1 1 1 material 6 and the bottom 2 layer is--a kind of etching stop reading 1 back 1 dam 5 , These layers consisting of the two materials (6 2 >--(β 3 —) and 1¾ are alternately applied above the sequence of seed layer. Note 1 1 matter 1 Figure 2 1 is in this layer In the sequence, the etch stop layer XF \ is opened. XF \ ί · \ 5 is ih. Here, a RIE using a gas containing gas can be filled in.) Install the vortex 1-i in the second η step C; F 6 / CHF 3 to stop this etching, page, W 1 j (Η layer 5 etched ♦ so that the bottom layer of this kind of — 'seed material 1 Ⅰ material can be exposed in this opening □ The surface of this type of etching step is selectively performed on the 1st first material. This kind of material is implanted! Order 1 I Jiayu deposits the first material on the horizontal surface of the 1-layer layer sequence 0 Figure 22; and then makes the layer sequence 1 1 6 in a non-isotropic etching process 6 2 (including this etch stop layer 5) is structured into a layered structure 6 actor 1 1 can be carried out as many times as possible related to this step. 0 The surface of the carrier 2 is bare \ exposed next to the layer structure 〇Γ 第The 2 3 figure is like the above-mentioned sheet 6 ^-a kind of free etching, 1 1 where the etching is selectively performed on the first material 〇 relative to ί I contact stop [h layer of) ¾ Etching is not required. Etching stop is also required. It is also required to be removed. It is suitable for isotropic etching of TEOS and odorants. W- is more familiar to industry experts than I, so it can be made. The first electrode 0 thin i I 6 1 is mechanically and electrically connected to each other via a supporting structure The contact with the I connection structure 3, 4 can be achieved by the lowest sheet 〇I -1 8 " IIII This paper size applies to Chinese national standards (CNS > A4 specifications (2 丨 0 X 297 cm) 4W〇7〇Λ7 B7 V. Description of the invention (q) (Please read the precautions on the back before filling this page) Therefore, the under-alignment between the support structure and the contacts is not weight. It is also possible to etch the lowermost sheet without using an etch stop layer and the barrier 4 may be damaged. Round 24: The capacitor is made by forming a high ε dielectric 9 and a ferroelectric on an exposed surface and generating a counter electrode 10. Explanation of symbols 1 substrate 2 isolation layers 3, 3, contact holes 4, 4, barriers 5 etch stop layer 6 layer structure 7 spacer layer 8 opening 9 ferroelectric 10 counter electrode 11, 12 source / drain region 14 bits Yuan line contact area 15 bit line 16 Corridor area 17 character line 18 Ditch 6 bu 62 floor -19- Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperative Cooperative This paper is printed in accordance with the Chinese National Standard (CNS) Α4 Specification (2 丨 0 X 297 mm)

Claims (1)

^ft/@14492號『依據廳狀堆疊原理具有ε介電質或鐵電質之電容器及其製造方法』 專利鬉 88年12日,TF C 六、申請專利範圍^ ft / @ 14492 "Capacitor with ε-dielectric or ferroelectricity and its manufacturing method according to the hall-shaped stacking principle" Patent 日 12, 1988, TFC VI. Application scope 揷霜容器,其配置在承載體上之半導體配置中,包 栝 經濟部智慧財產局員工消費合作社印製 - 一禪含有貴金隰之第一電極(6 i , 7 ), -.一揮-雷容器鐵電質(9 ),其是高ε介電質或鐵電質 材料所構成, -一種第二電極(1 0 ), 其特徴為:第一電極(6ι , 7)具有至少二値互相隔 開之簿!={ ( 6 1 ),這些薄K基本上是與承載體表面相 平行地配置箸且經由一種支撑.結構(7 )而在機槭上及 電件上互相連接。 2. 如申請專利範圍第1項之電容器,其中這些薄H (6l·) 猙由支撑結構(7 )而與承載體U , 2 )在電性上互相連 接 3. 如申請專利範圍第2項之電容器,其中此支撑結構(Ή 配置在薄Η ( 6 i )之至少一個連接邊綠上。 4. 如申請專利範圍第1或第2項之電容器,其中此支撑 結構(7)經由薄片而延伸。 5. 如申請專利範圍第1或第2項之電容器,其中承 載體在其面向電容之表面上具有一種隔離層(2)(其 中配置一種接觸區(3)),此接觸區(3)包括一種擴散 位障(4 )且與第一電極(6 i ,7 )相連接。 6 .如申請專利範圍第5項之電容器,其中此承載體包含 一種Μ 0 S電晶體巨接觸區(3 )使此電晶髏之源極/汲極 區Μ 1 )能與第一雷極(6丄,7 )相建接。 修煩 手諳 本委 f員 f明 Ϊ示葛年 容/1^ +日 ί所 正提 之 (請先閱讀背面之注意事項乒填寫本頁) 1Ί· .韓· 20 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ο ?34 A8SSS 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 7 . —稀如申請專利範圍第1項所述電容器之製造方法, 其恃徽為: -存承載體(1 , 2 )之表面上産生一種層序列,其交替 包含.一揮由含有貴金屬之第一種材料(6 i )所構成 之層以及一種由第二種材料(6 2 )所構成之層,第二 種材料可選擇性地對第一種材料而被蝕刻, -層序列被蝕刻成一種具有邊緣之層結構(6), •須形成一種靥結構(7 ),其覆蓋此種層結構(& )之至 少一邊緣且在機械上及電性上使這些由第一種材料 所構成之層相連接, -使這些由第二材料所構成之層(6 2 )選擇性地對這些 由第一種材料所構成之層及對支撑結構(7 )而被去除 -在這柴由第一種材料和支撑結構(6 1 , 7 )所構成之 層之裸露之表而上以共形方式(conform)施加一種 由高£介電質或鐵電質材料所構成之電容器介電質 m, --在電容器介電質上産生第二電極(1 〇 ) ,:· 8.如申請專利範圍第7項之方法,其中此種支撑結構藉 肋於第一種材料之共形方式之沣積以及隨..後非等_向性 之回蝕刻而産生以形成間隔層,然後對此種層結構中 之開口 U )進行蝕刻,此開口( 8 )使這些由第一種和第 二種材料所構成之各層之表面裸露出來。 9 .如申請專利範圍第8項之方法,其中該開口是位於層 結構(6 )之邊線。 -2 1 - 本紙張尺度適用尹國國家標準(CNS)A4規格(2〗〇χ 297公Μ ) ------------^^裝--------訂---------線. <請先閲讀背面之注意事項再填寫本頁) ?〇 γ Ο Α8 Β8 CS DS 六、申請專利範圍 I 0 .如申請專利範圍第8項之方法,其中該開口是位於層 結構之内部,使支撑結構保存在層結構之所有連接邊 (請先閱讀背面之注意事項再填寫本頁) 線上,:. II ,如申請專利範圍第8項之方法,其中在層結構中形成 上述之開口時層結構是以支撑結構而劃分成二値部份 區域,此二個部份區域是以一値間隙隔開,每一個部 份區域是電容器之第一電極。 1 2 .如申請專利範圍第7項之方法,其中該支撑結構藉 肋於非等向性之傾斜式蒸發過择而産生。 13. —種如申請專利範圍策1項所述電容器之製造方法, 其特徵為: -在承載體(1,_2)之表面上産生一種層序列,其交替 地包含一種由含有貴金屬之第一種材料(6i )所構成 之層以及一種由第二種材料(6 2 )所構成之層,第二 種材料可選擇性地對第一種材料而被蝕刻, -在層序列中形成一値開口, 經濟部智慧財產局員工消費合作社印製 -在此開口中形成一個支撑結構(7),其填入此開口中, -此種層序列在一種非等向性之蝕刻過程中被蝕刻成 一種層結構(6),其具有位於内部之支撑結構, -由第二種材料所構成之層(62)選擇性地對此種由 第一種材料所構成之層(6 i )及對該支撑結構(7 )而 被去除, -在此種由第一種材料及支撑結構Ut , 7)所構成之 層之裸露之表面上以共肢方式沈積一種由高e介電 -22 - 本紙張尺度適用中@國家標準<CNS)A4規格(210x 297公.爱) AS B8 C8 DS 7〇 六、申請專利範圍 暂或鐵霄質材料所構成之電容器介電質(9 ), ~芘雷容器介電質(9 )上産生第二電極Π 〇 )。 1 4 .如申請專利範圍第? - 1 3項中任一項之方法,其中這些 '層(6 )是由第一種材料(例如,P t , I r或1U 0 )所産生, 而请哩層(6 7 )是由第二種材料(其是可選撣性地對第 一種材料而被鈾刻之金屬,恃別是A 1或T i )所産生。 15. 如申請專利範圍第7 - 1 3項中任一項之方法’其中在承 載體(2)上或在此種層序列上之最下層上施加一種蝕 刻停止層(5)。 16. 申請專利範圍第14項之方法,其中在承載體(2)上或 在此種層序列上之最下層上施加一種蝕刻停止層 (5}。 (請先閱讀背面之注意事項再填寫本頁) · 線_ 經濟部智慧財產局員工消費合作社印製 -23- 本紙張尺度適用中固國家標準(CNS)A4規格(210 x 297公爱)The arsenic container, which is arranged in a semiconductor configuration on the carrier, is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-Yizen contains the first electrode of precious gold tincture (6i, 7),-. A container ferroelectric (9), which is composed of a high ε dielectric or ferroelectric material,-a second electrode (1 0), characterized in that the first electrode (6, 7) has at least two Divided book! = {(6 1), these thin Ks are basically arranged in parallel with the surface of the carrier, and are connected to each other on the maple and the electrical parts via a support structure (7). 2. As for the capacitor in the scope of patent application, the thin H (6l ·) 狰 is electrically connected to the carrier U, 2) by the support structure (7) 3. In the scope of patent application, the second A capacitor in which the supporting structure (Ή is arranged on at least one connecting edge of thin Η (6 i). 4. For a capacitor in the scope of patent application item 1 or 2, wherein the supporting structure (7) is via a sheet 5. If the capacitor of the first or second patent application scope, the carrier has an isolation layer (2) on its surface facing the capacitor (where a contact area (3) is configured), ) Includes a diffusion barrier (4) and is connected to the first electrode (6i, 7). 6. The capacitor according to item 5 of the patent application, wherein the carrier includes a MOS transistor giant contact area ( 3) The source / drain region M 1) of the electric crystal skull can be connected to the first thunder pole (6 丄, 7). Repair troubles, members of this committee, f, Ming Ming, Ge Nianrong / 1 ^ + Japanese, as mentioned (please read the precautions on the back and fill out this page) 1Ί ··················· This paper size applies to China Standard (CNS) A4 specification (210 X 297 mm) ο? 34 A8SSS Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Scope of patent application 7-Manufacturing method of capacitor as described in item 1 of the scope of patent application, Its emblem is:-A layer sequence is generated on the surface of the storage carrier (1, 2), which alternately contains. A layer composed of a first material (6i) containing a precious metal and a second material (6 2), the second material can be selectively etched to the first material,-the layer sequence is etched into a layer structure with edges (6), • a pseudo structure must be formed (7 ), Which covers at least one edge of this layer structure (&) and mechanically and electrically connects these layers made of the first material,-makes these layers made of the second material ( 6 2) Selectively these are composed of the first material The layer and the support structure (7) are removed-on the exposed surface of the layer made of the first material and the support structure (6 1, 7), a conformal method is applied in a conformal manner. £ Dielectric or ferroelectric material made of capacitor dielectric m,-to produce a second electrode (10) on the capacitor dielectric: 8. The method according to item 7 of the patent application, where This support structure is produced by the accumulation of the ribs in the conformal way of the first material and the subsequent non-isotropic etchback to form the spacer layer, and then the opening U in this layer structure is performed. By etching, this opening (8) exposes the surfaces of the layers made of the first and second materials. 9. The method according to item 8 of the scope of patent application, wherein the opening is located on the edge of the layer structure (6). -2 1-This paper size is applicable to Yin National Standard (CNS) A4 specification (2〗 〇297 Μ) ------------ ^^ 装 -------- Order --------- line. ≪ Please read the notes on the back before filling in this page) 〇γ 〇 Α8 Β8 CS DS VI. Application for patent scope I 0. For the method of applying for patent scope item 8 Among them, the opening is located inside the layer structure, so that the supporting structure is stored on all the connecting edges of the layer structure (please read the precautions on the back before filling this page) Online: .II, such as the method of applying for the scope of the patent No. 8 When the above-mentioned openings are formed in the layer structure, the layer structure is divided into two parts by a supporting structure, and the two parts are separated by a gap. Each part is the first of the capacitor. electrode. 12. The method according to item 7 of the scope of patent application, wherein the supporting structure is generated by the ribs being non-isotropically inclined and evaporated. 13. —A method for manufacturing a capacitor as described in item 1 of the patent application scope, characterized in that:-a layer sequence is generated on the surface of the carrier (1, _2), which alternately contains a first A layer made of one material (6i) and a layer made of a second material (62), the second material can be selectively etched to the first material,-forming a stack in the layer sequence The opening is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-a support structure (7) is formed in this opening, which is filled in this opening,-this layer sequence is etched in an anisotropic etching process A layer structure (6) having a supporting structure located in the interior,-a layer (62) composed of a second material is selectively applied to the layer (6i) composed of the first material and The support structure (7) is removed,-on a bare surface of such a layer composed of the first material and the support structure Ut, 7) a co-limb deposit of a high-e dielectric -22 is made-this paper Standards are applicable to @National Standards < CNS) A4 specifications (210x 297 male. Love) AS B8 C8 DS 7 0 6. Scope of patent application Capacitor dielectric (9) composed of temporary or iron materials, ~ The second electrode Π 〇 is generated on the dielectric of the thunder container (9). 1 4. What is the scope of patent application? -The method of any of 13 items, wherein the 'layer (6) is produced by the first material (for example, P t, I r or 1U 0), and the stratum (6 7) is produced by the first Two materials (which are metals that are optionally engraved with uranium to the first material, specifically A 1 or T i) are produced. 15. The method according to any one of claims 7 to 13 of the scope of patent application ', wherein an etch stop layer (5) is applied on the carrier (2) or on the lowest layer of such a layer sequence. 16. The method of applying for item No. 14 of the patent scope, wherein an etch stop layer (5) is applied on the carrier (2) or on the lowest layer of this layer sequence. (Please read the precautions on the back before filling in this (Page) · Line _ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -23- This paper size applies to the China National Solid Standard (CNS) A4 specification (210 x 297 public love)
TW088114492A 1998-09-17 1999-08-24 Capacitor with a high-ε-dielectric or a ferro-electricum according to fin-stack-principle and production method TW437070B (en)

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KR100442782B1 (en) * 2001-12-24 2004-08-04 동부전자 주식회사 a method for manufacturing of semiconductor device
US11916099B2 (en) 2021-06-08 2024-02-27 International Business Machines Corporation Multilayer dielectric for metal-insulator-metal capacitor

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KR0155785B1 (en) * 1994-12-15 1998-10-15 김광호 Fin capacitor & its fabrication method
KR0147640B1 (en) * 1995-05-30 1998-08-01 김광호 Capacitor of semiconductor device & its fabrication method
DE19527023C1 (en) * 1995-07-24 1997-02-27 Siemens Ag Method of manufacturing a capacitor in a semiconductor device
US5661064A (en) * 1995-11-13 1997-08-26 Micron Technology, Inc. Method of forming a capacitor having container members
DE19546999C1 (en) * 1995-12-15 1997-04-30 Siemens Ag Capacitor mfg system for semiconductor device
DE19707977C1 (en) * 1997-02-27 1998-06-10 Siemens Ag Capacitor production especially for DRAM cell array
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