436 9 9 4 a? ------B7 五、發明說明（1 ) iL關申請案之前後^ f靖先閱讀背面之注4事項再填寫本頁} 本發明主張1 999年1月1 3曰申請之美國臨時專利申請案 編號60/1 1 5,780之優先權。 發明範疇 本發明大禮上係有關一種積體電路，尤其有關一種積體 電路微影術。 發明背景 雙重金屬鑲嵌結構係半導體積體電路製造中所熟知。— 般雙重金屬鑲嵌結構包括兩積體電路層，其中各形成一渠 溝或一通路，之後充填導體。雙重金屬鑲嵌技術可用以產 生多層互連，其中位於該積體電路結構之兩層或多層中之 導體係藉由延伸於該層之間的通路互連。產生該種結構所 牽涉之問題係需準確地校準每一層，以使該通路可連接該 導體。此問題隨著圖型尺寸之縮小而惡化。 用以碌定校準之已知技術係包括界定通路優先及界定泪 溝優先方法。於界定通路優先方法中，經常於形成該渠$ 之後，於該通路姓刻期間使用具有高介電常數之蝕刻終止 層。不幸地’使用蝕刻終止層會增加導體間之寄生電容 經濟部智慧財產局員工消費合作社印製 而降低電路性能。於界定渠溝優先方法中，接點及通路係 於形成渠溝之後界定。此需該微影裝置具有高値焦點二 度。然而’目前光阻劑方法所伴隨之低値焦點深度難以， 到所需之通路尺寸及界定，和所謂之光阻劑除浩。而且' 此種高値焦點深度之需求随著圖型尺寸之縮小而更難以、 , ' 建 -4- 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） Γ' 436 994 Α7 經濟部智慧財產局員工消費合作社印製 Β7 五、發明說明（2 ) 此外，採用此等方法時’存在固有之校準問题。例如， 該通路於微影術期間未校準時，將使形成該通路之渠溝尺 寸產生局部偏差。而且，該通路與該渠溝校準不正將導致 該通路具有較小尺寸及異常形狀，諸如部分重整情沉下之 半月形。一種可能之解決方式是使該渠溝較該通路寬，以 補償該校準不正之公差。然而，此與該渠溝趨向較小圖型 尺寸之精神不符°另一種困難是期望該通路具有正方形剖 面，因爲此情況增加面積，因此降低層間之電阻。然而， 4試自具有正方形隙孔之光罩製造正方形通路時，通常在· 圖型尺寸縮小至約0‘5微米或更小時即無法施行。詳言 之，製造圓形通路；此種效果相信係由光阻劑表面張力效 應產生。與正方形通路比較下，此產生具有低於所需之剖 面積及較高之串聯電阻的通路。 發明概述 根據本發明’先前技藝之問題可藉著兩長型光罩開口之 互連以界定該通路或接點而獲得解決，每—開口皆位於個 別光罩中，使用至少一個該光罩開口以界定導體連接該通 路或接點之位置。此項研究實質正方形通路及該通路或接 點與該導體間之較佳校準的至少雙重優勢。 本發明説明具體實例係爲一種製造積體電路之方法，包 括提供一基材，其導電性材料上包含一介電層；於該介電 層上沉積一硬質光覃；於該硬質光罩上施加第—層光阻 劑；及感光界定一渠溝，蝕刻該硬質光罩，並部分蝕刻該 介電質，成具有—底部之一渠溝，制除該光阻劑，‘ “氏張尺ϋ用中國國家;票準(cns)aTS· (210 X 297 公* ) n I I I I ϋ n n n ϋ ϋ I n ^OJ1 n ϋ ϋ n I (請先閱讀背面之注意事項再填寫本頁〉 * ' 436^94 A7 B7 五、發明說明（3 ) 加第二層光阻劑，並感光界定一橫跨該渠溝之狄縫，自該 渠溝之底部向下選擇性地蚀刻該介電質直至底層導電性材 料’其中該硬質光罩及該第二層光阻劑兩者皆作爲光罩， 以形成通達該底層金屬之連接，而製造積體電路。是故， 本發明提出一種方法’以改善雙重金屬鑲嵌結構之處理， 另外提出經由使用單一取向自身校準接點及通路方法而避 免先前技藝高介電常數蝕刻終止層之使用的方法。而且， 根據本發明’提出一種積體電路’包括至少一連接，其中 該至少一連接係具有實質四邊形剖面，其中該四邊形係具 有約0 · 5_微米或更小之圖型尺寸。 圖式簡單説明 參照附圖而由以下詳述明瞭本發明。根據半導體工業之 一般經驗，強調圖中之各種圖型皆未按照比例。相反地， 各種圖型之尺寸係任意放大或縮小，以供説明。圖中包 括_· 圖1係爲本發明之一具體實例的介電質之透視圖，包括 兩導體’上層施加有一硬質光罩及第一層光阻劑； 圖2係爲前述具體實例之斷面透視圖，其中該第—層光 阻劑具有一開口，以於其中蚀刻一經感光界定之渠溝； 圖3係爲前述具體實例之透視圖，其中該硬質光罩已被 触刻穿透’而該介電其已被部分蝕穿而形成一渠溝； 圖4係爲前述具體實例之透視圖，其中該第一層光阻劑 已被移除： 圖5A係爲前述具體實例之透視圖，其中已施加第二層光 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） <請先閱讀背曲之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 I ! t·· I n I. · .^1 It n _u n n I— I n n n 1^1 n A7 436994 ______________________________________________ B7 — —. 五、發明說明（4 ) 阻劑； 係爲圖5 A之剖面； 念爲;^述具體實例之透視圖，其中該第二層光阻劑 具有橫跨其中經感光界定之渠溝的狹縫； 囷6 B係爲圖6 A之剖面； 圖6C係爲圖6A之平面圖； 圖7 A係爲前述具體實例之透視圖，其中該介電質係具有 自該渠溝底部蝕刻至該導體之正方形通路； 圖7 B係爲圖7 A之剖面； 圖7 C係爲圖7 A之剖面； 圖7D係爲圖7A之平面圖； 圖8 A係爲如述具體實例之透視圖，經金屬化及平面化之 後，已去除該第二層光阻劑及硬質光罩；且 圖8 B係爲圖8 A之剖面。 圖9 A係爲前述具體貫例之透視圖’經金屬化及平面化之 後，已去除該第二層光阻劑、該硬質光軍及某些該介電 質；且 圖9 B係爲圖9 A之剖面。 發明詳述 如前文所述，先前技藝之問題係藉著鑲嵌兩長形光罩開 口或狹缝而界足該通路或接點而解決’每個開口皆位於— 個別光罩中’使用至少一光罩開口以界定欲連接通路或接 點之導體的位置。若各光罩中之狹縫係爲長方形，則各光 罩中之狹縫係彼此垂直交叉，即下層光罩具有於光罩平面 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----I I ----— 1··-— — —---fj11· I I I I I I I I --J (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7436 9 9 4 a? ------ B7 V. Description of the invention (1) Before and after the iL application ^ f Jing first read the note 4 on the back before filling in this page} The present invention claims January 1, 999 The priority of U.S. Provisional Patent Application No. 60/1 1 5,780 filed on March 3. Scope of the invention The present invention relates to an integrated circuit, and more particularly to an integrated circuit lithography. BACKGROUND OF THE INVENTION Double metal damascene structures are well known in the manufacture of semiconductor integrated circuits. — The general double metal mosaic structure includes two integrated circuit layers, each of which forms a trench or a via, and is then filled with a conductor. Double metal damascene technology can be used to produce multilayer interconnections, in which the conductor system located in two or more layers of the integrated circuit structure is interconnected by vias extending between the layers. The problem involved in creating such a structure is that each layer needs to be accurately calibrated so that the pathway can connect to the conductor. This problem is exacerbated as the pattern size shrinks. Known techniques for performing calibration include the definition of pathway-first and tear-slot-first methods. In the method of defining a via priority, an etch stop layer having a high dielectric constant is often used during the engraving of the via after the formation of the trench. Unfortunately, the use of an etch stop layer increases the parasitic capacitance between the conductors. It is printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and reduces circuit performance. In the method of defining trenches first, the contacts and pathways are defined after the trenches are formed. This requires the lithographic apparatus to have a high degree of focus focus. However, the current low photoresist method is accompanied by a low focal depth, which is difficult to reach the required path size and definition, and the so-called photoresist. And 'the need for such a high depth of focus becomes more difficult as the size of the pattern decreases,' Jian-4- This paper size applies the Chinese national standard < CNS) A4 specification (210 X 297 mm) Γ '436 994 Α7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives B7 V. Description of Invention (2) In addition, when using these methods, there is an inherent calibration problem. For example, when the pathway is not calibrated during lithography, it will cause local deviations in the dimensions of the trenches that form the pathway. Moreover, improper alignment of the pathway with the trench will result in the pathway having a smaller size and anomalous shapes, such as a partially-reshaped half-moon shape. One possible solution is to make the trench wider than the channel to compensate for the misalignment tolerances. However, this is inconsistent with the spirit of the trench tending to a smaller pattern size. Another difficulty is that the via is expected to have a square cross-section, because this situation increases the area and therefore reduces the resistance between layers. However, in the case of making a square passage from a photomask with a square slot, the 4th test is usually unavailable when the pattern size is reduced to about 0'5 microns or less. In detail, circular paths are made; this effect is believed to result from the photoresist surface tension effect. Compared to a square via, this results in a via with a lower cross-sectional area and a higher series resistance. SUMMARY OF THE INVENTION The problem of the prior art according to the present invention can be solved by interconnecting two long photomask openings to define the path or contact, each opening is located in a separate photomask, using at least one photomask opening To define where the conductor connects to the path or contact. This study has at least the dual advantages of a substantially square path and a better alignment between the path or contact and the conductor. A specific example of the present invention is a method for manufacturing an integrated circuit, which includes providing a substrate including a dielectric layer on a conductive material; depositing a hard light layer on the dielectric layer; and depositing on the hard mask. Applying a first layer of photoresist; and photo-sensitively defining a trench, etching the hard mask, and partially etching the dielectric to have a trench at the bottom to remove the photoresist, ϋUse Chinese country; ticket (cns) aTS · (210 X 297 public *) n IIII ϋ nnn ϋ ϋ I n ^ OJ1 n ϋ ϋ n I (Please read the precautions on the back before filling in this page> * '436 ^ 94 A7 B7 V. Description of the invention (3) Add a second layer of photoresist, and define a photodiode across the trench, and selectively etch the dielectric down to the bottom from the bottom of the trench Conductive material 'wherein the hard mask and the second layer of photoresist are both used as a mask to form a connection to the underlying metal to manufacture an integrated circuit. Therefore, the present invention proposes a method' to improve The processing of the dual metal mosaic structure is also proposed by using a single orientation A method of quasi-contact and via method to avoid the use of the prior art high-dielectric constant etch stop layer. Moreover, according to the present invention, 'proposing a integrated circuit' includes at least one connection, wherein the at least one connection has a substantially quadrangular cross section, The quadrilateral system has a pattern size of about 0.5 μm or less. The drawings are briefly explained with reference to the drawings and the present invention will be described in detail below. According to the general experience of the semiconductor industry, the various patterns in the drawings are emphasized. Not to scale. On the contrary, the dimensions of various patterns are arbitrarily enlarged or reduced for explanation. Included in the figure. Figure 1 is a perspective view of the dielectric of a specific example of the present invention, including two conductors' upper layer A hard photomask and a first layer of photoresist are applied; FIG. 2 is a sectional perspective view of the foregoing specific example, wherein the first layer of photoresist has an opening to etch a photosensitive-defined trench therein; 3 is a perspective view of the foregoing specific example, in which the hard mask has been penetrated by touching and the dielectric has been partially etched to form a trench; FIG. 4 is the foregoing specific example Example of the perspective view, in which the first layer of photoresist has been removed: Figure 5A is a perspective view of the foregoing specific example, in which the second layer of light has been applied-6- This paper size applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) < Please read the precautions for the back song before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs I! T ·· I n I. ·. ^ 1 It n _u nn I— I nnn 1 ^ 1 n A7 436994 ______________________________________________ B7 — —. V. Description of the Invention (4) Resistor; It is a cross-section of Figure 5 A; It reads; ^ A perspective view of a specific example, in which the second layer of light The resist has a slit across the photosensitive-defined trench therein; 囷 6 B is a cross-section of FIG. 6A; FIG. 6C is a plan view of FIG. 6A; and FIG. 7A is a perspective view of the foregoing specific example, where the The dielectric has a square via etched from the bottom of the trench to the conductor; Figure 7B is a cross-section of Figure 7A; Figure 7C is a cross-section of Figure 7A; Figure 7D is a plan view of Figure 7A; 8 A is a perspective view of a specific example, after metallization and planarization, Remove the second layer of photoresist and hard mask; and Figure 8B is a cross section of Figure 8A. FIG. 9A is a perspective view of the foregoing specific embodiment. After metallization and planarization, the second layer of photoresist, the hard optical army, and some of the dielectric have been removed; and FIG. 9B is FIG. 9 Section A. Detailed description of the invention As mentioned above, the problem of the prior art is solved by inlaying two long photomask openings or slits to define the path or contact. 'Each opening is located-in an individual photomask' uses at least one The mask opening defines the location of the conductor to be connected to the via or contact. If the slits in each mask are rectangular, the slits in each mask are perpendicular to each other, that is, the lower mask has the plane of the mask. (Mm) ----- II ----— 1 ·· -— — —--- fj11 · IIIIIIII --J (Please read the precautions on the back before filling out this page) Staff Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Cooperative printed A7
4369 94 五、發明說明（5 ) 之X取向延伸之狹缝’而上層光罩具有於γ取向延伸之狹 缝’而該交叉係界定一位於X!，γ1位置之正方形。而且， 若下層光罩被固定，上層光罩於γ取向上自由地來回滑. 動’則Y取向上之狹缝可儘可能滑至最遠，並長至該γ狹 縫之至少一部分與X狹缝交叉，由該交點界定之正方形保 持於X〗’ Y,。因此’結合之光罩於該Y取向上半自動地校 準，位於此取向上之光罩較不重要。 現在參照附圖’其中相同編號於全文中表示相同元件， 圖1係爲本發明例示具體實例的介電1諸如二氧化矽之透視 圖，具有兩導體3及5，由導電性材料諸如銅製造，上層施 加有一硬質光罩7諸如氮化矽及第一層光阻劑。該第一層 光阻劑其次具有第一個長形開口或狹縫I 1，用以蚀刻其中 經感光界定之渠道，如圖2所示。氮化矽介電質被蝕穿， 而該二氧化矽介電其被部分蝕刻，“部分”意指未完全蝕除 至向下通達導電性材料3及5，加深該第一個長形開口 i j 以形成渠溝1 3，如圖3所示。去除該第一層光阻劑9，如 圖4所示，施加第二層光阻劑1 5，如圖5 A及5 B所示。該 第二層光阻劑經製作佈線圖型以形成第二組橫跨該渠溝i 3 之長形開口 17及19，如圖6A、6B及6C所示。由該平面 圖得知，圖6 C顯示二氧化矽曝露於蝕刻之正方形剖面。 對於二氧化矽介電其1具有選擇性但對氮化矽硬質光罩7或 光阻劑1 5不具有選擇性之蝕刻形成自該渠溝1 3底部至導 體3及5之頂部的正方形第三個開口 1 8及2 0，如圖7 A、 7 B、7 C及7 D所示。圖8 A及8 B係顯示金屬化之後的結 *8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) — ———— — — 1!111111 I . 經濟部智慧財產局員Η消費合作社印製 A7 卜 436994 五、發明說明（6 ) 構’充填該第三個開口18及2()，之後進行平面化以去除 孩第二層光阻劑、硬質光罩及過量金屬，產生所需之正方 形連接諸如通路或接點21及22。通路於層間提供連接， 而接點可爲結合塾，或使一結合塾终止，以結合線路等。 導禮3及5可由與通路成接π t 只、峪或接點2 1及2 2相同或不同導電性材 料製造。 本發明藉著單取向自動校準而改善界定小型接點及通路 圖型之微影能力。已發現前述方法避免與習用雙重金屬镶 焱方法相同地使用高介電常數中間層作爲蝕刻終止層諸如 氮化矽。 本發明方法包括使用硬質光罩及光阻劑，以於製造氧化 物渠溝之後使用雙重金屬鑲嵌方法界定接點及通路。渠溝 蚀刻之後，與傳統上界定圓孔形接點或通路之方法不同 地’根據接點或通路設計寬度而於該介電渠溝橫向印製— 狹縫。接點或通路之另一尺寸係由該渠溝之寬度界定。因 爲該狹縫寬度與該渠溝寬度可於狹缝長度之任何一處發 生’故本發明方法係於該狹縫尺寸中自動校準。解決因爲 一光罩沿其長形開口取向滑動而於至少一取向上產生之校 準問題，但由其與另一光罩中之長形開口之交點界定的開 口保持於相同位置。之後，使用高選擇性（相對於硬質光 罩及光阻劑）各向異性介電質蚀刻方法以向下界定通達先 前導電性材料層之接點或通路<5該狹縫以橫越並垂直於該 渠溝爲佳，但可爲任何角度，先決條件爲該狭缝非平行於 該渠溝。由該渠溝與該狹縫之交點所界定之通路的剖面形 -9- 表纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） C靖先閱讀背面之注意事項再填寫本頁) 訂· --------線. 經濟部智慧財產局員工消費合作社印製 436994 五、發明說明（ Α7 Β7 經 濟 部 智 .¾ 財 產 局 員 工 消 費 合 作 社 印 Μ 係爲四邊形。若該狹缝與渠溝等寬，則該形 直寬’則爲矩形，若該狹縫不與該渠溝垂 ^則係爲平行四邊形或偏菱形。如此， 圓之剖面比較之下，係铖最大化^ " 糸'，工最大化本發明四邊形通路及接 〇=形尺寸係爲0‘5微米及更小；以。·25較佳，而〇18至 ，及〇’14特佳，亦可使用0.12微米及更小之尺寸。 選佳擇硬質光罩作爲選擇性㈣（在沉Μ二層光阻劑之 仃）疋蚀刻終止|，因爲該独刻對於介電質具有選擇 :’而非該硬質光罩。例如’若介電質係爲二氧切或微 孔性玻璃’則該硬質光罩可爲例如氮切層，對於攻擊二 氣切之Μ錢刻劑如含有CH2F2、c4F8H2㈣之電衆 =有相當高之阻.抗。二氧化珍依序可作爲低_k聚合物諸如 ^基環丁燒及經氟化聚合物（氧電漿㈣劑）所使用之硬 質光罩，使得該二氧化矽保持實質未被接觸而蝕刻聚合 物。相反地，於該第一層光阻劑之後所進行之鞋刻不需: 有選擇性，唯該蝕刻劑對硬質光罩及二氧化矽依序具有選 擇，。蝕刻劑諸如熱磷酸MHF同時蝕刻該氮化矽^底層 二氧化矽。已知氮化矽具有約7 8之介電常數（幻，二氧/匕 矽相對地約4，而該低_k藥合物材料具有約2 7之介電常 數，毫微玻璃具有約2或更低之}^値。經氟化之矽酸鹽玻璃 有時係使用於低-k應用，而具有約3 5之k値。 已知因爲本發明通常且較佳去除該硬質罩，但非必要， 故該硬質光罩可包括非一般使用於先前技藝之材料，諸如 導電性材料。可使用之硬質光罩包括氮氧化矽、鈉鈣玻 (請先閱讀背面之注意事項再填寫本頁) 訂----- 線！ ί----------------- _________-10- 本紙張尺度適財關家標準（CNS)A4規格⑵〇 X 297公爱4369 94 V. Description of the invention (5) The X-direction extending slit 'and the upper mask has a γ-direction extending slit', and the intersection defines a square located at X !, γ1. Moreover, if the lower reticle is fixed, the upper reticle can slide freely back and forth in the γ orientation. The slit in the Y orientation can slide as far as possible and grow to at least a part of the γ slit and X The slits intersect, and the square defined by the intersection remains at X〗 'Y ,. Therefore, the 'bonded mask' is semi-automatically calibrated in this Y orientation, and the mask in this orientation is less important. Referring now to the accompanying drawings, wherein the same numbers represent the same elements throughout, FIG. 1 is a perspective view of a dielectric 1 such as silicon dioxide, illustrating a specific example of the present invention, having two conductors 3 and 5, made of a conductive material such as copper A hard mask 7 such as silicon nitride and a first layer of photoresist are applied on the upper layer. The first layer of photoresist secondly has a first elongated opening or slit I 1 for etching the photosensitive-defined channel therein, as shown in FIG. 2. The silicon nitride dielectric is eroded, and the silicon dioxide dielectric is partially etched. "Partial" means that it is not completely etched down to reach the conductive materials 3 and 5, deepening the first elongated opening. ij to form a trench 13 as shown in FIG. 3. The first layer of photoresist 9 is removed, as shown in Fig. 4, and a second layer of photoresist 15 is applied, as shown in Figs. 5A and 5B. The second layer of photoresist is patterned to form a second set of elongated openings 17 and 19 across the trench i 3, as shown in FIGS. 6A, 6B and 6C. From this plan view, Fig. 6C shows a square section of silicon dioxide exposed to the etching. For silicon dioxide dielectric, 1 is selective but not selective for silicon nitride hard mask 7 or photoresist 15. Etching is formed from the bottom of the trench 13 to the top of the conductors 3 and 5 Three openings 18 and 20 are shown in Figures 7 A, 7 B, 7 C and 7 D. Figure 8 A and 8 B show the results after metallization. * 8- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) — — ——— — — 1! 111111 I. Printed by A7, member of the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperative, 436436, V. Description of Invention (6) The structure 'fills the third openings 18 and 2 (), and then planarizes to remove A second layer of photoresist, hard mask, and excess metal creates the required square connections such as vias or contacts 21 and 22. A pathway provides a connection between layers, and a contact can be a bond, or a bond can be terminated to bond a line, etc. Guides 3 and 5 may be made of the same or different conductive materials as π t, 峪, or contacts 2 1 and 22 which are connected to the path. The present invention improves the lithography ability to define small contact and path patterns by automatic calibration of a single orientation. The foregoing method has been found to avoid the use of a high dielectric constant intermediate layer as an etch stop layer such as silicon nitride, as in the conventional double metal damascene method. The method of the present invention includes the use of a hard mask and a photoresist to define contacts and vias using a dual metal damascene method after the oxide trench is manufactured. After the trench is etched, it is different from the traditional method of defining circular hole-shaped contacts or vias, which are printed laterally on the dielectric trench—the slit according to the design width of the contact or via. Another dimension of a contact or via is defined by the width of the trench. Since the width of the slit and the width of the trench can occur anywhere in the length of the slit, the method of the present invention is automatically calibrated in the size of the slit. Solve the problem of alignment in at least one orientation caused by the sliding of one reticle along its elongated opening orientation, but the opening defined by the intersection of it with the elongated opening in the other reticle remains in the same position. Thereafter, a highly selective (as opposed to hard mask and photoresist) anisotropic dielectric etch method is used to define the contacts or pathways down to the previous layer of conductive material < 5 the slits cross across It is preferably perpendicular to the trench, but can be at any angle, a prerequisite is that the slit is not parallel to the trench. The cross-sectional shape of the path defined by the intersection of the trench and the slit. -9- The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). C Jing read the precautions on the back before filling This page) Order · -------- Line. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 436994 5. Description of the invention (Α7 Β7 Intellectual Property of the Ministry of Economic Affairs. The slit is the same width as the ditch, then the shape is straight, and the shape is rectangular. If the slit is not perpendicular to the ditch, it is a parallelogram or a rhombus. In this way, compared with a circular cross section, Maximizing ^ " 四 ', maximizing the quadrangular path and connection of the present invention = the size is 0'5 microns and smaller; 25 is preferred, and 〇18 to, and 〇14 are particularly good, Sizes of 0.12 microns and smaller can also be used. Select a hard mask as a selective ㈣ (on the second layer of photoresist in Shen M) 疋 Etch Termination |, because this etch has a choice of dielectrics: ' Instead of the hard mask. For example, 'if the dielectric is dioxane or microporous glass' The rigid photomask can be, for example, a nitrogen-cut layer, and has a very high resistance to attacking the two gas-cutting etchants such as those containing CH2F2, c4F8H2. Dioxin can be used as a low-k polymer in sequence. Rigid photomasks such as succinate and fluorinated polymers (oxygen plasma tinctures) keep the silicon dioxide substantially untouched and etch the polymer. Conversely, the first layer of light The shoe engraving after the resist is not required: selective, but the etchant has the choice of the hard mask and silicon dioxide in order. The etchant such as hot phosphoric acid MHF etches the silicon nitride at the same time ^ the bottom silicon dioxide It is known that silicon nitride has a dielectric constant of about 7 8 (relatively, the dioxygen / silicon is relatively about 4, and the low-k pharmacological material has a dielectric constant of about 2 7 and nanoglass has about 2 or lower} ^ 値. Fluorinated silicate glass is sometimes used in low-k applications and has a k 値 of about 35. It is known because the hard cover is generally and preferably removed by the present invention, However, it is not necessary, so the hard mask may include materials not commonly used in the prior art, such as conductive materials. The hard photomask used includes silicon oxynitride and soda-lime glass (please read the precautions on the back before filling this page) Order ----- Line! Ί --------------- -_________- 10- This paper is suitable for financial and family care standards (CNS) A4 specifications⑵〇X 297
經濟部智慧財產局員工消費合作杜印製 4 3 6 9 9 4 A7 ----- B7 五、發明說明（8 ) 璃、硼矽酸鹽玻璃、磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、多 晶矽、及鉬、鈕鈦鎢鈷鎳鈀鉑矽化物及氮化物、鉬、鎢、 鈦-鎢合金、氧化鋁、氮化鋁、二氧化鈦、氮化鈦及鉻。 之後，該硬質光罩可藉習用技術去除。光阻劑及硬質光 罩之去除可於平面化期間進行，而不需要一個別步驟。硬 質光罩之去除對於不需要低電容之積體電路而言係選擇性 步骤。然而，已發現該渠溝結構之底部通常不是蝕刻終止 層，而其存在有時係先前技藝雙重金屬鑲嵌形成技術之表 示〇 該導電性材料係包括金屬如鎢、銅、鋁及其合金及經摻 雜之多晶矽。該金屬化材料可與前述者相同或相異，而係 藉著習用技術諸如電解電鍍及無電電鍍、物理氣相沉積、 化學蒸汽沉積等技術沉積。 熟習此技藝者已知當該介電其係爲二氧化矽時，其通常 係爲生長或沉積於底層矽晶圓上之二氧化矽。 本發明優點包括： 改善之微影能力。就微影方法而言，曝露—狹縫之挑戰 性低於曝露一孔。微影法極限可藉著使用較薄之光阻劑而 進一步改善。 半自動校準以增加接點及通路面積。不同層間之金屬線 通常係設計成彼此交又。使用渠溝寬度以界定該接點或適 路之長度，以得到較大之中間層接點面積。如此一來，亦 可於極少或完全無損壞之情況下，於實質無校準不正公矣 下設計通路及後續金屬渠溝標準。 -11- 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） I 1 n n I, n I I I K I n HI n ί n n rj I t I t. f n n n [ i n n n n ϋ n I n n ·1 I I (請先閱讀背面之注意事項再填寫本頁) 436 y 9 4Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs on consumer cooperation Du 3 4 6 9 9 4 A7 ----- B7 V. Description of the invention (8) Glass, borosilicate glass, phosphosilicate glass, borophosphosilicate Glass, polycrystalline silicon, and molybdenum, button titanium tungsten cobalt nickel palladium platinum silicide and nitride, molybdenum, tungsten, titanium-tungsten alloy, aluminum oxide, aluminum nitride, titanium dioxide, titanium nitride, and chromium. The hard mask can then be removed using conventional techniques. Removal of the photoresist and the hard mask can be performed during the planarization without the need for a separate step. Removal of the hard mask is an optional step for integrated circuits that do not require low capacitance. However, it has been found that the bottom of the trench structure is usually not an etch stop layer, and its presence is sometimes a sign of the prior art double metal damascene formation technology. The conductive material includes metals such as tungsten, copper, aluminum and its alloys, and Doped polycrystalline silicon. The metallized material may be the same as or different from the foregoing, and is deposited by conventional techniques such as electrolytic plating and electroless plating, physical vapor deposition, and chemical vapor deposition. Those skilled in the art know that when the dielectric is silicon dioxide, it is usually silicon dioxide grown or deposited on the underlying silicon wafer. Advantages of the invention include: Improved lithography capabilities. For lithography methods, the exposure-slit is less challenging than exposing a hole. The lithography limit can be further improved by using a thinner photoresist. Semi-automatic calibration to increase contact and via area. The wires between different layers are usually designed to intersect with each other. Use the trench width to define the length of the contact or suitable path to get a larger area of the middle layer contact. In this way, the path and subsequent metal canal standards can also be designed with little or no damage and virtually no calibration irregularities. -11- This paper size is in accordance with China National Standard (CNS) A4 (210 x 297 mm) I 1 nn I, n IIIKI n HI n ί nn rj I t I t. Fnnn [innnn ϋ n I nn · 1 II (Please read the notes on the back before filling out this page) 436 y 9 4
五、發明說明（9 刻=…電場深度，因爲本發明薄層堆W 回復1容。本發明提供低電路電容，因爲不需要先 月’j技i i高介電常數蝕刻終止層。此:ΐ = ί本發明較佳及備擇特色及具體實例，故熟習 此技#者已知可更充分地明瞭本發明之詳 他特色將描述於下文，而形出太政n + t 尽發月工 广下又’ ^成本發日”請專利範圍之標 :。:。果，本發明所產生之改善之微影術、半自動校準及 降低乙回復電容形成申請專利範圍之基礎。熟習具有本發 明優點之技藝者已知可輕易地使用所揭示之觀念及特定具 體實例作爲基礎，設計或修飾進行相同之本發明目的之其 他結構。熟習此技藝者亦已知該同等結構不偏離本發明最 廣義之精神及範圍。 {請先閱讀背面之沒意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製V. Description of the invention (9 ticks = ... Electric field depth, because the thin layer stack W of the present invention recovers 1 capacitance. The present invention provides low circuit capacitance, because the high-dielectric constant etch stop layer is not required. This: ΐ = The preferred and alternative features and specific examples of the present invention, so those who are familiar with this technique # can know more fully the detailed features of the present invention will be described below, and form Taizheng n + t The following "^ Cost Issuance Date" invites the scope of patents: .... As a result, the improved lithography, semi-automatic calibration, and reduced B-recovery capacitance produced by the present invention form the basis of the scope of patent application. Familiarity with the advantages of the present invention It is known to the artist that he can easily use the disclosed concepts and specific specific examples as a basis to design or modify other structures for the same purpose of the invention. Those skilled in the art also know that the equivalent structure does not depart from the spirit of the invention in its broadest sense. And scope. {Please read the unintentional matter on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
-I V II — —---—II -12- 本紙張尺度過用中國國家標準（CNS)A4規格 (210 X 297公釐）-I V II — —---— II -12- This paper has been used in China National Standard (CNS) A4 (210 X 297 mm)