經濟部中央標準局員工消費合作社印裝 4 34 4 4 5 A7 __B7_五、發明説明（^ ) 〔發明所屬之技術領域〕 本發明，係關於矩陣型之液晶顯示裝置。 〔習知技藝〕 液晶顯示裝置，因薄型而輕量，且消耗電力低，故廣 被利用在各種顯示裝置。特別係，近年來已要求大畫面而 高精密者，技術開發也很積極。 有源矩陣型液晶顯示裝置，具有在顯示屏幕上配列成 矩陣狀之像素。圖5顯示各像素的等效電路。信號線1 5 和閘極線1 2係配置在正交方向，分別連接在薄膜電晶體 (TFT)18之汲極和閘極。各TFT，係形成在信號 線1 5和閘極線1 2的交叉點近傍* TFT1 8之源極和 基準電源V com，分別連接在液晶層的像素電極1 6和對 向電極3 4。液晶層，將做爲光調製器及電容C 1 c作 用。 因TFT 1 8，在其閘極和源極之間有無法避免的寄 生電容，故供給像素電極1 6之電位，會依供給閘極的脈 波之上升而變動。並且，已知在由TFT 1 8的斷開期間 之漏光的像素電位之保持期間*會引起電位變動》 爲了抑制此等的電位變動而獲得良好之畫質，在各像 素設有補助電容C S。 如圖6及圖7所示，液晶面板1 0 0有陣列基板1 〇 和對向電極3 0，在此等之間分別隔著配向膜2 3，2 4 保持扭曲線狀型液晶層4 0。面板1 0 0，係在其端部以 ；---------------1T------& - - (請先W讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X；Z97公釐） -4 - 經濟部智慧財產局貝工消费合作杜印製 A7 B7 五、發明說明（2 ) 密封劑（未圖示）密封。 偏光部37，分別配置在基板10 ’ 30的外側。在 陣列基板；I 0，有_例如，3 2 0 X 3條之信號線1 5 ’和 2 4 0條的閘掃描線1 2，設成互相正交。各像素電極 1 6，係做爲透明導電性膜由I T 0 (銦’氧化f )構成 。在各信號線15和閘極線12的交叉點近傍’設有倒交 錯型T F T 1 8。 閘極線1 2的一部份成爲TFT 1 8之閘電極1 2 a 。倒交錯型TF T 1 8，包含在閘電極上由氮化矽（ S 1 N X )而成的閘極絕緣層1 4，和在閘極絕緣層1 4 上之非晶形矽（a _ S i : Η )活性層3 3 ’及活性層 3 3上的通道保護（鈍化）層2 2。 從信號線15延伸的汲極15a ，通過η+型a — S i : Η有電阻之接觸層27，連接在a_S i : Η的活性 層3 3。源極17也通過η+型a — Si :Η有電阻之接 觸層27，連接在a — S i :Η的活性層33 °TFT 1 8，將做爲開關元件作用。 雖然，在上述係做爲TFT 1 8使用倒交錯型’但是 也可以使用交錯型TFT。同時，也可以代替a — S i : Η活性層3 3、而使用聚矽（P_S i )活性層或微晶膜 (micro-Crystal film )。 •補助電容配線1 3，係設成和閘極線1 2並行，而且 ，和像素電極16重疊。補助電容Cs ’係由像素電極 16和補助電容配線13形成。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）-5- 11! t -------^----1----^ 气請先W讀背面之注意事項#4.寫本頁> 經濟部智慧財產局員工消费合作社印製 -4 34 4 ^5 丨 疼王 A7 , ^ ; .七 ___B7_丨㈤..8. 五、發明說明C ) 對向電極3 0，具有玻璃基板3 8，RGB的濾色器 層3 6及配設在濾色器層之間的遮光層3 5。遮光層3 5 ，係爲了使入射光’不會到達TFT1 8，在陣列基板1 1 上的信號線1 5和像素電極1 6之間的間隙，及閘極線 12和像素電極16之間的間隙而設置。I TO之對向電 極3 4也ie置在濾色器層3 6上。 然後，在驅動本液晶顯示裝置時，係如圖8所示，例 如使用Η共用反轉驅動方法，表示分別爲像素電極，b爲 信號線1 5的共用電位（Vc om) ，C爲信號電極（ Vs i g) ，d爲閘極電位之各波形。 在此，供給補助電容配線1 3的驅動波形，係和共用 電位b之波形相同，爲每1寫入時間重複反轉的脈波波形 =同時，像素電極1 6因以信號線1 5和補助電容配線 1 3形成電容，故像素電位a也在保持期間•也隨著此等 信號線1 5和補助電容配線1 5的電位，一面與信號線 1 5之共用電位b保持某電位差，同樣地使電位反轉。 可是，完成如此的機能之補助電容配線1 3，通常將 以和閘極線1 2的材料相同之材料形成。如圖6所示，補 助電容配線1 3，係配置成和閘極線1 2平行的方向，以 橫斷像素電極1 6之中央部的狀態形成。在如此之構成， 補助電容配線1 3將設置和閘極線1 2同數’但是，通常 並不·對多數條的補助電容配線1 3，每1條供給電位，而 係把多數條總括起來給予相同之電位。因此’需要把多數 的補助電容配線1 3，在顯示領域外總括起來成批配線。 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐〉· 6 - 111·裝---寒！ —訂-----！_ -線 (#先閲讀背面之ii意Ϋ項再象寫本頁)Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 34 4 4 5 A7 __B7_ V. Description of the Invention (^) [Technical Field to which the Invention belongs] The present invention relates to a matrix-type liquid crystal display device. [Knowledge] Liquid crystal display devices are widely used in various display devices because they are thin and light, and consume low power. In particular, those who have demanded large screens and high precision in recent years have also actively developed their technology. An active matrix liquid crystal display device has pixels arranged in a matrix on a display screen. FIG. 5 shows an equivalent circuit of each pixel. The signal line 15 and the gate line 12 are arranged in orthogonal directions, and are connected to the drain and gate of the thin film transistor (TFT) 18, respectively. Each TFT is formed near the intersection of the signal line 15 and the gate line 12 * The source of the TFT 18 and the reference power source V com are connected to the pixel electrode 16 and the counter electrode 34 of the liquid crystal layer, respectively. The liquid crystal layer will function as a light modulator and a capacitor C 1 c. Since the TFT 18 has an unavoidable parasitic capacitance between its gate and source, the potential supplied to the pixel electrode 16 will change according to the rise of the pulse wave supplied to the gate. In addition, it is known that a potential variation occurs during the holding period of the pixel potential of the light leaked during the off period of the TFT 18. In order to suppress such potential variation and obtain good image quality, a storage capacitor CS is provided in each pixel. As shown in FIG. 6 and FIG. 7, the liquid crystal panel 100 has an array substrate 10 and a counter electrode 30, and the twisted linear liquid crystal layer 40 is held between the alignment films 2 3 and 2 4 respectively. . The panel 1 0 0 is at its end; --------------- 1T ------ &--(Please read the precautions on the back before filling in this Page) This paper size is in accordance with Chinese National Standard (CNS) A4 specification (21 × X; Z97 mm) -4-Printed A7 B7 by Shellman Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) Sealant ( (Not shown) sealed. The polarizing sections 37 are disposed outside the substrates 10 '30, respectively. In the array substrate; I 0, for example, there are 3 2 0 X 3 signal lines 1 5 ′ and 2 4 0 gate scanning lines 12, which are set to be orthogonal to each other. Each pixel electrode 16 is composed of I T 0 (indium 'oxide f) as a transparent conductive film. In the vicinity of the intersection of each of the signal lines 15 and the gate lines 12 'is provided an inverted crossover type T F T 1 8. A part of the gate line 12 becomes the gate electrode 12 a of the TFT 18. An inverted staggered TF T 1 8 includes a gate insulating layer 14 made of silicon nitride (S 1 NX) on a gate electrode, and an amorphous silicon (a _ S i) on the gate insulating layer 14. : Ii) the channel protection (passivation) layer 2 2 on the active layer 3 3 ′ and the active layer 33. The drain electrode 15a extending from the signal line 15 is connected to the active layer 33 of a_S i: Η through a contact layer 27 having a resistance of η + type a — S i: Η. The source electrode 17 is also connected to the active layer 33-TFT 18 of a-Si: Η through the η + -type a-Si: Η resistive contact layer 27, which will function as a switching element. Although an inverted staggered type is used as the TFT 18 in the above-mentioned system, an staggered type TFT may be used. At the same time, it is also possible to use a polysilicon (P_S i) active layer or micro-Crystal film instead of a — S i: Η active layer 3 3. • The auxiliary capacitor wiring 1 3 is provided in parallel with the gate line 12 and overlaps with the pixel electrode 16. The storage capacitor Cs' is formed by the pixel electrode 16 and the storage capacitor wiring 13. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -5- 11! T ------- ^ ---- 1 ---- ^ Please read the back of the paper first Note # 4. Write this page> Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-4 34 4 ^ 5 丨 King A7, ^; .7B7_ 丨 ㈤.8. V. Description of Invention C) The counter electrode 30 includes a glass substrate 38, an RGB color filter layer 36, and a light-shielding layer 35 disposed between the color filter layers. The light-shielding layer 3 5 is for preventing incident light from reaching the TFT 18, the gap between the signal line 15 and the pixel electrode 16 on the array substrate 1 1, and the gap between the gate line 12 and the pixel electrode 16 Clearance. The opposing electrode 34 of I TO is also placed on the color filter layer 36. Then, when the liquid crystal display device is driven, as shown in FIG. 8, for example, a 反转 common inversion driving method is used, which represents pixel electrodes, b is a common potential (Vc om) of the signal line 15, and C is a signal electrode. (Vs ig), d is each waveform of the gate potential. Here, the driving waveform supplied to the auxiliary capacitor wiring 13 is the same as the waveform of the common potential b. It is a pulse waveform that is repeatedly inverted every writing time = At the same time, the pixel electrode 16 is compensated by the signal line 15 and the auxiliary The capacitor wiring 13 forms a capacitor, so the pixel potential a is also maintained. Along with the potential of these signal lines 15 and the auxiliary capacitor wiring 15, a potential difference is maintained on the common potential b of the signal line 15 and the same. Invert the potential. However, the auxiliary capacitor wiring 13 for performing such a function is usually formed of the same material as that of the gate wire 12. As shown in FIG. 6, the auxiliary capacitor wiring 13 is arranged in a direction parallel to the gate line 12 and is formed so as to cross the central portion of the pixel electrode 16. In such a configuration, the auxiliary capacitor wiring 13 is provided with the same number as the gate line 12. However, usually, the auxiliary capacitor wiring 13 is not supplied with a potential for each of the plurality of auxiliary capacitor wirings 13, and the plurality of auxiliary capacitor wirings are collectively included. Give the same potential. Therefore, a large number of auxiliary capacitor wirings 13 need to be collectively wired outside the display area. This paper size applies the Chinese national standard (CNS > A4 size (210 X 297 mm) · 6-111 · installed --- cold! — Order -----! _-Line (#read the meaning of the ii on the back side first) (Items like writing this page)
經濟部智慧財產局員工消費合作社印製 五、發明說明（4 ) 可是，對此等各補助電容配線1 3，因在相同方向配 置有閘極體12，且對各補助電容配線1 3，每隔1條通 過，故須以和此等_各閘極線1 2絕緣之狀態成批配線。 因此，如圖5，圖9所示，在做爲液晶顯示裝置的從 顯示領域離開之部份，在和各閘極線1 2與補助電容配線 1 3絕緣的閘極絕緣膜1 4之表面側，向與信號線1 5相 同方向以相同材料形成成批配線1 9。然後，與各補助電 容配線1 3之間，係經由分別設在對應於閘極絕緣膜1 4 的各補助電容配線13之一端側的位置之貫通表裏的接觸 孔20而連接。結果，各補助電容配線13之一端側，將 會由成批配線19總括起來成批連接。 如此地，把補助電容配線1 3和成批配線1 9經由接 觸孔2 0電性地連接時，如圖9的X — X截面圖之圖1 0 所示，形成成批配線1 9而和信號線1 5相同材料的導電 膜1會在和接觸孔2 0的上部角部之間，容易引起如圖所 示地此間的厚度變成極薄之，所謂段切現象。 發生段切時，該處的電阻會變高，從成批配線1 9供 給之補助電容配線1 3的電極電位脈波將會鈍化》如此地 脈波鈍化時將會影響像素電位，而發生橫串音不良。 〔發明所要解決之課題〕 如此地，把補助電容配線1 3和成批配線1 9通過接 觸孔_2 0連接時，具有由於接觸孔2 0的上部角部會在成 批配線1 9發生段切，由成批配線1 9供給的補助電容配 線1 3之電極電位脈波會鈍化、影響像素電位、而發生橫 本紙張尺度適用中國國家標準（CNSXA4規格（210 X 297公釐）-7- I I I I -------I I * — — — — I I--— I— (請先聞讀背面之ii意事項再瑀寫本頁) V 434445 經濟部中央標準局負工消費合作社印製 A7 B7___ 五、發明説明（$ ) 串音不良之問題。 本發明，係鑑於上述問題點而開發者，其目的在提供 無段切所引起之橫串音不良的，能夠良好地顯示的有源矩 陣型之液晶顯示裝置》 〔爲了解決課題之裝置〕 本發明，係具備有多數條的閘極線，和對此等閘極線 交叉之多數條信號線，和介在此前述閘極線及信號線間的 閘極絕緣膜，和形成在此等閘極線及信號線之交點的薄膜 電晶體，在此該薄膜電晶雔控制之前述閘極絕緣膜的一面 側配設成矩陣狀之像素電極，和形成在前述閘極絕緣膜的 他面側，以橫斷前述各像素電極之略中央部的位置關係分 別設置之多數的補助電容配線，分別設在和前述補助電容 配線之各一端側對向部份的多數個接觸孔，以及，在前述 閘極絕緣膜之設置接觸孔部份，向和前述各補助電容配線 交叉的方向形成，具有分別通過多數個接觸孔和前述各補 助電容配線之一端側連接的成批配線之陣列基板，和具有 對向電極而對向於該陣列基板的對向基板，和挾持在前述 陣列基板及對向基板間之液晶者，由於把接觸孔做爲多 數，越過段差的領域將會增加，不斷切而接觸之段差部的 地方將會增加，故能抑制補助電容配線之電阻上升。結 果，因能抑制供給補助電容電極的電位脈波之鈍化I，故能 獲得無橫串音不良之良好畫質》 同時，接觸孔，係沿補助電容配線的長方向配置者， (請先-閲讀背面之注意Ϋ項再填寫本頁) 本紙張尺度適用中國國家接準（CNS ) Α4規格（210X297公釐） _ g - 434445 鋰濟部中央揉準局貝工消費合作社印製 A7 B7_五、發明説明（6 ) 成批配線在接觸孔之段差部位外的領域將會增加，能夠抑 制成批配線本身之電阻上升，抑制供給補助電容電極的電 位脈波之鈍化*而使畫質變爲良好。 更且，接觸孔，係形成向形成成批配線的面成爲大徑 的遞變狀，能夠確實防止由接觸孔之成批配線的，不 會有段|引起之橫串音不良，而將成爲良好之顯示。 〔發明之實施形態〕 以下，參照圖1及圖2說明本發明的液晶顯示裝置之 —實施例。 本實施例的液晶顯示裝置之像素部的構成，係和圖5 至圖7所示者相同，做爲液晶顯示裝置全雔，將在玻璃基 板1 1上形成具有閘極1 2 a的例如鉬（Mo )之閘極線 1 2，同時和該閘極線1 2略平行地，同時地形成例如鉬 (Mo )的補助電容配線1 3，如被覆此等閘極線1 2及 補助電容配線1 3地，在玻璃基板11上形成有氮化矽之 閘極絕緣膜1 4。同時，在該閘極絕緣膜1 4的表面，在 和閘極線1 2正交方向形成有鋁（A I )之信號線1 5， 而在該信號線1 5有汲極1 5 a突出形成》 同時，在閘極絕緣膜1 4上形成有I TO像素電極 16，在該像素電極16及閘極12a上形成源極17。 在閘極1 2 a上，有隔著閘極絕緣膜1 4形成的半.導體餍 之a — S i : Η活性層33，分別經由有電阻的接觸層2 7連接在源極1 7及汲極1 5 a，以此等形成倒交錯型之 ----------^------ix------A - - (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS } A4说格（210X297公釐） -9- 4 34 4 4 5 經濟部中央樣準局貝工消费合作社印家 A7 B7五、發明説明（？） 薄膜電晶體1 8 ’該薄膜電晶體1 8係在閘極線1 2及信 號線1 5的交點。再者’補助電容配線1 3 ’係位於橫斷 像素電極1 6之略中央部的位置。然後’以此等形成陣列 基板。 再者，圖1顯示此等各補助電容配線1 3的在做爲液 晶顯示裝置之顯示領域以外的鋁之成批配線19的部份’ 該成批配線將把每多數個補助電容配線總括連接而引出。 此等成批配線1 9和各補助電容配線1 3的一端側，在隔 著閘極絕緣膜1 4對向之部份，以和此等各補助電容配線 1 3正交的的方向形成。同時，在對應閘極絕緣膜1 4之 各補助電容配線1 3的一端側’和成批配線1 9之交叉部 的部份，設有多數個貫通該閘極絕緣膜1 4之表裡的接觸 孔2 1。因此，成批配線1 9、係各補助電容配線1 3之 一端側，通過向形成成批配線1 9的面成爲大徑之遞變狀 的多數個接觸孔21電性連接。同時，在此等之表面，依 次叠層形成有氮化矽的鈍化膜2 2及聚亞胺之配向膜 2 3。 更且，使具有對向電極的對向基板對向該陣列基板， 把液晶挾在陣列基板和對向基板之間構成液晶顯示裝置》 以下，參照圇2，圖6及圖7，說明本發明的一實施 例之液晶顯示裝置的製造方法。 首先，在玻璃基板1 1上以噴鍍法形成3，0 0 0A (埃）厚度的鉬（Mo )膜，由感光蝕刻法形成所定形狀 之閘電極1 2 a，閘極線1 2及補助電容配線1 3 »然 本紙張尺度適用中國國家樣丰（CNS )八4規格（210X297公羞） .10. i. n 裝*~ I n ^ I H *Λ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央梯準局員工消费合作社印裂 u 4 3 η - - ^ A7 _B7_ _ 五、發明说明（？） 後，以CVD法，在玻璃基板1 1全面，把4，000A 厚度的氮化矽（S i Nx)之閘極絕緣膜1 4，和將成爲 薄膜電晶體18的通道領域33之1，OOOA厚度的i 型a_S i膜之半導體者，和將成爲通道保護膜22的 2，0 0 0A厚度之氮化矽依次叠層成膜。S iNx保護 膜，以感光蝕刻法形成通道的蝕刻保護膜2 2之圖型*並 且，由CVD法，形成將成爲有電阻的接觸層之1，00 0A厚度的n+型a — Si :H膜，把n+型a-Si ， i型a_S i膜形成所定形狀之圖型。然後，由噴鍍法形 成I T ◦所成的透明導電膜，形成像索電極1 6之圔形》 其後，在全面塗佈感光抗蝕刻，爲了在閘極絕緣膜 14形成連接以後形成的成批配線和補助電容線之接觸 孔，把抗蝕刻膜形成圖型，以包含NH4F(30%)和 HF ( 6%)的混合液之蝕刻液將閘極絕緣膜1 4蝕刻， 打開貫通孔在閘極絕緣膜1 4形成接觸孔2 1。基本上此 係等方濕式蝕刻、故接觸孔將以遞變狀的內壁形成在閘極 絕緣膜1 4。各接觸孔2 1的成批配線1 9側之開□，係 比補助電容配線1 3側的開口大。接觸孔之個數，係例如 爲3個，將設在成批配線1 9和各補助電容配線1 3的交 叉點。然後，以噴鍍法形成鋁膜，由感光蝕刻形成信號線 15,源極15a，汲極17及成批配線19。 更且，由CVD法在全面形成2，0 0 0A厚度的 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） _ ” _ ---------^------ir------在 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作杜印製 4 34 4 4 5 A7 _B7_____ 五、發明説明㈠） S i NX之鈍化膜2 8，使對應像素電極1 6的部份會去 除地形成圖型（參照圖2) »在其上塗佈聚亞胺配向膜 2 3° 在此爲了改善閘極絕緣膜1 4的膜質，常使用例如 S i Nx和S i 0之2層膜。在如此的元件，也能容易地 製作接觸孔eWCVD法形成2 . 000A的S iNx和 2，000入之S iO膜，而以包含NH14F (30%) 和HF (6%)的混合液之蝕刻液製作接觸孔。於是，因 S iNx膜的蝕刻率比S iO膜慢，故在閘極絕緣膜14 會形成如圖2所示之接觸孔。 此時，在上述實施形態，因把各補助電容配線1 3的 一端側，和成批配線1 9電性連接之接觸孔21，分別在 每各補助電容配線13之一端側與成批配線19的各交叉 部設置多數個，故將增加在成批配線1 9在接觸孔2 1之 部份越過段差的導電膜部份。因此，將會增加不段切而接 觸的段差部之數，故能抑制補助電容配線1 3的電阻上 升。亦即，將會抑制供給補助電容配線1 3的竃位脈波之 鈍化，結果，能夠獲得無串音不良的良好之畫質。 同時，因將多數的接觸孔2 1，沿補助電容配線1 3 之長方向配置，故成批配線1 9的在接觸孔2 1之段差部 以外的領域會增加，能夠抑制成批配線1 9本身之電阻上 升，由此點也能抑制供給補助電容電極的電位脈波之鈍 本紙張尺度逋用中國國家揉率（CNS ) A4规格（210X297公釐） -12- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局貝工消費合作社印製 Α7 Β7_ 五、發明説明（/〇 ) 化，而能獲得良好的畫質。同時’在成批配線1 9，將會 流通圖1的直方向之電流，如圖所示地要設置3個接觸孔 2 1時，由把此等沿補助電容配線之長方向配置，因能包 含各接觸孔2 1間，把直向之電流通路確保多數而理想。 同時，因將各接觸孔2 1如圖2所示，形成向形成成 批配線1 9的面成爲大徑之遞變狀，故能確實防止由接觸 孔2 1的成批配線1 9之段切，而獲得無段切所引起的橫 串音不良之值異的顯示》 並且，雖然在實施形態，係做爲接觸孔2 1顯示四方 形者，但是並不限於此形狀，可以爲圖形或多角形等之任 何形狀。 同時，做爲多數個的接觸孔3 1之配匿方向，雖然顯 示沿補助電容配線1 3的長方向配置之情況，但是，也可 以如圖3所示，把該補助電容配線13的長方向做爲列數 m (圚示m=3)，把與此正交之方向做爲段數η (圖示 η=2)，把此在圖1所示的接觸孔21小面稹之接觸 孔，配置m X η個。 更且，接觸孔21的配置方向，並非只限定於補助電 容配線1 3之長方向，也可以如圖4所示，把形成横長的 多數個接觸孔3 2，以長方向會沿補助電容配線1-3之長 方向的狀態，向上下方向配置多數段。如此地形成時，能 將此形成1個接觸孔時加長接觸孔的外周之長度’而能減 (請先閲讀背面之注意事項再填寫本頁) 訂 本纸張尺度適用中國_家樣率（CNS > Α4规格（210X297公釐) -13- 經濟部智慧財產局員工消費合作社印製 1 ^ 34 a 4 5 A7 匕 a. 17.和4 __ _B7_^ 五、發明說明（11 ) 低成批配線和補助電容配線之連接電阻。 〔發明之效果〕 根據本發明時，由於使接觸孔成爲多數，越過段差的 領域會增加*不會形成段切而接觸的段差部之處會增加， 故能抑制補助電容配線的電阻上升，抑制供給補助電容電 極之電位脈波的鈍化，而獲得無橫串音不良之優異畫質。 同時，成批配線在接觸孔的段差部位外之領域會增加 ，能夠抑制成批配線本身的電阻上升，抑制供給補助電容 電極之電位脈波的鈍化，而能使畫質變成良好。 並且，能夠確實防止由接觸孔的成批配線之段切，消 除因段切而引起的橫串音，而能良好地顯示。 圖面之簡單說明 〔圖1〕 爲顯示本發明的液晶顯示裝置之一實施形態的成批配 線和補助電容配線之連接部份的平面圖。 〔圖2〕 爲同上圖1之I I 一 I I線截面圖。 〔圖3〕 本紙張尺度遶用中國國家標準<CNS)A4規格（210x 297公釐）-14- — II---------•裝----- II 訂----- (請先閱讀背面之注意事項再4寫本頁) 4 34445 經濟部中央標準局員工消费合作社印裝 A7 B7 五、發明説明（，2 ) 爲同上的顯示其他實施形態之成批配線和補助電容配 線的連接部份之平面圖。 〔圖4〕 爲同上的顯示其他賁施形態之成批配線和補助電容配 線的連拉部份之平面圖》 〔圖5〕 爲關於液晶顯示裝置的像素之電性等效電路圖。 〔圖6〕 爲液晶顯示裝置的陣列基板之平面圖。 〔圖7〕 爲同上圖之VI I— VI I線截面圖。 〔圖8〕 爲顯示同上使用在有源矩陣型的液晶顯示裝置之Η共 用反轉驅動方式的各波形之波形圚。 〔圖9〕 爲顯示習知的成束配線和補助電容配線的連接部份之 平面圖。 〔圖 1 0〕 ---------装------,π------^ (請先閲讀背面之注意Ϋ項再填寫本頁) 本紙張尺度適用中國國家標率（CNS ) Α4規格（210X297公釐） · 15 _ 4 344 4 5 A7 B7 五、發明説明（θ ) 爲同上圖9的I X_ I X線截面圖 經濟部中央標準局員工消費合作社印製 〔記號之說明〕 1 0陣列基板 1 1玻璃基板 1 2閘極線 1 2 a閘電極 1 3補助電容配線 1 4閘極絕緣膜 1 5信號線 1 5 a汲極 1 6像素電極 1 7源極 1 8薄膜電晶體 1 9成批配線 2 3 2接觸孔 (請先閲讀背面之注意事項再填寫本頁) 2 2鈍化層 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） _伯-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (4) However, for these auxiliary capacitor wirings, 1 3, the gate body 12 is arranged in the same direction, and each auxiliary capacitor wiring is 13, each Pass every other line, so it must be wired in batches in a state insulated from these 12 gate lines. Therefore, as shown in FIG. 5 and FIG. 9, the part of the liquid crystal display device that is separated from the display area is on the surface of the gate insulating film 14 that is insulated from each gate line 12 and the auxiliary capacitor wiring 13. On the side, the bulk wiring 19 is formed in the same direction as the signal line 15 and made of the same material. The auxiliary capacitor wirings 13 are connected to each other through contact holes 20 provided on the front and rear surfaces of the auxiliary capacitor wirings 13 corresponding to one end of the gate insulating film 14 respectively. As a result, one end side of each of the auxiliary capacitor wirings 13 will be collectively connected in batches by the bulk wirings 19. In this way, when the auxiliary capacitor wiring 13 and the batch wiring 19 are electrically connected through the contact hole 20, as shown in FIG. 10 of the X-X cross-sectional view, the batch wiring 19 is formed and The conductive film 1 of the same material as the signal line 15 will be between the upper corners of the contact hole 20, which easily causes the thickness to become extremely thin as shown in the figure, a so-called segmentation phenomenon. When segmentation occurs, the resistance there will increase, and the electrode potential pulse wave of the auxiliary capacitor wiring 1 3 supplied from the batch wiring 19 will be passivated. When the pulse wave is passivated, the pixel potential will be affected, and a horizontal string will occur. Bad sound. [Problems to be Solved by the Invention] In this way, when the auxiliary capacitor wiring 13 and the batch wiring 19 are connected through the contact hole_2 0, the upper corners of the contact hole 20 are generated in the batch wiring 19. Cut, the electrode potential pulses of the auxiliary capacitor wiring 1 3 supplied by the batch of wiring 19 will passivate, affect the pixel potential, and occur horizontally. The paper size applies the Chinese national standard (CNSXA4 specification (210 X 297 mm) -7- IIII ------- II * — — — — I I --— I— (Please read and read the meaning on the back of the page before writing this page) V 434445 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7___ V. Description of the Invention ($) The problem of poor crosstalk. The present invention was developed in view of the above problems, and its purpose is to provide an active source that can display poor horizontal crosstalk caused by stepless cuts. [Matrix type liquid crystal display device] [A device for solving a problem] The present invention includes a plurality of gate lines, a plurality of signal lines crossing the gate lines, and the gate lines and signals described above. Gate insulation film between lines, and formed on A thin film transistor at the intersection of the gate line and the signal line, where one side of the gate insulation film controlled by the thin film transistor is arranged in a matrix-like pixel electrode, and the other formed on the gate insulation film On the surface side, a plurality of auxiliary capacitor wirings respectively provided in a positional relationship that crosses the slightly central portion of each of the pixel electrodes are provided in a plurality of contact holes facing the one end side of the auxiliary capacitor wiring, and, An array substrate having a plurality of wirings connected to a plurality of contact holes and one end side of each of the auxiliary capacitor wirings is formed in a portion of the gate insulating film provided with a contact hole. As opposed to a counter substrate having a counter electrode facing the array substrate, and a liquid crystal held between the array substrate and the counter substrate, since the contact holes are used as the majority, the area beyond the step will increase and continue to be cut. In addition, there will be an increase in the number of contact points, so that the resistance of the auxiliary capacitor wiring can be suppressed from increasing. As a result, the electricity supplied to the auxiliary capacitor electrode can be suppressed. The passivation of the pulse wave I, so you can get good picture quality without poor crosstalk. At the same time, the contact holes are arranged along the long direction of the auxiliary capacitor wiring. (Please read the note on the back before filling this page) This paper size is applicable to China National Access Standard (CNS) A4 specification (210X297 mm) _ g-434445 Printed by the Central Government Bureau of the Ministry of Lithuania and printed by the Bayong Consumer Cooperative A7 B7_ 5. Description of the invention (6) Batch wiring is in contact The area outside the stepped portion of the hole will increase, which can suppress the increase in the resistance of the bulk wiring itself, and the passivation of the potential pulse supplied to the auxiliary capacitor electrode to improve the image quality. Moreover, the contact hole is formed to the direction The surface on which the batch wiring is formed becomes a large-diameter tapered shape, which can surely prevent the batch wiring from the contact hole, and there will be no horizontal crosstalk caused by the segment |, and it will become a good display. [Embodiment of the invention] Hereinafter, an embodiment of a liquid crystal display device of the present invention will be described with reference to Figs. 1 and 2. The structure of the pixel portion of the liquid crystal display device of this embodiment is the same as that shown in FIG. 5 to FIG. 7. As the whole of the liquid crystal display device, for example, molybdenum having a gate electrode 1 2 a will be formed on the glass substrate 11. The gate line 12 of (Mo) is formed at the same time as the gate line 12 in parallel, and at the same time, a supplementary capacitor wiring 1 3 such as molybdenum (Mo) is formed. On the ground, a silicon nitride gate insulating film 14 is formed on the glass substrate 11. At the same time, a signal line 15 of aluminum (AI) is formed on the surface of the gate insulating film 14 in a direction orthogonal to the gate line 12, and a drain 15a is formed on the signal line 15 》 At the same time, an I TO pixel electrode 16 is formed on the gate insulating film 14, and a source electrode 17 is formed on the pixel electrode 16 and the gate electrode 12 a. On the gate electrode 1 2 a, there is a half formed through the gate insulating film 14. The conductor 餍 a — S i: Η active layer 33 is connected to the source electrode 17 and the contact electrode 2 7 through the resistance layer 27 respectively. Drain 1 5 a to form an inverted staggered type ---------- ^ ------ ix ------ A--(Please read the precautions on the back before (Fill in this page) This paper size applies Chinese National Standard (CNS) A4 scale (210X297 mm) -9- 4 34 4 4 5 Central Samples Bureau, Ministry of Economic Affairs, Shellfish Consumer Cooperative, India A7, B7, 5. Description of invention (? ) Thin film transistor 1 8 'The thin film transistor 18 is at the intersection of the gate line 12 and the signal line 15. Furthermore, the' supply capacitor wiring 1 3 'is located at a slightly central portion across the pixel electrode 16. Position. Then, 'the array substrate is formed in this way. Moreover, FIG. 1 shows a part of the batch of wiring 19 of aluminum of each of the auxiliary capacitor wirings 13 outside the display area of the liquid crystal display device. The wiring will lead out the collective connection of each of the plurality of auxiliary capacitor wirings. One end of each of the batch wirings 19 and each of the auxiliary capacitor wirings 13 is opposed to the gate insulation film 14 It is formed in a direction orthogonal to these auxiliary capacitor wirings 13. At the same time, at the portion where one end of each of the auxiliary capacitor wirings 13 corresponding to the gate insulating film 14 is intersected with the bulk wiring 19 A plurality of contact holes 21 are provided through the front and back surfaces of the gate insulating film 14. Therefore, the bulk wiring 1 9 is one end of each auxiliary capacitor wiring 1 3, and the bulk wiring 1 9 is formed. The large-diameter surface is electrically connected to the plurality of contact holes 21 that are gradually changed in shape. At the same time, a passivation film 2 2 of silicon nitride and an alignment film 23 of polyimide are sequentially laminated on these surfaces. Furthermore, a counter substrate having a counter electrode is opposed to the array substrate, and a liquid crystal display device is formed between the array substrate and the counter substrate. The following describes the present invention with reference to FIG. 2, FIG. 6, and FIG. A method for manufacturing a liquid crystal display device according to an embodiment. First, a molybdenum (Mo) film having a thickness of 3,000 A (angstrom) is formed on a glass substrate 11 by a sputtering method, and a gate having a predetermined shape is formed by a photolithography method. Electrode 1 2 a, gate line 12 and auxiliary capacitor wiring 1 3 Use China National Samples (CNS) size 8 (210X297). 10. i. N equipment * ~ I n ^ IH * Λ (Please read the precautions on the back before filling this page) Central Ministry of Economic Affairs Employee Consumer Cooperative Coupling u 4 3 η--^ A7 _B7_ _ V. After the description of the invention (?), The CVD method is used on the glass substrate 1 1 and the thickness of 4,000 A silicon nitride (S i Nx) is reduced. The gate insulating film 14 and the semiconductor of the i-type a_S i film with a thickness of 1, OOOA which will become the channel area 33 of the thin film transistor 18, and the nitride of 2,0 0 0A which will become the channel protection film 22 Silicon is sequentially laminated to form a film. S iNx protective film, a pattern of etching protection film 22 for forming a channel by a photo-etching method *, and an n + type a—Si: H film having a thickness of 1,000 0 A to be a resistive contact layer is formed by a CVD method The n + -type a-Si and i-type a_S i films are formed into a predetermined shape. Then, IT was formed by thermal spraying to form a transparent conductive film, and a picture electrode 16 was formed. Thereafter, a photoresist and an anti-etching film were applied over the entire surface to form a connection formed after the gate insulating film 14 was connected. The contact holes of the batch wiring and the auxiliary capacitor line are used to pattern the anti-etching film. The gate insulating film is etched with an etching solution containing a mixed solution of NH4F (30%) and HF (6%), and the through-holes are opened. The gate insulating film 14 forms a contact hole 21. Basically, this is an isotropic wet etching, so the contact hole will be formed on the gate insulating film 14 with a tapered inner wall. The openings on the 9 side of the batch wiring 19 of each contact hole 21 are larger than the openings on the 3 side of the auxiliary capacitor wiring 13. The number of contact holes is, for example, three, and they will be provided at the intersections of the batch wiring 19 and the auxiliary capacitor wirings 13. Then, an aluminum film is formed by thermal spraying, and signal lines 15, source 15a, drain 17 and batch wiring 19 are formed by photo-etching. In addition, the CVD method is used to form a paper with a thickness of 2,000 A. It is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) _ ”_ --------- ^ --- --- ir ------ (Please read the notes on the back before filling out this page) Printed by the Department of Economics, Central Standards Bureau, Consumer Cooperation Du 34 4 4 4 5 A7 _B7_____ V. Description of Invention ㈠) S i NX passivation film 28, so that the part corresponding to the pixel electrode 16 will be removed to form a pattern (refer to Figure 2) »Polyimide alignment film 2 is coated on it 3 ° Here, in order to improve the gate insulation film 1 4 film quality, such as Si Nx and Si 0 two-layer film is often used. In such devices, the contact hole eWCVD method can be easily formed to form 2.000A SiNx and 2,000 Si Si film, The contact hole is made of an etching solution containing a mixture of NH14F (30%) and HF (6%). Therefore, since the etching rate of the SiNx film is slower than that of the SiO film, a gate insulating film 14 is formed as shown in FIG. At this time, in the above embodiment, because one end of each auxiliary capacitor wiring 13 is electrically connected to the contact holes 21 of the batch wiring 19, each of the auxiliary capacitor wirings is arranged separately. A plurality of cross sections of one end side of the wire 13 and the batch of wiring 19 are provided, so a portion of the conductive film that crosses the step in the portion of the batch of wiring 19 in the contact hole 21 will be increased. The number of stepped portions that are brought into contact with each other can suppress the resistance of the auxiliary capacitor wiring 13 from increasing. That is, passivation of the pulsation of the niche pulses supplied to the auxiliary capacitor wiring 13 can be suppressed. At the same time, since most of the contact holes 21 are arranged along the length of the auxiliary capacitor wiring 13, the area of the batch of wiring 19 outside the step difference of the contact hole 21 will increase, which can be suppressed. The resistance of the bulk wiring 19 itself rises, which can also suppress the bluntness of the potential pulses supplied to the auxiliary capacitor electrode. The paper size is based on the Chinese national kneading rate (CNS) A4 specification (210X297 mm) -12- (Please Please read the notes on the back before filling this page) Order printed by the Central Standards Bureau of the Ministry of Economic Affairs and printed by the Shellfish Consumer Cooperative A7 Β7_ V. Description of the invention (/ 〇), and you can get good picture quality. At the same time 'in batch wiring 1 9, will circulate the histogram of Figure 1 When three contact holes 21 are provided as shown in the figure, by arranging these along the long direction of the auxiliary capacitor wiring, since the contact holes 21 can be included, the direct current path can be ensured in most cases. At the same time, as shown in FIG. 2, each contact hole 21 is formed so as to have a large diameter gradually changing to a surface forming the bulk wiring 19, so that the bulk wiring 1 by the contact hole 21 can be reliably prevented. 9-section cut to obtain a different display of the value of the poor cross-talk caused by the non-section cut. "Although in the embodiment, the contact hole 21 shows a square, but it is not limited to this shape. Any shape such as a graphic or a polygon. At the same time, although the arrangement direction of the plurality of contact holes 31 is shown as being arranged along the longitudinal direction of the auxiliary capacitor wiring 13, the longitudinal direction of the auxiliary capacitor wiring 13 may also be shown in FIG. 3. As the number of columns m (shown as m = 3), and the direction orthogonal to this as the number of segments η (shown as η = 2), the contact hole 21 on the facet 小 of the contact hole 21 shown in FIG. 1 , Configure m X η. In addition, the arrangement direction of the contact holes 21 is not limited to the length direction of the auxiliary capacitor wiring 13, but as shown in FIG. 4, the plurality of contact holes 32 formed in a horizontally long direction will be along the auxiliary capacitor wiring in the long direction. In the state of length 1-3, a large number of segments are arranged in the up and down directions. When it is formed in this way, the length of the outer periphery of the contact hole can be increased when forming one contact hole, and it can be reduced (please read the precautions on the back before filling this page). CNS > Α4 specifications (210X297 mm) -13- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 ^ 34 a 4 5 A7 dagger a. 17. and 4 __ _B7_ ^ V. Description of the invention (11) Low batch Connection resistance of wiring and auxiliary capacitor wiring. [Effects of the invention] According to the present invention, since the number of contact holes is increased, the area beyond the step difference is increased. The resistance of the auxiliary capacitor wiring is prevented from increasing, and the passivation of the potential pulses supplied to the auxiliary capacitor electrodes is suppressed to obtain excellent image quality without poor crosstalk. At the same time, the area of the batch of wiring outside the stepped portion of the contact hole will increase, and It can suppress the increase of the resistance of the bulk wiring itself and the passivation of the potential pulses supplied to the auxiliary capacitor electrode, so that the image quality can be improved. Furthermore, it is possible to reliably prevent the segment of the bulk wiring from being cut by the contact hole. The horizontal crosstalk caused by segment cutting is eliminated, and the display can be well displayed. Brief description of the drawing [Fig. 1] The connection part of the batch wiring and the auxiliary capacitor wiring showing one embodiment of the liquid crystal display device of the present invention [Figure 2] It is a cross-sectional view taken along line II-II in Figure 1 above. [Figure 3] This paper scale follows the Chinese National Standard < CNS) A4 size (210x 297 mm) -14- — II-- ------- • Equipment ----- II Order ----- (Please read the precautions on the back before writing this page) 4 34445 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 5 2. Description of the invention (, 2) is the same plan view showing the connection part of the batch wiring and the auxiliary capacitor wiring in other embodiments. [Fig. 4] It is a plan view showing the connecting part of the batch wiring and the auxiliary capacitor wiring in the same embodiment as above. [Fig. 5] An electrical equivalent circuit diagram of the pixels of the liquid crystal display device. [Fig. 6] A plan view of an array substrate of a liquid crystal display device. [Fig. 7] It is a sectional view taken along the line VI-I-I of the same figure. [Fig. 8] The waveforms of the waveforms of the common reverse driving method used in the active matrix type liquid crystal display device shown above are shown. [Fig. 9] A plan view showing a connection portion between the conventional bunched wiring and the auxiliary capacitor wiring. 〔Figure 1 0〕 --------- Installation ------, π ------ ^ (Please read the note on the back before filling this page) This paper size is applicable to China Standard rate (CNS) Α4 specification (210X297 mm) · 15 _ 4 344 4 5 A7 B7 V. The description of the invention (θ) is the same I X_ IX cross-sectional view as shown in Figure 9 above. Explanation of symbols] 1 0 array substrate 1 1 glass substrate 1 2 gate line 1 2 a gate electrode 1 3 auxiliary capacitor wiring 1 4 gate insulation film 1 5 signal line 1 5 a drain 1 6 pixel electrode 1 7 source 1 8 thin film transistors 1 9 batch wiring 2 3 2 contact holes (please read the precautions on the back before filling out this page) 2 2 passivation layer This paper size applies to Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm ) _Bo-