KR100264188B1 - Liquid Crystal Display Device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides an active matrix liquid crystal display device which enables a good display without a horizontal crosstalk defect caused by breaking of a stage.

The gate line 12 and the storage capacitor wiring 13 are formed on the glass substrate 11, the gate insulating film 14 and the pixel electrode 16 are formed, and the wiring lines are bundled on the gate insulating film 14. A through hole is formed in a tapered shape with a large diameter toward the surface on which the 19 is formed to form a contact hole 21, which corresponds to one end side of each auxiliary capacitance wiring 13. Each of the three lines may be opened, and the signal line 15 and the bundle wiring 19 may be formed in a direction orthogonal to the storage capacitor wiring 13 through the upper portion of the contact hole 21.

Description

Liquid Crystal Display Device

The present invention relates to a matrix type liquid crystal display device.

The liquid crystal display device is widely used in various display devices because it is thin, light weight, and low power consumption. In particular, in recent years, it is required to have a high precision in a large screen, so the technology development is also active.

An active matrix liquid crystal display device has pixels arranged in a matrix on a display screen. The equivalent circuit of each pixel is shown in FIG. The signal line 15 and the gate line 12 are arranged in the orthogonal direction, and are connected to the drain electrode and the gate electrode of the thin film transistor (TFT) 18, respectively. Each TFT is formed near the intersection of the signal line 15 and the gate line 12. The source electrode and the reference power supply V _com of the TFT 18 are connected to the pixel electrode 16 and the counter electrode 34 of the liquid crystal layer, respectively. The liquid crystal layer acts as a light modulator and capacitance C _LC .

Since the TFT 18 has an inevitable parasitic capacitance between the gate electrode and the source electrode, the potential supplied to the pixel electrode 16 fluctuates in response to the rise of the pulse supplied to the gate electrode. It is also known to cause a potential change in the sustain period of the pixel potential due to optical leakage in the off period of the TFT 18.

The auxiliary capacitance C _s is provided in each pixel in order to control such potential variation and obtain good image quality.

As shown in FIGS. 6 and 7, the liquid crystal panel 100 has an array substrate 10 and a counter electrode 30, and is twisted nematic through alignment films 23 and 24, respectively. The liquid crystal layer 40 is held. The panel 100 is sealed with a sealant (not shown) at the end thereof.

The polarizer 37 is disposed outside the substrates 10 and 30, respectively. The array substrate 10 is provided such that, for example, 320 x 3 signal lines 15 and 240 gate scan lines 12 are perpendicular to each other. Each pixel electrode 16 is made of indium tin oxide (ITO) as a transparent conductive film. Inverse staggered TFTs 18 are provided near the intersections of the signal lines 15 and the gate lines 12.

Part of the gate line 12 becomes the gate electrode 12a of the TFT 18. The reverse staggered TFT 18 includes a gate insulating layer 14 made of silicon nitride (SiN _x ) on a gate electrode, an amorphous silicon (a-Si: H) active layer 33 on the gate insulating layer 14, and the The channel protection (passivation) layer 22 is included on the active layer 33.

The drain electrode 15a extending from the signal line 15 is connected to the active layer 33 of a-Si: H through an n + type a-Si: H ohmic contact layer 27. The source electrode 17 is also connected to the active layer 33 of a-Si: H through the n + type a-Si: H ohmic contact layer 27. The TFT 18 functions as a switching element.

Although the staggered type was used as the TFT 18, a staggered type TFT may be used. Instead of the a-Si: H active layer 33, a polysilicon (p-Si) active layer or a micro crystal film may be used.

The storage capacitor wiring 13 is provided in parallel with the gate line 12 and overlaps the pixel electrode 16. The storage capacitor Cs is formed by the pixel electrode 16 and the storage capacitor wiring 13.

The counter electrode 30 has a light blocking layer 35 disposed between the glass substrate 38, the RGB color filter layer 36, and the color filter layer. In the light shielding layer 35, incident light reaches a gap between the signal line 15 and the pixel electrode 16 and a gap between the gate line 12 and the pixel electrode 16 on the TFT 18 and the array substrate 11. It is installed to prevent it. The counter electrode 34 of ITO is also disposed on the color filter layer 36.

When driving the liquid crystal display, as shown in Fig. 8, for example, the H common inversion driving method is used, where "a" is the pixel potential and "b" is the common potential V _com of the signal line 15. is a signal potential (V _sig ) and "d" represents each waveform of the gate potential.

Here, the driving waveform supplied to the storage capacitor wiring 13 is the same as the waveform of the common potential b, and is a pulse waveform which repeats inversion every input time. In addition, since the pixel electrode 16 forms a capacitance in the signal line 15 and the storage capacitor wiring 13, the potential of the signal line 15 and the storage capacitor wiring 13 is also changed during the sustain period. As a result, the potential is inverted in a similar manner while maintaining a certain potential difference with the common potential b of the signal line 15.

However, the storage capacitor wiring 13 having such a function is usually formed of the same material as that of the gate line 12. As shown in FIG. 6, the storage capacitor wiring 13 is formed in a direction parallel to the gate line 12 and is formed to cross the central portion of the pixel electrode 16. In such a configuration, the storage capacitor wirings 13 are provided in the same number as the gate lines 12, but in general, the plurality of storage capacitor wirings 13 are provided with the same potential in a plurality of batches without supplying potentials one by one. have. For this reason, it is necessary to bundle a plurality of storage capacitor wirings 13 in a bundle other than the display area.

However, the gate lines 12 are arranged in the same direction with respect to each of the storage capacitor wirings 13, and in addition to each of the storage capacitor wirings 13, the gate lines 12 are insulated from the respective gate lines 12. It is necessary to wire in bundle.

Thus, as shown in Figs. 5 and 9, the signal line 15 and the signal line 15 are formed on the surface side of the gate insulating film 14 insulated from each gate line 12 or the storage capacitor wiring 13 in a portion outside the display area of the liquid crystal display device. The bundle wiring 19 is formed with the same material in the same direction. Each of the storage capacitor wirings 13 is connected to each of the storage capacitor wirings 13 through contact holes 20 passing through front and rear surfaces respectively provided at positions corresponding to one end of each storage capacitor wiring 13 of the gate insulating film 14. have. As a result, one end side of each storage capacitor wiring 13 is collectively connected by the bundle wiring 19.

As such, when the auxiliary capacitance wiring 13 and the bundle wiring 19 are electrically connected through the contact hole 20, the bundle wiring 19 is formed as shown in FIG. 10, which is a cross-sectional view of FIG. 9. As shown in the figure, a conductive film made of the same material as that of the signal line 15 is likely to be broken between the upper corner portions of the contact hole 20 so that the thickness between them becomes extremely thin.

However, if a break occurs, the resistance at that point becomes high, and the electrode potential pulse of the storage capacitor wiring 13 supplied from the bundle wiring 19 is slowed down. When the pulse is slowed as described above, the pixel potential is affected and transverse crosstalk failure occurs.

In this way, when the auxiliary capacitance wiring 13 and the bundle wiring 19 are connected through the contact hole 20, the end portions of the bundle wiring 19 are broken by the upper corners of the contact hole 20, and the bundle is broken. The electrode potential pulse of the storage capacitor wiring 13 supplied from the wiring 19 is slowed down, and the pixel potential is affected, resulting in a problem of lateral crosstalk failure.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to provide an active matrix liquid crystal display device which is free from lateral crosstalk defects due to disconnection of a stage and enables good display.

1 is a plan view showing a connection portion between a bundle wiring and a storage capacitor wiring, which is an embodiment of a liquid crystal display of the present invention;

2 is a cross-sectional view taken along the line II-II of FIG. 1;

3 is a plan view showing a connection portion between the bundle wiring and the auxiliary capacitance wiring in the embodiment of the liquid crystal display device according to the present invention;

4 is a plan view showing a connection portion between the bundle wiring and the auxiliary capacitance wiring of another embodiment of the liquid crystal display device according to the present invention;

5 is an electrical equivalent circuit diagram of a pixel of a liquid crystal display;

6 is a plan view of an array substrate of a liquid crystal display device;

7 is a cross-sectional view taken along line VII-VII of FIG. 6;

8 is a waveform diagram showing respective waveforms in the H common inversion driving method used in the active matrix liquid crystal display device;

9 is a plan view showing a connection portion between a conventional bundle wiring and a storage capacitor wiring;

10 is a cross-sectional view taken along line VII-VII of FIG. 9.

* Explanation of symbols for main parts of the drawings

10: array substrate 11: glass substrate

12: gate line 12a: gate electrode

13: auxiliary capacitance wiring 14: gate insulating film

15: signal line 15a: drain electrode

16: pixel electrode 17: source electrode

18: thin film transistor 19: bundle wiring

21, 31, 32: contact hole 22: passivation layer

23 and 24: polyimide film 27: ohmic contact layer

30: opposing substrate 33: active area

34: counter electrode 40: liquid crystal layer

The present invention relates to a plurality of gate lines and a plurality of signal lines crossing the gate lines, a gate insulating film interposed between the gate lines and the signal lines, and a thin film transistor formed at the intersection of the gate lines and the signal lines, the thin film transistor being controlled by the thin film transistor and A plurality of storage capacitor wirings each of which has a pixel electrode arranged in a matrix on one surface side of the gate insulating film, and a plurality of storage capacitor wirings respectively formed in a positional relationship formed on the other surface side of the gate insulating film and crossing substantially central portions of the pixel electrodes; A plurality of contact holes provided at portions facing the one end side and contact holes of the gate insulating film are formed in a direction intersecting with the respective storage capacitor wirings, and each of the storage capacitor wirings is formed through a plurality of contact holes, respectively. Array with bundle wiring to connect to one end By providing a plate, an opposing substrate having an opposing electrode and opposing the array substrate, and a liquid crystal sandwiched between the array substrate and the opposing substrate, a plurality of contact holes are provided, thereby increasing the area beyond the step and making seamless contact between the stages. Since the locations of the stepped portions increase, the increase in resistance of the storage capacitor wiring can be suppressed. As a result, since the slowing of the potential pulse supplied to the storage capacitor electrode can be suppressed, a good image quality without transverse crosstalk failure can be obtained.

In addition, the contact holes are arranged along the longitudinal direction of the storage capacitor wirings, so that areas outside the stepped portions in the contact holes of the wirings increase, the resistance of the bundle wirings themselves is suppressed, and the potential pulses supplied to the storage capacitor electrodes are slowed down. Can be suppressed, resulting in good image quality.

In addition, the contact hole is formed in a tapered shape with a large diameter toward the surface on which the bundle wiring is formed, thereby reliably preventing the break of the end of the bundle wiring due to the contact hole, and there is no transverse crosstalk defect due to the break of the end. Is displayed.

EMBODIMENT OF THE INVENTION Hereinafter, one Embodiment of the liquid crystal display device of this invention is described with reference to FIG.

In this embodiment, the configuration of the pixel portion of the liquid crystal display device is, as shown in Figs. 5 to 7, as the whole liquid crystal display device having a gate electrode 12a on the glass substrate 11, for example, molybdenum (Mo) Gate lines 12 are formed and at the same time substantially parallel to the gate lines 12, for example, the storage capacitor wiring 13 of molybdenum (Mo) is formed and such a gate line 12 and the storage capacitor A gate insulating film 14 of silicon nitride is formed on the glass substrate 11 so as to cover the wiring 13. On the surface of the gate insulating film 14, a signal line 15 of aluminum (Al) is formed in a direction orthogonal to the gate line 12, and a drain electrode 15a is formed on the signal line 15 to protrude.

An ITO pixel electrode 16 is formed on the gate insulating film 14, and a source electrode 17 is formed on the pixel electrode 16 and the gate electrode 12a, and the gate insulating film 14 is formed on the gate electrode 12a. The a-Si: H active layer 33, which is a semiconductor layer formed through, is connected to each of the source electrode 17 and the drain electrode 15a through the ohmic contact layer 27, thereby forming a reverse staggered thin film transistor. An 18 is formed and the thin film transistor 18 is located at the intersection of the gate line 12 and the signal line 15. In addition, the storage capacitor wiring 13 is located at a position crossing almost the center of the pixel electrode 16. As a result, an array substrate is formed.

1 shows a portion of the bundle wiring 19 of aluminum outside the display area of the storage capacitor wiring 13 as the liquid crystal display device, and the bundle wiring collectively connects and draws out the plurality of storage capacitor wirings. The bundle wiring 19 is formed in a direction orthogonal to each of the storage capacitor wirings 13 at a portion opposite to one end side of each storage capacitor wiring 13 through the gate insulating film 14. In addition, a contact hole 21 penetrating the front and back of the gate insulating film 14 is provided at a portion corresponding to the intersection of one end side of each storage capacitor wiring 13 and the bundle wiring 19 of the gate insulating film 14. We install plural. For this reason, the bundle wiring 19 is electrically connected through a plurality of tapered contact holes 21 having a large diameter toward one end side of each storage capacitor wiring 13 and the surface on which the bundle wiring 19 is formed. have. Further, a silicon nitride passivation film 22 and a polyimide alignment film 23 are sequentially formed on such a surface.

Further, a liquid crystal display device is constructed by placing a liquid crystal between the array substrate and the counter substrate by opposing the counter substrate having the counter electrode to the array substrate.

Next, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention will be described with reference to FIGS. 2, 6, and 7.

First, a molybdenum (Mo) film having a thickness of 3,000 kPa is formed on the glass substrate 11 by sputtering, and the gate electrode 12a, the gate line 12, and the auxiliary capacitance line 13 having a predetermined shape are formed by the photoetching method. Form. Subsequently, a thickness of 1,000 GPa serving as a channel region 33 of the thin film transistor 18 and a gate insulating film 14 of silicon nitride (SiN _x ) having a thickness of 4,000 μs is deposited on the entire glass substrate 11 by CVD (Chemical Vapor Deposition). The semiconductor layer of the i-type a-Si film and the silicon nitride having a thickness of 2,000 되는 serving as the channel protective film 22 are sequentially laminated. The SiN _x protective film is patterned so as to become the etching protective film 22 of the channel by the photo etching method. In addition, an n + type a-Si: H film having a thickness of 1,000 Å made of the ohmic contact layer 27 is formed by CVD, and the n + type a-Si and i type a-Si films are patterned into a predetermined shape. Next, by sputtering, a transparent conductive film made of ITO is formed and patterned to form the pixel electrode 16.

Thereafter, a resist is applied on the entire surface, and an etching resist which has to form a contact hole for connecting the bundle wiring formed after the gate insulating film 14 and the auxiliary capacitance wiring is patterned, and NH ₄ F (30%) and HF (6%). The gate insulating film 14 is etched with the etchant of the mixed liquid containing the (), and the through hole is opened to form the contact hole 21 in the gate insulating film 14. Since this is basically an isotropic moisture etching, a contact hole is formed in the gate insulating film 14 by a tapered inner wall. The opening on the bundle wiring 19 side of each contact hole 21 is larger than the opening on the storage capacitor wiring 13 side. The number of contact holes is three, for example, provided at the intersection of the bundle wiring 19 and each auxiliary capacitance wiring 13. The aluminum film is formed by sputtering, and the signal line 15, the source electrode 15a, the drain electrode 17, and the bundle wiring 19 are formed by photoetching.

Further, a 2,000-nm-thick SiNx passivation film 28 is formed on the entire surface by the CVD method, and patterning is formed so that portions corresponding to the pixel electrodes 16 are removed (see Fig. 2). The polyimide oriented film 23 is apply | coated on it.

In order to improve the film quality of the gate insulating film 14, for example, a two-layer film of SiNx and SiO is often used. Contact holes can be made easily even in such a device. A 2,000 mu SiN _x and 2,000 mu Si SiO film is made by CVD and an etchant of a mixed solution containing NH ₄ F (30%) and HF (6%) is used to make contact holes. As a result, the etching rate of the SiNx film is lower than that of the SiO film, and contact holes as shown in FIG. 2 are formed in the gate insulating film 14.

Here, in the above-described embodiment, the contact hole 21 for electrically connecting the one end side of each storage capacitor wiring 13 and the bundle wiring 19 is connected to the one end side of the storage capacitor wiring 13 and the bundle wiring 19. Since a plurality of portions are provided at each cross section of the cross section, the portion of the contact hole 21 of the bundle wiring 19 increases the portion of the conductive film that exceeds the step. For this reason, the increase in the resistance of the storage capacitor wiring 13 can be suppressed because the number of stepped portions that are in contact without disconnection increases. That is, the slowing of the potential pulse supplied to the storage capacitor wiring 13 is suppressed, and as a result, good image quality without crosstalk failure can be obtained.

In addition, since the plurality of contact holes 21 are arranged along the longitudinal direction of the storage capacitor wiring 13, regions other than the stepped portions in the contact holes 21 of the bundle wiring 19 increase and the bundle wiring 19 is increased. It is possible to suppress an increase in the resistance of itself, and also to suppress the slowing down of the potential pulse supplied to the storage capacitor electrode, thereby obtaining good image quality. In addition, since the current flows in the longitudinal direction of FIG. 1 in the bundle wiring 19, when the three contact holes 21 are provided as shown in the figure, by placing them along the longitudinal direction of the storage capacitor wiring 13, It is preferable because a plurality of longitudinal current paths can be secured including the contact holes 21.

Moreover, since each contact hole 21 was formed in the taper shape which becomes large diameter toward the surface in which the bundle wiring 19 is formed, as shown in FIG. 2, the end of the bundle wiring 19 by the contact hole 21 is short. It is possible to reliably prevent the breakage, and to obtain a good display without the transverse crosstalk failure caused by the breakage.

In addition, although embodiment showed that each contact hole 21 was rectangular, it is not limited to this shape, A shape, such as a circle or a polygon, may be sufficient.

Moreover, the case where it arrange | positions along the longitudinal direction of the storage capacitor wiring 13 as an arrangement direction of the several contact hole 31 was shown, As shown in FIG. m = 3) and m * n contact holes of a smaller area than the contact holes 21 shown in FIG. 1 may be arranged in a direction n orthogonal to this (n = 2).

In addition, the arrangement direction of the contact hole 21 is not limited only to the longitudinal direction of the storage capacitor wiring 13, and the storage capacitor wiring 13 has a longitudinal direction in which the plurality of contact holes 32 are formed to be horizontally long as shown in FIG. You may arrange | position it in multiple stages in the up-down direction in the state along the longitudinal direction of (). When formed in this way, the length of the outer periphery of a contact hole can be lengthened compared with the case where one contact hole is formed, and the connection resistance of a bundle wiring and a storage capacitor wiring can be reduced.

According to the present invention, a plurality of contact holes increase the area beyond the step and increases the locations of the stepped portions that are in seamless contact with each other, thereby increasing the resistance of the storage capacitor wiring and suppressing the increase in resistance of the storage capacitor wiring. Since the deterioration of the potential pulse can be suppressed, good image quality without transverse crosstalk defects can be obtained.

In addition, in the contact hole of the bundle wiring, an area outside the step portion increases, thereby suppressing an increase in the resistance of the bundle wiring itself, and suppressing the slowing of the potential pulse supplied to the storage capacitor electrode, thereby obtaining good image quality.

In addition, it is possible to reliably prevent the end break of the bundle wiring caused by the contact hole, and to display it satisfactorily without the lateral crosstalk defect caused by the end break.

Claims (9)

An array substrate, an opposing substrate facing the array substrate, and In the liquid crystal display device having a liquid crystal layer sandwiched between the array substrate and the opposing substrate, the array substrate is An insulator substrate for a liquid crystal display panel, A plurality of thin film transistors and auxiliary capacitances formed on the insulator substrate, A plurality of electrical conductor lines arranged on the insulator substrate and connected to the gate electrode of the thin film transistor and the electrode of the auxiliary capacitance; An insulating film which coats the insulator substrate and the electrical conductor line; A bundle line of an electrical conductor provided on the insulating film, There is a part where this bundle line and the electrical conductor line intersect, A plurality of contact holes drilled in the insulating film at each of the crossing portions; An electrical conductor film coated on an inner wall of the contact hole for connecting the electrical conductor line and the bundle line, And the plurality of contact holes provided at the intersections are arranged along the electrical conductor line. A plurality of gate lines, a plurality of signal lines crossing the gate lines, a gate insulating film interposed between the gate lines and the signal lines, a thin film transistor formed at an intersection of the gate lines and the signal lines, controlled by the thin film transistor, A plurality of storage capacitor wirings arranged in a matrix shape on one surface side, a plurality of storage capacitor wirings formed on the other surface side of the gate insulating film and disposed in a positional relationship crossing a portion of the pixel electrodes, and facing one end side of the storage capacitor wiring; The contact holes of the gate insulating film and the plurality of contact holes respectively provided in the portions are formed in a direction intersecting the respective storage capacitor wirings, and are connected to one end of each storage capacitor wiring through the plurality of contact holes, respectively. An array substrate having bundle wiring An opposing substrate facing the array substrate, and And a liquid crystal sandwiched between the array substrate and the counter substrate. The method of claim 2, And the contact hole is arranged along the longitudinal direction of the storage capacitor wiring. The method of claim 2 or 3, The contact hole is formed in a tapered shape with a large diameter toward the surface on which the bundle wiring is formed. The method of claim 1, And said insulating film comprises at least two insulating film layers of a first insulating film layer for directly coating said insulator substrate and electrical conductor lines and a second insulating film layer covering said first insulating film layer. The method of claim 1, The insulating film is composed of an insulating film layer of at least two layers of a first insulating film layer which directly coats the insulator substrate and the electrical conductor line and a second insulating film layer covering the first insulating film layer, and the contact hole is formed on the insulator substrate side. And the opening is smaller than the opening on the opposite side. The method of claim 1, The insulating film is composed of an insulating film layer of at least two layers of a first insulating film layer which directly coats the insulator substrate and the electrical conductor line and a second insulating film layer covering the first insulating film layer, and the contact hole is formed on the insulator substrate side. An opening is smaller than the opening on the opposite side, and the cross-sectional shape is tapered. The method of claim 1, The insulating film is composed of at least two insulating film layers of the first insulating film layer which directly coats the insulator substrate and the electrical conductor line and the second insulating film layer covering the first insulating film layer, and the etching rate of the second insulating film layer is And the contact hole is formed by etching the first and second insulating film layers using an insulating material larger than the etching rate of the first insulating film layer. The method of claim 1, The insulating film has an insulating film layer of at least two layers of a first insulating film layer made of silicon nitride which directly coats the insulator substrate and an electrical conductor line, and a second insulating film layer made of silicon oxide covering the first insulating film layer. And forming the contact hole by etching the second insulating film layer.

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