TW432700B - Memory-cells arrangement and its production method - Google Patents

Memory-cells arrangement and its production method Download PDF

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Publication number
TW432700B
TW432700B TW088104477A TW88104477A TW432700B TW 432700 B TW432700 B TW 432700B TW 088104477 A TW088104477 A TW 088104477A TW 88104477 A TW88104477 A TW 88104477A TW 432700 B TW432700 B TW 432700B
Authority
TW
Taiwan
Prior art keywords
memory
bit line
adjacent
memory cell
patent application
Prior art date
Application number
TW088104477A
Other languages
English (en)
Chinese (zh)
Inventor
Hans Reisinger
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW432700B publication Critical patent/TW432700B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
TW088104477A 1998-03-24 1999-03-22 Memory-cells arrangement and its production method TW432700B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19812948 1998-03-24

Publications (1)

Publication Number Publication Date
TW432700B true TW432700B (en) 2001-05-01

Family

ID=7862152

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088104477A TW432700B (en) 1998-03-24 1999-03-22 Memory-cells arrangement and its production method

Country Status (7)

Country Link
US (2) US6365944B1 (US07585860-20090908-C00162.png)
EP (1) EP1068644B1 (US07585860-20090908-C00162.png)
JP (1) JP2002508594A (US07585860-20090908-C00162.png)
KR (1) KR100623144B1 (US07585860-20090908-C00162.png)
CN (1) CN1165999C (US07585860-20090908-C00162.png)
TW (1) TW432700B (US07585860-20090908-C00162.png)
WO (1) WO1999049516A1 (US07585860-20090908-C00162.png)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002539611A (ja) 1999-03-09 2002-11-19 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 不揮発性メモリを有する半導体装置
JP4730999B2 (ja) * 2000-03-10 2011-07-20 スパンション エルエルシー 不揮発性メモリの製造方法
DE10051483A1 (de) * 2000-10-17 2002-05-02 Infineon Technologies Ag Nichtflüchtige Halbleiterspeicherzellenanordnung und Verfahren zu deren Herstellung
US6580120B2 (en) * 2001-06-07 2003-06-17 Interuniversitair Microelektronica Centrum (Imec Vzw) Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure
US6630384B1 (en) * 2001-10-05 2003-10-07 Advanced Micro Devices, Inc. Method of fabricating double densed core gates in sonos flash memory
JP3967193B2 (ja) * 2002-05-21 2007-08-29 スパンション エルエルシー 不揮発性半導体記憶装置及びその製造方法
US7423310B2 (en) * 2004-09-29 2008-09-09 Infineon Technologies Ag Charge-trapping memory cell and charge-trapping memory device
US7804126B2 (en) 2005-07-18 2010-09-28 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
KR100739532B1 (ko) 2006-06-09 2007-07-13 삼성전자주식회사 매몰 비트라인 형성 방법
US8441063B2 (en) * 2010-12-30 2013-05-14 Spansion Llc Memory with extended charge trapping layer

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4651184A (en) * 1984-08-31 1987-03-17 Texas Instruments Incorporated Dram cell and array
JP2596198B2 (ja) 1990-08-30 1997-04-02 日本電気株式会社 Ｍｏｓ型読み出し専用半導体記憶装置
JPH05102436A (ja) * 1991-10-09 1993-04-23 Ricoh Co Ltd 半導体メモリ装置とその製造方法
US5278438A (en) * 1991-12-19 1994-01-11 North American Philips Corporation Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure
DE19510042C2 (de) 1995-03-20 1997-01-23 Siemens Ag Festwert-Speicherzellenanordnung und Verfahren zu deren Herstellung
DE19514834C1 (de) * 1995-04-21 1997-01-09 Siemens Ag Festwertspeicherzellenanordnung und Verfahren zu deren Herstellung
KR0179807B1 (ko) * 1995-12-30 1999-03-20 문정환 반도체 기억소자 제조방법
KR100215840B1 (ko) * 1996-02-28 1999-08-16 구본준 반도체 메모리셀 구조 및 제조방법
US6118147A (en) * 1998-07-07 2000-09-12 Advanced Micro Devices, Inc. Double density non-volatile memory cells
US6207493B1 (en) * 1998-08-19 2001-03-27 International Business Machines Corporation Formation of out-diffused bitline by laser anneal

Also Published As

Publication number Publication date
WO1999049516A1 (de) 1999-09-30
EP1068644B1 (de) 2015-07-08
CN1165999C (zh) 2004-09-08
CN1294759A (zh) 2001-05-09
JP2002508594A (ja) 2002-03-19
KR100623144B1 (ko) 2006-09-12
KR20010042141A (ko) 2001-05-25
EP1068644A1 (de) 2001-01-17
US20020055247A1 (en) 2002-05-09
US6534362B2 (en) 2003-03-18
US6365944B1 (en) 2002-04-02

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