經濟部中夬標隼局貝T:消费合忭枝印聚 42565 9 (J6 1 STWlvDOC/Friink/OOi A7 _ B7 五、發明説明（I ) 本發明是有關於半導體的製造技術，且特別是有關於 一種金屬介層洞（Metai Via Hole)的製造方法。 金屬界層窗（Metal Via)在半導體製程的應用上，主要 是在於電極（例如源極（Source) /汲極（Drain))對外的連 接，與金屬層和金屬層之間的連接。當所形成的金屬介層 窗和經由光罩（Mask)定義的位置誤差過大，會對後續製程 有極大的影響。 一般測量偏差的大小係以關鍵尺寸偏差（Cri tica 1 Dimension Bias)當作測量的依據，所謂關鍵尺寸偏差就是 以ϋ刻後檢視（After Etching Inspection)的關鍵尺寸減 掉顯影後檢視（After Develop Inspection)的關鍵尺寸値 來表示。數値愈趨近於零，表示偏差愈小。由於製作金屬 介層洞時，在同一個晶片上製作的線寬不一定相同，造成 測量關鍵尺寸偏差的複雜性，因此選擇在晶片上非主動區 域（Nonactive Region)製作相同線寬的關鍵尺寸測試窗 (Critical Dimension Bar)。以測量關鍵尺寸測試窗的關 鍵尺寸偏差，來代表實際金屬介層洞的關鍵尺寸偏差。 習知方法中，請參照第1圖，金屬介層洞的製造方法 是在顯影步驟之後，要對已定義出金屬介層洞位置的介電 層進行蝕刻'顯影步驟之後的製程步驟一般可分爲四個步 驟··第·次烘烤（First Bake)ll、濕蝕刻（Wet Etching)12 ' 第—：次烘烤13和乾触刻（Dry E tch i ng) 1 4。一種習知的金 晡介層洞之製造方法荊阆時參照第丨圖與第2a 2c_’旨先 請參照第2a圖，在.導電層2 1上，例如是.命屬曆或足源 I ί I I : I I 1 - 1 I- - I I 1 I — I II Τ» *τ (诗先閱讀背面之注意事項再填寫本頁) ^ Ί :¾ ；ϊ] -ι·ί\|Λ] f ; r\s 1 λκ·! 1 經濟部中央標"局員消费合作.ft卬製 v 425659 五'發明説明（工） 極/汲極區，形成一介電層（Dielectrics)22，例如是以化 學氣相沈積法形成之二氧化矽層。接著，在介電層22上塗 佈一層光阻23，例如是正光阻（Positive Photoresist) 〇 之後，利用微影（Photolithography)製程，經過曝光 (Exposure) '顯影後，在欲形成金屬介層洞的位置上方之 光阻層23中形成一開口（Opening)24。 接著請參照第1與2b圖，將晶片置於加熱板（Hot Plate) 上，在約12G°C的溫度下進行第一次烘烤11，時間約1至2 分鐘。第一次烘烤11的目的是使光阻層23內的溶劑蒸發， 使光阻層23硬化（Curing)，以增加光阻的附著力 (Adhesion)。之後進行濕蝕刻12，例如用20比1的緩衝氧 化物触刻液（Buffered Oxide Etchant)，對開口 24下的介 電層22進行等向性（Isotropic)蝕刻。此時，只去除開口 24下方的部份介電層22，形成一第一蝕刻部份25。 接著請參照第1與2c圖，進行第二次烘烤13，例如將 晶片置於加熱板上，以約爲12G °C的溫度烘烤光阻層23約 1至2分鐘。晶片在濕蝕刻步驟12後須進行淸洗，此時， 光阻層23會再吸收水氣，因此，進行第二次烘烤13將水氣 蒸發。最後以光阻層23爲罩幕，對介電層22進行乾蝕刻 14，直到導電層21表面裸露爲止，形成一金屬介層洞26。 上述習知方法中，由於光阻層23在約10(M30 °C的高 溫下時會軟化產生形變，故在進行第二次烘烤13時，光[S 層2 3會因受熱丨ίϊί變形’使得第一·次烘烤13後的光阻圖案與 原先顯影後所定義的光阻圖案不同。尤其是在濕蝕刻丨2 4 (請先閱讀背面之注意事項再填寫本頁)The Ministry of Economic Affairs, the Ministry of Economic Affairs, the Ministry of Economic Affairs, T: Consumption, Cooperation, and Printing 42565 9 (J6 1 STWlvDOC / Friink / OOi A7 _ B7 V. Description of the Invention (I) This invention relates to semiconductor manufacturing technology, and in particular A method for manufacturing a metal via (Metai Via Hole). The application of a metal boundary layer (Metal Via) in a semiconductor process is mainly based on an electrode (such as a source / drain) facing outward. Connection, connection between the metal layer and the metal layer. When the formed metal interlayer window and the position error defined by the mask are too large, it will have a great impact on subsequent processes. Generally, the size of the measurement deviation is based on The critical dimension deviation (Cri tica 1 Dimension Bias) is used as the basis for measurement. The so-called critical dimension deviation is represented by the critical dimension of After Etching Inspection minus the critical dimension of After Develop Inspection. The closer the number is to zero, the smaller the deviation. Since the line widths made on the same wafer are not necessarily the same when making the metal vias, the deviation in the key dimensions of the measurement is caused. Complexity, so choose to make the critical dimension test window (Critical Dimension Bar) of the same line width in the non-active region on the wafer. To measure the critical dimension deviation of the critical dimension test window, to represent the key of the actual metal via hole Dimensional deviation. In the conventional method, please refer to FIG. 1. The manufacturing method of the metal interlayer hole is after the development step, the dielectric layer that has defined the position of the metal interlayer hole is etched. The process step after the development step Generally, it can be divided into four steps: First Bakell, Wet Etching 12 'First —: Bake 13 and Dry Etch 1 4. The conventional method for manufacturing the interstitial hole of the golden eagle refers to Figure 丨 and Figure 2a and 2c_ 'when referring to Figure 2a. On the conductive layer 21, for example, the fate calendar or foot source I ί II: II 1-1 I--II 1 I — I II Τ »* τ (Notes on the back of the poem before filling in this page) ^ Ί: ¾; ϊ] -ι · ί \ | Λ] f; r \ s 1 λκ ·! 1 Central Standard of the Ministry of Economic Affairs " Consumer cooperation of bureau members. ft system v 425659 Five 'invention description (work) / Drain region, a dielectric layer 22 is formed, such as a silicon dioxide layer formed by chemical vapor deposition. Next, a photoresist 23 is coated on the dielectric layer 22, such as a positive photoresist ( [Positive Photoresist] 〇 After that, after exposure (development) using a photolithography process, an opening 24 is formed in the photoresist layer 23 above the position where the metal interlayer hole is to be formed. Next, referring to Figures 1 and 2b, the wafer is placed on a hot plate, and the first baking is performed at a temperature of about 12G ° C for 11 to 2 minutes. The purpose of the first baking 11 is to evaporate the solvent in the photoresist layer 23 and harden the photoresist layer 23 to increase the adhesion of the photoresist (Adhesion). Thereafter, wet etching 12 is performed. For example, the dielectric layer 22 under the opening 24 is etched isotropically (Isotropic) using a buffered oxide etch solution (20: 1). At this time, only a portion of the dielectric layer 22 below the opening 24 is removed to form a first etched portion 25. Next, referring to Figures 1 and 2c, perform a second baking13. For example, place the wafer on a hot plate and bake the photoresist layer 23 at a temperature of about 12G ° C for about 1 to 2 minutes. After the wafer is wet-washed after the wet etching step 12, the photoresist layer 23 will absorb water vapor again. Therefore, the second baking 13 is performed to evaporate the water vapor. Finally, the photoresist layer 23 is used as a mask, and the dielectric layer 22 is dry-etched 14 until the surface of the conductive layer 21 is exposed to form a metal interlayer hole 26. In the above conventional method, since the photoresist layer 23 is softened and deformed at a high temperature of about 10 (M30 ° C), when the second baking 13 is performed, the light [S layer 2 3 will be deformed due to heat. 'Make the photoresist pattern after the first baking 13 different from the photoresist pattern defined after the original development. Especially in wet etching 丨 2 4 (Please read the precautions on the back before filling this page)
J-1T 屮㈦闲窣悻苹' r、S 1 \4叫,恪t :U>、、2.)·公缂 425659 0 6 l 5TWF DCC/[;rank/002 A7 __B7 五、發明説明（多） 後’光阻層23的底部在所形成之第一触刻部份25上方係懸 空，因此，再經過第二次烘烤13時，其關鍵尺寸偏差就更 大。 因此’爲了改善習知技藝的缺點，本發明提出一種金 屬介層洞的製造方法，將習知技藝中第二次烘烤的步驟去 除’避免光阻層因受熱產生形變，使關鍵尺寸偏差變大， 以利爾後的製程。 ' 爲達本發明上述的目的，提出一種金屬介層洞的製造 方法，包括下列步驟： a·在一導電層上形成一介電層； b. 在該介電層上形成一光阻層，對該光阻層進行曝 光、顯影步驟，在預定的位置形成一開口，曝露出該介電 層； c. 對該光阻層進行烘烤； d. 對曝露出的該介電層進行第一次蝕刻，形成一第一 飩刻部份；以及 e. 對曝露出的該介電層進行第二次蝕刻，形成該金屬 介層洞。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖是習知-種金屬介層涧的製造步驟流程圖； 第2 a _ 2 c圖是汽知…·種金屬介層洞的製造流程剖面示 —►I- i^i I - in I . I I - t. 、^--- -I n 1^1 1 ^^1 ^14 -5 (請先閱讀背面之注意事項再填寫本頁) Η 孓❾苹) \4#格 i 二1(】 '，公 ft、 ，! ^5659 0 6 1 5TWF.DOC/Frank/O02 Α7 Β7 五、發明説明（4) 意圖； 第3圖是根據本發明一較佳實施例，一種金屬介層洞 的製造步驟流程圖：以及 第4a-4c是根據本發明一較佳實施例，一種金屬介層 洞的製造流程剖面示意圖。 實施例 請參照第3圖，根據本發明一較佳實施例，金屬介層 洞的製造方法是在顯影步驟之後，要對已定義出金屬介層 洞位置的介電層進行蝕刻°顯影步驟之後的製程步驟分爲 三個步驟：烘烤31、第一次蝕刻32和第二次蝕刻33。金 屬介層洞之製造方法請同時參照第3圖與第4a-4c圖，首先 請參照第4a圖，在一導電層41上，例如是一金屬層或是源 極/汲極區，形成一介電層42，例如是以化學氣相沈積法形 成之二氧化矽層。接著，在介電層42上塗佈一層光阻43， 例如是正光阻。之後，利用微影製程，經過曝光、顯影後， 在欲形成金屬介層洞的位置上方之光阻層43中形成一開口 44 ° 經濟部中央標準局員工消費合作社印^J-1T (屮 ㈦, S 1 \ 4), t: U > ,, 2.) · Public 425659 0 6 l 5TWF DCC / [; rank / 002 A7 __B7 V. Description of the invention ( Many) The bottom of the rear photoresist layer 23 is suspended above the first engraved portion 25 formed. Therefore, when the second baking step 13 is performed, the critical dimension deviation is even greater. Therefore, 'in order to improve the shortcomings of the conventional technique, the present invention proposes a method for manufacturing a metal interlayer hole and removes the second baking step in the conventional technique' to prevent the photoresist layer from being deformed by heat and causing critical dimension deviation Great, after Eli's process. In order to achieve the above-mentioned object of the present invention, a method for manufacturing a metal interlayer hole is proposed, which includes the following steps: a. Forming a dielectric layer on a conductive layer; b. Forming a photoresist layer on the dielectric layer, Performing exposure and development steps on the photoresist layer to form an opening at a predetermined position to expose the dielectric layer; c. Baking the photoresist layer; d. Performing a first exposure to the dielectric layer Performing a second etch to form a first etched portion; and e. Performing a second etch on the exposed dielectric layer to form the metal interlayer hole. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: FIG. 1 It is a flowchart of the manufacturing steps of a conventional metal interlayer 涧; Figure 2a _ 2c is a cross-sectional view of the manufacturing process of a metal interlayer hole—►I- i ^ i I-in I. II -t., ^ --- -I n 1 ^ 1 1 ^^ 1 ^ 14 -5 (Please read the notes on the back before filling in this page) Η 孓 ❾Apple) \ 4 # 格 i 二 1 () ' , Ft,,! ^ 5659 0 6 1 5TWF.DOC / Frank / O02 Α7 Β7 V. Description of the invention (4) Intent; Figure 3 is a manufacturing step of a metal interlayer hole according to a preferred embodiment of the present invention Flow chart: and 4a-4c are schematic cross-sectional views of a manufacturing process of a metal interlayer hole according to a preferred embodiment of the present invention. Please refer to FIG. 3 for an embodiment. According to a preferred embodiment of the present invention, a metal interlayer hole The manufacturing method is to etch the dielectric layer that has defined the positions of the metal interlayer holes after the development step. The process steps after the development step are divided into three Steps: bake 31, first etch 32, and second etch 33. Please refer to Figure 3 and Figures 4a-4c for the manufacturing method of the metal interlayer hole, first refer to Figure 4a, a conductive layer A dielectric layer 42 is formed on, for example, a metal layer or a source / drain region, such as a silicon dioxide layer formed by a chemical vapor deposition method. Then, a layer is coated on the dielectric layer 42. The photoresist 43 is, for example, a positive photoresist. After that, using a photolithography process, after exposure and development, an opening is formed in the photoresist layer 43 above the position where a metal via is to be formed. 44 ° Consumption by employees of the Central Standards Bureau of the Ministry of Economic Affairs Cooperative seal ^
If· m u I n I n n K n In n n n I— i 丁 (請先閲讀背面之注意事項再填寫本頁) 接著請參照第3與4b圖，將晶片置於烤盤或烤箱上， 在約100至150°C的溫度下，較佳是約120°C，進行烘烤31， 利用烤盤時間約Q.5至3分鐘，利用烤箱時間約15至35分 鐘。烘烤31的目的是使光阻層43内的溶劑蒸發，使光阻層 43硬化，以增加光阻的附著力。之後進行第·次蝕刻32 , 例如是濕蝕刻，利用緩衝氧化物蝕刻液或氫氟酸（HF)對開 1 ] 4彳下方的介電層42進行等向性蝕刻。此時，只去除開丨丨 ft 經濟部中央標準局員丁：消費合作讧印裝 425659 06 1 5TWF.DOC/Frank/(!02 八7 ___ B7 _ 五、發明説明（厂） 44下方的部份介電層42，形成一第一蝕刻部份45。 接著請參照第3與4c圖，以光阻層43爲罩幕，對介電 層42進行第二次蝕刻33，例如是乾蝕刻，直到導電層41 表面裸露爲止，形成金屬介層洞46。在第二次蝕刻33前， 由於未再進行高溫烘烤，因此，光阻層43在所形成之第一 蝕刻部份45上方的部份就不會大幅變形，降低了關鍵尺寸 偏差過大的問題。 ^ 爲證明依照本發明一較佳實施例的金屬介層洞之製造 方法較習知者佳，本發明人作了一些實驗，在此謹以第1 表分析如後。請參照第1表，本表是一比較表，其顯示分 別依照本發明一較佳實施例與習知技藝方法所製得的金屬 介層洞與關鍵尺寸測試窗的關鍵尺寸偏差値。從第1表中 發現’“關鍵尺寸測試窗”的關鍵尺寸偏差由習知方法的 0·441μπι減少爲依照本發明一較佳實施例的-0.002 μπι，有 明顯的減少。而“金屬介層洞”的關鍵尺寸偏差由習知方法 的--0.041μιη改變爲依照本發明一較佳實施例的一 0·064μίη ’兩者相差不大。更重要的是“3倍標準差”項目， 3倍的關鍵尺寸偏差的標準差，從習知方法的0.38降低到 依照本發明一較佳實施例的〇.〇9，表示偏差的分佈範圍較 爲集中，且穩定。 1 I _ ί - --1. I m n I F - I . _ I I - -I i. I, (請先閱讀背面之注$項再填寫本頁) 7If · mu I n I nn K n In nnn I— i Ding (Please read the precautions on the back before filling this page) Then refer to Figures 3 and 4b, place the wafer on a baking sheet or oven, at about 100 At a temperature of 150 ° C, preferably about 120 ° C, baking 31 is performed, the baking tray time is about Q. 5 to 3 minutes, and the oven time is about 15 to 35 minutes. The purpose of baking 31 is to evaporate the solvent in the photoresist layer 43 and harden the photoresist layer 43 to increase the photoresist adhesion. Thereafter, a second etching 32 is performed, for example, wet etching, and isotropic etching is performed on the dielectric layer 42 below the substrate 1 using a buffer oxide etchant or hydrofluoric acid (HF). At this time, only remove the member of the Central Standards Bureau of the Ministry of Economic Affairs: consumer cooperation printing 425659 06 1 5TWF.DOC / Frank / (! 02 8 7 ___ B7 _ V. Part of the description of the invention (factory) 44 The dielectric layer 42 forms a first etching portion 45. Next, referring to FIGS. 3 and 4c, using the photoresist layer 43 as a mask, the dielectric layer 42 is etched a second time 33, such as dry etching, until Until the surface of the conductive layer 41 is exposed, a metal interlayer hole 46 is formed. Before the second etching 33, the high-temperature baking is not performed, so the portion of the photoresist layer 43 above the first etching portion 45 formed It will not be greatly deformed, which reduces the problem of excessive critical dimension deviation. ^ In order to prove that the method for manufacturing a metal interlayer hole according to a preferred embodiment of the present invention is better than the conventional one, the inventor has performed some experiments, here Please refer to Table 1 as follows. Please refer to Table 1. This table is a comparison table, which shows the metal interlayer holes and critical dimension tests made according to a preferred embodiment of the present invention and a conventional technique. The critical dimension deviation of the window is The "inch test window" critical dimension deviation is reduced from 0.41 μm in the conventional method to -0.002 μm in accordance with a preferred embodiment of the present invention, which is significantly reduced. The critical dimension deviation of the "metal via" is conventionally known. --0.041μιη of the method is changed to 0.064μίη according to a preferred embodiment of the present invention. The two are not much different. More important is the "3 times standard deviation" item, 3 times the standard deviation of the critical dimension deviation, The decrease from 0.38 of the conventional method to 0.09 according to a preferred embodiment of the present invention indicates that the distribution range of the deviation is more concentrated and stable. 1 I _ ί---1. I mn IF-I. _ II--I i. I, (Please read the note on the back before filling this page) 7
4 ‘Ο ο 〇 b 061 5TWF. DOC/Frank/00 2^ S Π 5 C Α7 Β7 五、發明説明（ 第1表 本發明一較佳實施例 習知方法 關鍵尺寸測試窗 -〇. 002μιη 0 · 44Ιμιη 金屬介層窗 -0.064μιη 、0 · 041μιη 3倍標準差 0.09 0.38 另外，也對依照本發明一較佳實施例及習知技藝中， 製造金屬介層洞方法的電路測試良率做一比較。請參照第 二表，“電路測試良率”從習知技藝的47%提升到依照本發明 一較佳實施例的62%。其中成長比率增加了 32%，對良率的 提昇有極大的助益。 第2表 ^>1 n i * i I I— I I m» -i ϋ ml - I. n 丁 ---° (請先閱讀背面之注意事項再填寫本頁) 本發明一較佳實施例 習知方法 電路測試良率（％) 62¾ 47% 經濟部4-標隼局丄消费"作"印焚 因此' 熟知此技藝者可瞭解，應用本發明之金屬介層 洞的製造方法，具有下列優點： 1 .關鍵尺寸偏差値較穩定，且容易控制，對次微米 (Subm i cron)的製程有絕對的助益3 2.可提昇產品電路測試的良率。 出·1，W 内 ΐ O. ( NS ^ \4tV ft 1 425659 〇615TWF.D〇C/Frank/0〇2 A7 —_____ B7 五、發明説明（Q ) 3. 關鍵尺寸測試窗和金屬介層洞的關鍵尺寸偏差値較 爲相近。 4. 依照本發明一較佳實施例的金屬介層洞製造方 法，較習知技藝的方法少一個製程步驟，可節省製程時間。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) .裝4 'Ο ο 〇b 061 5TWF. DOC / Frank / 00 2 ^ S Π 5 C Α7 Β7 V. Description of the invention (Table 1 A key dimension test window of a conventional method of a preferred embodiment of the present invention-0.002 μιη 0 · 44 Ιμιη metal interlayer window-0.064μιη, 0 · 041μιη 3 times standard deviation 0.09 0.38 In addition, a comparison of the circuit test yield of the method of manufacturing a metal via in accordance with a preferred embodiment of the present invention and the conventional technique is also made. Please refer to the second table, the "circuit test yield" has increased from 47% of the conventional skills to 62% according to a preferred embodiment of the present invention. The growth rate has increased by 32%, which greatly improves the yield. Table 2 ^ > 1 ni * i II— II m »-i ϋ ml-I. n 丁 --- ° (Please read the precautions on the back before filling this page) A preferred implementation of the present invention Example Known Method Circuit Test Yield (%) 62¾ 47% Ministry of Economic Affairs 4-Standards Bureau Consumption " Working " Printing and Burning Therefore, those skilled in the art can understand the manufacturing method of the metal interlayer hole applying the present invention , Has the following advantages: 1. The critical dimension deviation 値 is more stable and easy to control, Sub-micron (Subm i cron) process has absolute benefits 3 2. It can improve the yield of product circuit testing. Out · 1, W Inner O. (NS ^ \ 4tV ft 1 425659 〇615TWF.D〇C / Frank / 0〇2 A7 —_____ B7 V. Description of the invention (Q) 3. The critical dimension deviation of the critical dimension test window and the metal interlayer hole is relatively similar. 4. The metal interlayer according to a preferred embodiment of the present invention The hole manufacturing method has one less process step than the conventional method, which can save the process time. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Without departing from the spirit and scope of the present invention, some modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling this page )
<1T 每濟部中央標率局員工消費合作社印裝< 1T Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs