425653 ‘ A7 B7 五、發明說明（ -I發明領域 經濟部智慧財產局員工消費合作社印製 本發明係有關於-種淺溝渠隔離層，特別是有關於一 種形成淺溝渠隔離層的方法。 5-2發明背景： 隨著半導體積體電路積集度的增加 ^ a加 疋件與兀件間的 距離也日益縮短。當元件的距離縮翅至—定程度之後，元 件間的閉鎖（Latch Up)問題也將日形嚴重，甚至會造成 元件的癱m克服此—現象而達成有效的隔離不同元 件之目的，一種傳統上的作法是利用在半導體元件周圍， 蝕刻出一道淺溝渠並於其中填入介電材料，此一製程即為 目前業界習知的淺溝渠隔離（Shaii〇w Isolation)。然而，淺溝渠隔離層與半導體基材表面交接 的角落’常會在半導體製程中遭到蝕刻損失而形成向内凹 陷的曲面。其角落的損失常會造成半導體中摻雜區域之接 合面（Junction)的深度縮短，當淺溝渠隔離層的表面復 蓋導電層之後，將會造成其間漏電流的問題。此外在淺溝 渠隔離層與半導體基材表面交接的角落，亦容易造成電場 的集中而使得漏電流的問題變得更加嚴重。因此，淺溝渠 隔離層角落的損傷，將是影饗其隔絕能力的一項重要因 素。 參閱第1圖，顯示了一個淺溝渠隔離層之半導艘結構 ----ΜII.I-----裝 i — (請先閲讀背面之注意事項再填寫本頁) 訂： -線 本紙張尺度適用中國囷家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 42565 3 A； ---B7 五、發明說明（） 剖面圖。半導體基材102的表面具有墊氧化層（pa(i Oxide) 106’與氮化矽層（Sil icon Nitride) 104。透過微影製程 於氮化矽層104的表面定義出所欲形成隔離溝渠之區域 後’隨即進行姓刻、去光阻、沈積介電材料等步麻，以於 隔離溝渠之中形成溝渠隔離層108。 接著參閱第2囿’當溝渠隔離層108形成之後，隨即 除去氮化矽層1 0 4，並利用濕式蝕刻法剝除墊氧化層1 〇 6。 由於溝渠隔離層1 08的材料通常係為氧化矽，因此當進行 墊氧化層1〇6的剝除時’亦會對其造成損傷而形成如208 所示的角落損失。此外，為了配合元件製程，通常會於基 材的表面形成一層遮蔽氧化層（Screen Oxide) 202，接著 對整個半導體結構進行離子植入而形摻雜區域2〇4β 一般 而言’摻雜區域的深度距離半導體表面大約在1 500^左 右=然而*溝渠隔離層108與半導體結搆表面交接處的角 落’將由於蝕刻墊氧化層之損失’而使得其與接合面206 的深度210將小於1500Α。此外，當摻雜區域204形成之 後’必須要將遮蔽氧化層202剝除，而此一步琢又會造成 溝渠隔離層108更進一步的損失〃更有甚者，當離子植入 程序完成之後常會再形成一層犧牲氧化層（Sacrificial Oxide)後並將其剝除’以除去受離子轟擊後產生缺陷的基 材表面。一般而言，經過墊氧化層1〇6與遮蔽氧化層202 甚至犧牲氧化層等三道蝕刻程序之後，溝渠隔離層的角落 損失208大該會有400〜500A的深度，因此使得實際的接 合面深度只剩大約1000A的距離’而造成了隔離能力大幅 本紙張尺度適用中國國家標準（CNS)A4規格（210*： 297公釐） 7-----裝·----------訂---------線 (請先閲讀背面之沒意事項再填寫本頁) A7 42565 3 ______B7__ 五、發明說明（） 的降低。 另外，一些現今常用的半導體製程將會使得此一情況 更加惡化。參閱第3圖’顯示了在形成的溝渠隔離層ι〇8 之上沈積一層矽化姑導電層302的情形。當矽化姑導電層 302沈積於基材102上之後，由於分子間作用力的影響， 鈷會擴散至基材102之中而形成擴散層304。而沿著溝渠 絕緣層108所損失的角落308’鈷將更深入基材1〇2之中， 而造成接合面206深度更進一步的縮小，而使得漏電的問 題變得更加嚴重。 在美國專利No. 5, 521,422中提出了一種於淺溝渠隔離 層週邊形成間隙壁（Spacer )的方法，以保護其角落區域 不受蝕刻損傷。然而此方法必須增加額外製程而使得淺溝 渠隔離層的製程變得更加複雜。 綜上所述’亟需要提出一種新的淺溝渠隔離層之製 程’使得其角落區域不致受到蝕刻損傷，並同時能兼顧簡 化製程的目標’以提高淺溝渠隔離層的隔絕效果。 5-3發明目的及概述： 本發明之目的為在提供一種形成淺溝渠隔離層之方 法。 本發明之另一目的為在提供一種於形成淺溝渠隔離層 之製程中，保留墊氧化層作為遮蔽氧化層之方法，以保護 淺溝渠隔離層與基材交接處之角落不受蝕刻傷害。 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公茇） ; ’------Μ--------^---------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局貝工消費合作社印製 經濟部智慧財產局員Η消費合作社印製 42565 3 A7 ______B7_____ 五、發明說明（） 本發明揭露了一種用以隔絕半導體元件的方法。首先 於半導體基材的表面形成墊氧化層，接著於墊氧化層的表 面形成氮化矽層》再以光阻層定義所欲形成淺溝渠隔離層 的區域，並對此區域進行蝕刻以形成隔離溝渠。當隔離溝 渠形成之後，對其進行熱處理使得溝渠内側壁形成一層氧 化薄膜。再沈精介電層於氮化層的表面上，並同時填滿於 溝渠之内》隨後對此半導體的表面進行平坦化處理後，以 蝕刻方式除去氮化矽層。 當氮化矽層除去之後，保留位於基材表面的墊氧化層 作為配合後續雜子植入製程之遮蔽層。接著配合元件製程 對半導體结構中的主動區域（Active Area)進行離子植入 而形成摻雜區域，如P井、N井》之後，對半導體結構進 行加熱氧化處理，以於墊氧化層的下方形成一層犧牲氧化 層。最後利用蝕刻製程將墊氧化層與犧牲氧化層去除，以 完成淺溝渠隔離層之結構。 5-4圖式簡單說明： 第1囷 為傳統中具有淺溝渠隔離層之半導體結構刮 面囷。 第2圖 為傳統中蝕刻墊氧化層之後造成淺溝渠隔離 層角落損失的示意圊。 第3圖 為傳統中於淺溝渠隔離層與半導體基材表面 本紙張尺度適用中國1家標準（CNS)A4規格<210 X 297公釐） ^ 7 裝--------訂---------線 C請先間讀背面之注意事項再填寫本頁) 4 2 5 6 5 3 A7 _______B7 五、發明說明（ 沈積鈷化矽層，所造成之鈷向基材方向擴散 之不意圓。 (請先閱讀背面之注意事項再填寫本頁) 第4圖 為本發明中於半導體基材中形成隔離溝渠之 結構剖面圖。 第5圖 為本發明中於隔離溝渠中與半導體結構表面 沈積介電材料之示意圊。 第6圖 為本發明中對半導體結構進行平坦化製程之 示意圖。 第7围 為本發明中除去氮化矽層並形成額外低溫氧 化層之示意圖。 第8围 為本發明中除去墊氧化層與犧牲氧化層以形 成淺溝渠隔離層之示意圖。 ^5發明詳細說明： 經濟部智慧財產局員工消费合作社印製 首先參閱第4囷所顯示之半導體結構400其中包含基 材402、並於基材402的上方形成墊氡化層（Pad Oxide) 404與氮化石夕層（Silicon Nitride) 406。塾氧J化層404 _般皆透過加熱氧化的方式，於基材402的表面形一層厚 度約1 0 0〜2 0 0 A的氧化矽，至於氮化矽層4 0 6則多以化學 氣象沈積法（CVD)的方式沈積一層約1 0 00〜20 000A的氮 化矽。接著，於氮化矽層406的表面形成一光阻層408， 並透過微影製程（Photolithography)圓案化該光阻層以 定義出所欲形成隔離溝渠之區域412。接著對所定義出的 本紙張尺度適用中國國家標準（CNS)A4規格<210 * 297公釐）425653 'A7 B7 V. Description of the invention (-I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Invention Field This invention relates to a kind of shallow trench isolation layer, especially to a method of forming a shallow trench isolation layer. 5- 2 Background of the Invention: With the increase of the semiconductor integrated circuit accumulation degree, the distance between the plus piece and the element is also shortened. When the distance between the components is reduced to a certain degree, latch-up between components (Latch Up) The problem will also make the sun shape serious, and even cause the paralysis of the component to overcome this phenomenon to achieve the purpose of effectively isolating different components. A traditional method is to use a semiconductor trench to etch a shallow trench and fill it. Dielectric materials, this process is currently known in the industry as the shallow trench isolation (Shaii〇w Isolation). However, the corner of the shallow trench isolation layer and the surface of the semiconductor substrate interface 'is often formed during the semiconductor process due to etching loss and formed A curved surface that is recessed inward. The loss of its corner often causes the depth of the junction of the doped region in the semiconductor to be shortened. After the surface is covered with a conductive layer, the problem of leakage current will be caused. In addition, in the corner where the shallow trench isolation layer and the surface of the semiconductor substrate are connected, it is easy to cause the concentration of the electric field and the problem of leakage current becomes more serious. Therefore The damage to the corners of the shallow trench isolation layer will be an important factor affecting its isolation ability. Refer to Figure 1, which shows the semi-conductor structure of a shallow trench isolation layer-MII.I ---- -Install i — (Please read the notes on the back before filling out this page) Order:-The paper size of the thread is applicable to the Chinese Family Standard (CNS) A4 (210 X 297 mm) Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 42565 3 A; --- B7 V. Description of the invention () Sectional view. The surface of the semiconductor substrate 102 has a pad oxide layer (pa (i Oxide) 106 'and a silicon nitride layer (Sil icon Nitride) 104. After defining the area where the isolation trench is to be formed on the surface of the silicon nitride layer 104, a step of engraving, removing photoresist, and depositing a dielectric material is then performed to form a trench isolation layer 108 in the isolation trench. See section 2 After the trench isolation layer 108 is formed, the silicon nitride layer 104 is then removed, and the pad oxide layer 106 is removed by wet etching. Since the material of the trench isolation layer 108 is usually silicon oxide, When the pad oxide layer 10 is peeled off, it will also cause damage and form a corner loss as shown in 208. In addition, in order to cooperate with the component process, a shielding oxide layer (Screen Oxide) is usually formed on the surface of the substrate. 202, followed by ion implantation of the entire semiconductor structure to shape the doped region 204. Generally speaking, the depth of the doped region is about 1 500 ^ from the semiconductor surface = however * where the trench isolation layer 108 intersects with the surface of the semiconductor structure The corner 210 will be less than 1500A in depth from the joint surface 206 due to the loss of the oxide layer of the etch pad. In addition, when the doped region 204 is formed, the masking oxide layer 202 must be stripped, and this step will cause further loss of the trench isolation layer 108. What's more, when the ion implantation process is completed, it will often A sacrificial oxide layer is formed and stripped 'to remove the surface of the substrate that is defective after being bombarded by ions. Generally speaking, after three etching processes such as pad oxide layer 106, masking oxide layer 202, and even sacrificial oxide layer, the corner loss of the trench isolation layer is 208, which should have a depth of 400 ~ 500A, so that the actual joint surface The depth is only about 1000A, which results in a large isolation capacity. The paper size applies the Chinese National Standard (CNS) A4 specification (210 *: 297 mm). 7 ----- Installation --------- --Order --------- line (please read the unintentional matter on the back before filling out this page) A7 42565 3 ______B7__ 5. Decrease of the description of the invention (). In addition, some semiconductor processes commonly used today will make this situation worse. Referring to FIG. 3 ', it is shown that a silicided conductive layer 302 is deposited on the formed trench isolation layer ι0. After the silicided conductive layer 302 is deposited on the substrate 102, cobalt will diffuse into the substrate 102 due to the influence of intermolecular forces to form a diffusion layer 304. The corner 308 'cobalt lost along the trench insulation layer 108 will penetrate deeper into the substrate 102, causing the depth of the joint surface 206 to be further reduced, making the problem of leakage more serious. In U.S. Patent No. 5,521,422, a method of forming a spacer around a shallow trench isolation layer is proposed to protect its corner areas from being damaged by etching. However, this method must add additional processes to make the process of the shallow trench isolation layer more complicated. In summary, 'there is a need to propose a new process for the shallow trench isolation layer' so that corner areas are not damaged by etching, and at the same time, the goal of simplifying the process can be taken into consideration 'to improve the isolation effect of the shallow trench isolation layer. 5-3 Object and Summary of the Invention The object of the present invention is to provide a method for forming a shallow trench isolation layer. Another object of the present invention is to provide a method for retaining a pad oxide layer as a shielding oxide layer in a process for forming a shallow trench isolation layer, so as to protect the corner where the shallow trench isolation layer and the substrate meet from being damaged by etching. This paper size applies to China National Standard (CNS) A4 specification (210 * 297 cm); '------ M -------- ^ --------- ^ (please first Read the notes on the back and fill in this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Printed by the Consumers Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and printed by the Consumer Cooperative, 42565 3 A7 ______B7_____ V. Description of the Invention () This invention discloses a method for isolating semiconductors. Component method. First, a pad oxide layer is formed on the surface of the semiconductor substrate, and then a silicon nitride layer is formed on the surface of the pad oxide layer. The photoresist layer is used to define the area where the shallow trench isolation layer is to be formed, and this area is etched to form the isolation. ditch. After the isolation trench is formed, heat treatment is performed on the inner wall of the trench to form an oxide film. Re-sink the dielectric layer on the surface of the nitride layer and fill the trench at the same time. "After the surface of this semiconductor is planarized, the silicon nitride layer is removed by etching. After the silicon nitride layer is removed, the pad oxide layer on the surface of the substrate is retained as a shielding layer for cooperating with the subsequent hetero implantation process. Then, the active area in the semiconductor structure is ion-implanted to cooperate with the component manufacturing process to form a doped area, such as P well, N well. After that, the semiconductor structure is heat-oxidized to form under the pad oxide layer. A sacrificial oxide layer. Finally, an etching process is used to remove the pad oxide layer and the sacrificial oxide layer to complete the structure of the shallow trench isolation layer. 5-4 Schematic description: Section 1 is the traditional semiconductor structure scraping surface with a shallow trench isolation layer. Figure 2 is a schematic illustration of the corner loss of a shallow trench isolation layer caused by the traditional middle etch pad oxidation layer. Figure 3 shows the surface of the conventional medium trench isolation layer and the surface of the semiconductor substrate. The paper size applies to a Chinese standard (CNS) A4 specification < 210 X 297 mm. ^ 7 Packing -------- Order- -------- Line C, please read the notes on the back before filling this page) 4 2 5 6 5 3 A7 _______B7 V. Description of the invention (Cobalt silicon layer is deposited, the resulting cobalt is facing the substrate Unexpected circle of diffusion. (Please read the precautions on the back before filling out this page.) Figure 4 is a cross-sectional view of the structure of an isolation trench formed in a semiconductor substrate in the present invention. Schematic diagram of dielectric materials deposited on the surface of semiconductor structures. Figure 6 is a schematic diagram of the planarization process of semiconductor structures in the present invention. Figure 7 is a schematic diagram of removing the silicon nitride layer and forming an additional low-temperature oxide layer in the present invention. Figure 8 is a schematic diagram of removing a pad oxide layer and a sacrificial oxide layer in the present invention to form a shallow trench isolation layer. ^ 5 Detailed description of the invention: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics Firstly refer to the semiconductor structure 400 shown in Figure 4 Which contains substrate 402, A pad oxide layer (404) and a silicon nitride layer (Silicon Nitride) 406 are formed on the substrate 402. The oxide J layer 404 is generally formed on the surface of the substrate 402 by heating and oxidizing. A layer of silicon oxide with a thickness of about 100 ~ 2 0 A, and as for the silicon nitride layer 4 0, a layer of silicon nitride with a thickness of about 100 ~ 20 000 A is deposited by a chemical weather deposition method (CVD). A photoresist layer 408 is formed on the surface of the silicon nitride layer 406, and the photoresist layer is patterned by a photolithography process to define a region 412 where isolation trenches are to be formed. Then, the paper is defined. Standards apply to China National Standard (CNS) A4 specifications < 210 * 297 mm)
隔離溝渠區域進行蝕刻，以於基材中形成淺隔離溝渠4i2。 1 裝--- (請先閲讀背®之注意事項再填寫本頁) 接著參閱第5圖’除去半導體結構400表面的光阻層 408。之後，對半導體結構4〇〇進行加熱氧化處理使得淺 隔離溝渠412的表面形成一層厚度約為2〇〇〜35〇A的氧化 薄膜506。再沈積一層介電材料於隔離溝渠412中與氮化 矽層406的表面上。至於此實施例中所使用的介電材料則 為氧化石夕。由於所形成的介電層5〇2,在隔離溝渠412兩 側之主動區域（Active Area ) 508a、508b的上方會堆積 出較高的高度。為了輔助後續平坦化製程的進行，可於其 上方轴刻一部分的介電材料而曝露出部份的氮化矽廣 406。至於此部份的製程，可在介電層5〇2的表面形成光阻 層並對其加以圖案化以定義出所欲蝕刻的區域a以此光阻 為幕罩蝕刻此區域中的介電材料以曝露出部份的氮化矽層 406後’再除去該光阻層而形成如圊中所示的結構。接著 利用化學機械研磨法（CMP )對整個半導艘表面進行平坦 化’直到淺隔離溝渠中的介電材料表面與氮化矽層406的 表面大致成平坦為止，如第6圖所示。 -線 經濟部智慧財產局負工消費合作社印製 參閱第7圖’首先利用蝕刻製程除去氤化矽層4〇6。一 般而言’由於蝕刻選擇性的考量，此處剝除氮化矽層的方 法大多是使用熱磷酸進行之濕式蝕刻。當氮化石夕406除去 之後，保留墊氧化層404直接作為後續製程中的遮蔽氧化 層（Screen Oxide) » 由於傳統製程在氮化矽層去除之後，會緊接著除去塾 氧化層，而之後欲進行主動區域離子植入時，又會在基材 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） 425653The isolation trench area is etched to form a shallow isolation trench 4i2 in the substrate. 1 Pack --- (Please read the Precautions of Back® before filling this page) Then refer to Figure 5 'to remove the photoresist layer 408 on the surface of the semiconductor structure 400. Thereafter, a thermal oxidation treatment is performed on the semiconductor structure 400 to form a surface of the shallow isolation trench 412 with an oxide film 506 having a thickness of about 2000 to 35 Å. A further layer of dielectric material is deposited on the surface of the isolation trench 412 and the silicon nitride layer 406. As for the dielectric material used in this embodiment, it is stone oxide. Due to the formed dielectric layer 502, a high height will be deposited above the active areas 508a and 508b on both sides of the isolation trench 412. In order to assist the subsequent planarization process, a portion of the dielectric material may be etched on the upper shaft to expose a portion of the silicon nitride 406. As for this part of the process, a photoresist layer can be formed on the surface of the dielectric layer 502 and patterned to define the area to be etched a. The photoresist is used as a mask to etch the dielectric material in this area. After exposing a portion of the silicon nitride layer 406, the photoresist layer is removed to form a structure as shown in FIG. Then, the entire surface of the semiconducting vessel is planarized by chemical mechanical polishing (CMP) until the surface of the dielectric material in the shallow isolation trench and the surface of the silicon nitride layer 406 are substantially flat, as shown in FIG. 6. -Line Printed by the Consumer Goods Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Refer to Figure 7 'First, the silicon oxide layer 406 is removed by an etching process. Generally speaking, due to the consideration of etching selectivity, the methods for stripping the silicon nitride layer here are mostly wet etching using hot phosphoric acid. After the nitride stone 406 is removed, the remaining pad oxide layer 404 is directly used as a screen oxide in subsequent processes. »As the traditional process removes the hafnium oxide layer after the silicon nitride layer is removed, it is necessary to perform For active area ion implantation, the Chinese paper standard (CNS) A4 (210 * 297 mm) will be applied to the paper size of the substrate. 425653
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的表面形成一層額外的遮蔽氧化層並於植入的過程结束後 予以剝除。而這樣的製程中，每一次除去氧化層的步驟都 將造成淺溝渠隔離區域與半導體底材表面接合處角落之材 料損失’而造成溝渠隔離層的效果大為降低。 因此在本發明中氮化矽層406除去之後，將不會立即 對塾氧化層404進行濕式蝕刻’而是進行主動區域5〇8a、 50 8b的離子植入。透過適當光罩的定義，將可對所需的主 動區域令植入特定的雜質，以形成p井或N井的結構.如 圖中所示對主動區域508b進行離子植入以形成摻雜區域 702’而其接合面704的深度則約在4000〜8000A之間。此 時墊氧化層404的存在不但可以防止淺溝渠隔離層5〇2與 基材402表面接合之角落708處發生蝕刻還可以作為離子 植入的遮蔽層’以防止離子植入時發生所謂的通道現象D 當離子植入程序完成之後，接著對整個半導體結構進 行熱處理。將整個半導體結構置於“㈧〜丨丨“^的環境中 進行加熱氧化處理約30〜60sec的時間即可於塾氧化廣 404的下方形成一層犧牲氧化層（SacrificUi Uyer) 70 6。由於進行離子植入時，係透過電場對離子加速而轟擊 晶圓的表面’而當離子轟擊晶園時將造成表面產生殘留應 力甚至產生缺陷。因此，對半導雜結構進行熱處理將可以 使得這些部份氧化，並於後續的蝕刻步驟中隨著墊氧化層 404 —起除去。 最後利用濕式蝕刻法將墊氧化層4 0 4與犧牲氧化廣 706同時除去，以留下如第8圖所示的淺溝渠隔離層5〇2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 諳 先 閱 讀 背 & 之 注 意 事 項 再 填 I I I I 訂 線 經濟部智慧財產局員工消费合作社印製 425653 Α7 Β7 五、發明說明（） 而淺溝渠隔離層502的角落708將不會如習知技藝般向基 材40 2的方向產生嚴重的凹陷。此即意味著，摻雜區域2〇4 沿淺溝渠隔絕區域502週邊的接合面深度將較採用習知技 藝時為更深，也就是說淺溝渠隔離層502對元件間的隔絕 效果將會越好•將可以更進一步簡化傳統製程十反覆形成 氧化層的步驟，更使得此一形成淺溝渠隔離層之製程變得 更為簡潔》 本發明以一較佳實施例說明如上，僅用於藉以幫助了 解本發明之實施，非用以限定本發明之精神，而熟悉此領 域技藝者於領悟本發明之精神後，在不脫離本發明之精神 範圍内，當可做些許更動潤飾及等同之變化替換，其專利 保護範圍當視後附之專利申請範圍及其等同領域而定β (靖先閲讀背面之注意事項再填窝本頁) 裝-------訂--------線，1 經濟部智慧財產局員工消费合作社印製 本紙張尺度適用中S圉家標準（CNS)A4規格（210 * 297公釐）An additional masking oxide layer was formed on the surface of the surface and stripped off after the implantation process was completed. In such a process, each step of removing the oxide layer will cause the loss of material at the corner of the shallow trench isolation area and the surface of the semiconductor substrate, and the effect of the trench isolation layer is greatly reduced. Therefore, after the silicon nitride layer 406 is removed in the present invention, the hafnium oxide layer 404 will not be wet-etched immediately ', but the ion implantation of the active areas 508a and 508b will be performed. Through the definition of an appropriate photomask, specific impurities can be implanted into the required active area to form a p-well or N-well structure. As shown in the figure, the active area 508b is ion-implanted to form a doped area. 702 ', and the depth of the joint surface 704 is about 4000 ~ 8000A. At this time, the presence of the pad oxide layer 404 can not only prevent etching at the corner 708 where the shallow trench isolation layer 502 is bonded to the surface of the substrate 402, but also can be used as a shielding layer for ion implantation to prevent so-called channels from occurring during ion implantation. Phenomenon D After the ion implantation process is completed, the entire semiconductor structure is then heat-treated. Placing the entire semiconductor structure in an environment of "㈧ ~ 丨 丨" ^ and performing a thermal oxidation treatment for about 30 ~ 60sec can form a sacrificial oxide layer (SacrificUi Uyer) 70 6 under the 塾 oxide film 404. When ion implantation is carried out, the ions are accelerated by an electric field to bombard the surface of the wafer ', and when the ions bombard the crystal garden, residual stress or even defects will occur on the surface. Therefore, heat treatment of the semiconducting impurity structure can oxidize these parts and remove them with the pad oxide layer 404 in the subsequent etching step. Finally, the pad oxide layer 4 0 4 and the sacrificial oxide layer 706 are removed at the same time by a wet etching method, so as to leave a shallow trench isolation layer 50 as shown in FIG. 8. This paper standard applies to the Chinese National Standard (CNS) A4 specification. (210 X 297 mm) 阅读 Read the back & notes before filling in IIII. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperative of the Ministry of Economic Affairs. Printed 425653 Α7 Β7. 5. Description of the invention () The corner 708 of the shallow trench isolation layer 502 will be There is no serious depression in the direction of the substrate 402 as in the conventional art. This means that the depth of the joint surface of the doped region 204 along the periphery of the shallow trench isolation region 502 will be deeper than when using conventional techniques, that is, the better the isolation effect of the shallow trench isolation layer 502 between components will be • It will further simplify the traditional process of repeatedly forming the oxide layer, making the process of forming a shallow trench isolation layer more concise. The invention is described above with a preferred embodiment, and is only used to help understand The implementation of the present invention is not intended to limit the spirit of the present invention, and those skilled in the art can understand the spirit of the present invention and make some modifications and equivalent changes without departing from the spirit of the present invention. The scope of its patent protection depends on the scope of the attached patent application and its equivalent field β (Jing first read the precautions on the back before filling in this page) Line, 1 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size is applicable to the Chinese Standard (CNS) A4 (210 * 297 mm)