4 2R6 1 6 A7 B7 經濟部中央梯率局貝工消費合作社印製 五、發明説明（1 ) 本發明是有關於一種半導體製程，且特別是有關於 一種整合金屬梦化物閘極（silicide gate)與自對準金屬妙 化物（salicide)的製程。 為了提尚半導體元件的操作速度與性能，一般常見 的MOS電晶體’必須將作為其閘極電極的複晶石夕以及源 極、没極的片電阻（sheet resistance)，還有各電極間接觸 點的電阻值，盡可能地降低。由於以石夕材質作為導電媒 介難能發揮實效’於是利用金屬（例如鈦或鈷）與矽反應成 低電阻碎化物的方式，就被廣泛地採用，期使電晶艘内 導通電流的部份能有更低的電阻值，而提昇其效能。利 用鈦金屬的自對準金屬矽化物製程（self_aUgned silicide ;簡稱salicide)是目前業界經常使用的方式之一， 其方法是先利用滅鍵或物理氣相沈積的方式在一 MOS結 構上形成鈦膜’再利用快速熱回火（rapid thermal annealing ; RTA)，使鈦金屬與源極/汲極上的矽及閘極 上的複晶矽反應，形成矽化鈦（TiSi2)。而未參與反應或 反應後所剩餘的鈦，則以濕蝕刻的方式去除，而在MOS 三個極的表面上留下TiSi2。 然而’假若上述的自對準製程在MOS側壁層（spacer) 上殘留有鈦金屬或是矽化鈦*則會產生所謂源極/汲極橋 接（S/D bridging)的問題，造成電極間短路的現象。尤其 是當應用在記憶元件的製作時，此種現象更為嚴重，往 往導致良率的降低。因此，如何能在不影響記憶電路 (memory circuit)的良率下，同時提昇邏輯電路（logic (請先聞讀背面之注意事項再填寫本頁)4 2R6 1 6 A7 B7 Printed by Shelley Consumer Cooperative of Central Gradient Bureau of the Ministry of Economic Affairs 5. Description of the Invention (1) The present invention relates to a semiconductor process, and in particular to an integrated metal silicide gate Process for salicide with self-aligned metal. In order to improve the operating speed and performance of semiconductor devices, common MOS transistors must use polycrystalline spar as the gate electrode, sheet resistance of the source and non-electrodes, and contact between the electrodes. The resistance value of the point is reduced as much as possible. Because it is difficult to use Shixi material as a conductive medium, it is difficult to achieve effectiveness. Therefore, a method of reacting a metal (such as titanium or cobalt) with silicon to form a low-resistance shattered compound has been widely used in order to make the current part in the transistor ship conductive. Can have a lower resistance value and improve its performance. Self-aUgned silicide (salicide) using titanium is one of the frequently used methods in the industry. The method is to first form a titanium film on a MOS structure by means of bond destruction or physical vapor deposition. 'Using rapid thermal annealing (RTA), the titanium metal reacts with the silicon on the source / drain and the polycrystalline silicon on the gate to form titanium silicide (TiSi2). The titanium that is not involved in the reaction or after the reaction is removed by wet etching, leaving TiSi2 on the surface of the three MOS electrodes. However, 'if the above self-alignment process leaves titanium or titanium silicide on the MOS sidewall spacer *, it will cause the so-called source / drain bridging (S / D bridging) problem, resulting in short circuit between electrodes phenomenon. Especially when applied to the production of memory elements, this phenomenon is more serious, which often leads to a reduction in yield. Therefore, how to improve the logic circuit at the same time without affecting the yield of the memory circuit (logic (please read the precautions on the back before filling this page)
T 裝. 訂 本紙張尺度適用中國圃家標準（CNS ) A4規格（210X297公缝） 〇 經濟部中央樣準局貝工消费合作社印裝T Pack. Binding This paper size is in accordance with China Garden Standard (CNS) A4 (210X297 cm) 〇 Printed by the Shell Consumer Cooperative of the Central Samples Bureau of the Ministry of Economic Affairs
AT B7 五、發明説明（2) circuit)的操作性能，便成為當前的主要課題。 有鑑於此’本發明的主要目的就是提供一種整合金 屬矽化物閘極與自對準金屬矽化物的製程，一方面可在 邏輯電路區形成自對準金屬矽化物（salicide)，以提昇其 性能；另一方面，在記憶電路區則同時形成金屬石夕化物 閘極（silicide gate);由於在記憶電路區的電晶體，只有閘 極上形成有金屬矽化物，因此可避免閘極與源極/汲極發 生短路的風險，並降低源極/汲極區之接合漏電流 (junction leakage) 〇 根據上述目的，本發明提供一種整合金屬矽化物閘 極與自對準金屬矽化物的製程，包括下列步驟：（a)首先 在一矽基底上，以一淺溝渠或場氧化層隔離出第一主動 區與第二主動區，其中該第一主動區係用來形成邏輯電 路’該第二主動區係用來形成記憶電路；（b)分別在第一 主動區與第二主動區上，形成至少一電晶體，包括一複 晶矽閘極、及一源極/汲極區；（c)形成一遮蔽層，覆蓋於 該些電晶體上；（d)去除複晶矽閘極上的遮蔽層；（e)去除 位於第一主動區之遮蔽層；以及（f)以一自對準金屬矽化 物製程’在第一主動區的複晶矽閘極、及源極/汲極區上 形成金屬矽化物，同時在該第二主動區的複晶矽閘極上 形成金屬矽化物。 在本發明之較佳實施例中，步驟（d)可利用一犧牲層 作為罩幕，先覆蓋住源極/汲極區上的遮蔽層，然後再以 濕浸泡（wet dip)或乾蚀刻的方法，去除閘極上方的遮蔽 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐} (讀先鬩讀背面之注意事項再填寫本頁) -裝‘ 訂 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（3) 層；而步驟（e)可利用微影與蝕刻製程，先將第二主動區 用一光阻覆蓋住後’再去除第一主動區的遮蔽層。 為讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式， 作詳細說明如下： 圖式之簡單說明： 第1-5圖繪示依本發明之製程同時形成金屬矽化物 閘極與自對準金屬矽化物之剖面示意圊。 符號說明： 10〜矽基底；14a、14b〜複晶矽閘極；18a、18b ~ 源極/汲極區；13〜閘氧化層：16〜侧壁層；20〜覆蓋氧 化層；22、24〜光阻層；30a、30b〜矽化鈦。 實施例 首先請參照第1圊’在一矽基底1〇上，以淺溝渠12 隔離出第一主動區I與第二主動區II，其中第一主動區I 係用來形成邏輯電路（logic circuit)、第二主動區II係用 來形成記憶電路（memory circuit)。接著，分別在第一主 動區I與第二主動區Π上’各形成至少一電晶趙，包括 複晶矽閘極14、源極/汲極區18、閘氧化層13、及側壁 層16 ’其中位於第一主動區I的閘極、源極/没極區特稱 為14a、18a，而位於第二主動區π的閘極、源極/汲極 區特稱為14b、18b。 請繼續參照第1圖，形成一遮蔽層覆蓋於該些電晶 體上，其材質可為氧化矽、氮氧化矽（Si〇N)、或氣化妙； (請先閱讀背面之注意事項再填寫本頁} Γ -eAT B7 V. Invention description (2) The operation performance of the circuit) has become the main issue at present. In view of this, the main purpose of the present invention is to provide a process for integrating metal silicide gates and self-aligned metal silicides. On the one hand, self-aligned metal silicides can be formed in the logic circuit area to improve its performance. On the other hand, a metal silicide gate is formed in the memory circuit area at the same time; because the transistor in the memory circuit area, only metal silicide is formed on the gate, so the gate and the source / The risk of short-circuiting the drain electrode and reducing junction leakage in the source / drain region. According to the above purpose, the present invention provides a process for integrating a metal silicide gate and a self-aligned metal silicide, including the following: Steps: (a) First, a first active region and a second active region are separated by a shallow trench or field oxide layer on a silicon substrate, wherein the first active region is used to form a logic circuit 'the second active region Is used to form a memory circuit; (b) forming at least one transistor on the first active region and the second active region, including a polycrystalline silicon gate and a source / drain region; (C) forming a shielding layer covering the transistors; (d) removing the shielding layer on the polycrystalline silicon gate; (e) removing the shielding layer located in the first active region; and (f) using a self-alignment The quasi-metal silicide process' forms a metal silicide on the complex silicon gate in the first active region and the source / drain region, and simultaneously forms a metal silicide on the complex silicon gate in the second active region. In a preferred embodiment of the present invention, in step (d), a sacrificial layer can be used as a mask to cover the shielding layer on the source / drain region first, and then wet dip or dry etched Method to remove the shadow above the gate electrode. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (read the precautions on the back first and then fill out this page)-Binding 'A7 B7 Central Bureau of Standards, Ministry of Economic Affairs Employee Consumer Cooperatives Co., Ltd. 5. Description of invention (3) layer; and step (e) can use the lithography and etching process to cover the second active area with a photoresist first, and then remove the shielding layer of the first active area. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: Section 1 Figure -5 shows a schematic cross-section of a metal silicide gate and a self-aligned metal silicide formed simultaneously according to the process of the present invention. Symbol description: 10 ~ silicon substrate; 14a, 14b ~ polycrystalline silicon gate; 18a, 18b ~ Source / drain region; 13 ~ gate oxide layer: 1 6 ~ sidewall layer; 20 ~ cover oxide layer; 22, 24 ~ photoresist layer; 30a, 30b ~ titanium silicide. For example, please refer to the first step “1” on a silicon substrate 10 and isolate it with shallow trench 12 The first active region I and the second active region II, wherein the first active region I is used to form a logic circuit, and the second active region II is used to form a memory circuit. An active region I and a second active region II each have at least one transistor formed thereon, including a polycrystalline silicon gate 14, a source / drain region 18, a gate oxide layer 13, and a sidewall layer 16 '. The gate and source / drain regions of the active region I are designated as 14a and 18a, while the gate and source / drain regions of the second active region π are designated as 14b and 18b. Please continue to refer to FIG. 1 , Forming a shielding layer to cover these transistors, the material can be silicon oxide, silicon oxynitride (SiON), or gasification; (Please read the precautions on the back before filling this page} Γ -e
I 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） 經濟部中央揉準局員工消费合作社印裝 A7 B7 五、發明説明（4 ) 在本實施例中是一覆蓋氧化層20 (cap oxide)。在後續的 salicide製程中’此覆蓋氧化層20將作為第二主動區π 之源極/汲極區18b的遮蔽層。接著’在覆蓋氧化層20 上形成一層平坦的犧牲層，例如塗佈一層平坦的光阻層 22 ’此光阻層可為傳統式光阻、或底層反反射塗層光阻 (bottom ARC P.R.)。 ¥ 請參照第2圖，回钱刻上述光阻層22，直到露出閘 極上方的覆蓋氧化層20為止》之後並以濕浸泡（wet dip) 或乾蝕刻的方式’去除氧化層20所露出之部份，得到如 第2圖所示的結構。此時，覆蓋在複晶矽閘極14a、i4b 上的氧化層已經完全去除。 請參照第3圖’接下來的步驟是去除位於第一主動 區I上的覆蓋氧化層。首先將殘餘的光阻層22，去除，再 利用微影技術將一光阻層24定義在第二主動區π之上， 並以此為罩幕，蝕刻去除位於第一主動區I的覆蓋氧化層 2(Τ。蝕刻完畢後’將光阻24去除，留下如第4圖所示之 結構。此時，第一主動區I上的源極/汲極區18a已經裸 露出來’而位在第二主動區Π上的源極/汲極18b則保持 為氧化層20'所覆蓋。 接下來的步驟，是利用傳統的自對準金屬矽化物製 程’在第一主動區I形成salicide的同時，也在第二主動 區II上形成silicide gate。先在第一主動區I與第二主動 區ΪΙ既有的結構上，濺鍍一層Ti ;接著，以第一道快速 熱回火（RTA)，使Ti與閘極14a、14b的複晶矽和源極/ 本紙張尺度適用中國國家橾準（CNS ) Α4規格（210Χ297公楚） ί請先閲讀背面之注意事項再填寫本頁) 裝' 訂 425616 A7 B7 五'發明説明（5) 汲極區18a的單晶矽反應形成Tisi2 (在此為電阻率較高 的C49相TiSiz) ’而未與矽反應之部份Ti會形成TiN。 請參照第5圖，以濕蝕刻法選擇性地去除未反應的耵/丁⑺ 後’即在第一主動區I的閘極和源極/汲極區14a、i8a 留下矽化鈦30a，是為自對準金屬矽化物；同時在第二 主動區II的閘極14b留下矽化鈦30b，作為金屬矽化物 閘極。之後’再以一道較高溫度的快速熱回火，將原來 的C49相TiSG轉變成低電阻率的C54相TiSi2，以完成 該salicide製程。 由上述可知’本發明的製程在第一主動區I的邏輯電 路上形成了自對準金屬矽化物30a，可提昇其性能，同 時在第二主動區II的記憶電路上形成金屬矽化物閘極 30b，以避免良率降低。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明’任何熟習此技藝者，在不脫離本發明 之精神和範圍内’當可作各種之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。 (請先閲讀背面之注意事項再填寫本頁)I This paper size applies Chinese national standards (CNS > A4 size (210X297 mm). Printed by the Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs, printed by A7 B7. V. Description of the invention (4) In this embodiment, it is an oxide layer 20 (cap oxide). In the subsequent salicide process, 'This capping oxide layer 20 will serve as a shielding layer for the source / drain region 18b of the second active region π. Then,' a flat sacrificial layer is formed on the capping oxide layer 20. For example, coating a flat photoresist layer 22 'This photoresist layer can be a conventional photoresist or a bottom anti-reflective coating photoresist (bottom ARC PR). ¥ Please refer to Figure 2 and engraved the above photoresist After the layer 22 is exposed to cover the oxide layer 20 above the gate, the exposed portion of the oxide layer 20 is removed by wet dip or dry etching to obtain a structure as shown in FIG. 2. At this time, the oxide layer covering the polysilicon gates 14a, i4b has been completely removed. Please refer to FIG. 3 'The next step is to remove the cover oxide layer located on the first active region I. First, the remaining light Resist layer 22, removed, and reused lithography A photoresist layer 24 is defined above the second active region π and is used as a mask to etch and remove the covering oxide layer 2 (T in the first active region I. After the etching is completed, the photoresist 24 is removed, The structure shown in Figure 4 is left. At this time, the source / drain region 18a on the first active region I has been exposed, and the source / drain 18b on the second active region Π is maintained. Covered by the oxide layer 20 '. The next step is to use the conventional self-aligned metal silicide process' to form a salicide in the first active region I and a silicide gate on the second active region II. A layer of Ti is sputtered on the existing structures of the first active area I and the second active area Ϊ1; then, the first rapid thermal tempering (RTA) is performed to make Ti and the polycrystalline silicon and source of the gates 14a, 14b Polar / This paper size applies to China National Standards (CNS) Α4 size (210 × 297). Please read the notes on the back before filling out this page.) Binding 425616 A7 B7 Five 'invention description (5) Drain pole area 18a The single-crystal silicon reacts to form Tisi2 (here, the C49 phase TiSiz with a higher resistivity) ′ but does not react with silicon Ti will form TiN. Please refer to Fig. 5. After removing the unreacted plutonium / butadiene by wet etching method, it is left in the gate and source / drain regions 14a, i8a of the first active region I. Titanium silicide 30a is a self-aligned metal silicide; at the same time, titanium silicide 30b is left on the gate 14b of the second active region II as the metal silicide gate. After that, a rapid thermal tempering at a higher temperature is performed again. , The original C49 phase TiSG is transformed into a low resistivity C54 phase TiSi2 to complete the salicide process. It can be known from the above that the process of the present invention forms a self-aligned metal silicide 30a on the logic circuit of the first active region I, which can improve its performance, and simultaneously forms a metal silicide gate on the memory circuit of the second active region II. 30b to avoid yield reduction. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling this page)
、1T 經濟部中央標準局貝工消费合作社印製 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐）， 1T Printed by Shelley Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs This paper size applies to Chinese national standards (CNS > A4 size (210X297 mm)