TWI222466B - Novel method to form a poly connector - Google Patents

Abstract

The present invention includes forming a polysilicon layer on the isolation layer, followed by etching the polysilicon layer by using an etchant that is only attacks the silicon material but stop on the isolation. Subsequently, a metal layer is formed on the patterning feature. A refractory or noble metal layer, such as Ti, Pt, Co, W, Ni, Pd, Cr etc, is formed on the isolation layer and the polysilicon. Successively, a rapid thermal process is employed at 350 to 700 degrees centigrade in N2 ambient to react the metal with the polysilicon, thereby forming silicide on the defined polysilicon. The non-reactive metal on the dielectric layer is next removed.

Description

1222466 A7 B7 V. Description of the Invention (5-1 Field of the Invention: The present invention relates to a process for an electrical connection structure, particularly an electrical connection and structure process for a metal silicide applied to an integrated circuit. 5-2 Background of the invention: In the trend of ultra-large integrated circuits, the size of semiconductor components is continuously shrinking, and the degree of accumulation is continuously increasing. After reducing the size of electronic components, it is already possible to achieve the maximum integration capability of semiconductor integrated circuits. After the reduction in size, many challenges have arisen in the manufacturing process of integrated circuits. In addition, due to the rapid development of computers and communication technology, more and more types and applications of memory are required. For example, voice operations Computer interfaces or other communication interfaces require many memory components. Therefore, the trend of integrated circuits will continue to develop towards a high degree of accumulation. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs when the appearance of components is shrinking, power consumption is reduced. The need for structural connection resistance is more important than in the past. The increase in resistance value will lead to the component operation speed due to RC. Delay and slow down. One of the proposals to solve the above problem is to replace the polycrystalline silicon material with aluminum metal. However, the melting point of aluminum metal is lower than the processing temperature of many subsequent processes, that is, it will be more than 500 degrees Celsius. Therefore, aluminum is not suitable as a substitute material. Recently, the silicided metal formed on the silicon layer is a commonly used to reduce the size of this paper. Applicable to the Chinese National Standard (CNS) M specification (210 X 297 mm) 1222466 A7 B7 V. Description of the invention () Structure or method of contact resistance. Components made by self-aligned silicided process can effectively reduce resistance and increase operation speed. The process of making silicided metal usually involves a deposition process. And a post-deposition heat treatment process, that is, a metal is deposited on the silicon layer, and then the wafer is subjected to a heat treatment process to form a metal silicide due to the reaction between the metal and the silicon. In this technical field, the CVD process can provide a comparative Good step coverage and higher capacity. A system called cold-wall system It has been very successful in the tungsten silicide process. After silicon and silicide are formed on the oxide dielectric layer, a problem arises when patterning the silicide / silicon composite structure. To synchronize the above-mentioned composite structure, Since the etchant that etches tungsten silicide will also etch oxides, it will be very difficult to control the etching to stop on the oxide layer in the process. Another method is to use different etching processes and etchant to etch tungsten silicide and Silicon layer, and the etchant that etches the silicon layer cannot etch oxides, but this method will increase costs and reduce productivity. (Please read the precautions on the back before filling this page)

A new one that is formed of siliconized silicon and is made by process.

The central government bureau of the Ministry of Economic Affairs' employee consumer cooperatives printed the general outline of the project to pass through the underlying layer of silicon in place to prevent the seed 1 ο for the process of the project belongs to Jin Minghua's silicon etched paper standard applicable China National Standard (CNS) A4 specification (210X297 mm) I222466 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7, ____B1__________ _V. Description of the invention () The invention includes the formation of a silicon dioxide layer on a substrate as MO S gate electrode oxide layer. A polycrystalline silicon layer is deposited on the silicon dioxide layer, the field oxidation region, and the substrate. A silicide metal and a cap layer or ARC are respectively formed on the polycrystalline silicon layer. The masking layer may be formed of an oxide or a nitride. Gate structures, doped regions, and other electrical connection transfer structures are then formed using conventional techniques. A sidewall gap is formed above the sidewall of the gate electrode. Subsequently, a dielectric layer as an insulation is formed on the gate structure, the field oxidation region, and the substrate. Next, a contact window (opening) is formed in the dielectric layer to expose a part of the substrate using lithography and etching techniques. A polycrystalline silicon layer is formed on the dielectric layer 'and backfilled into the contact window. . Etching the polycrystalline silicon layer forms a pattern. The etchant for this etch only etches the polycrystalline silicon without attacking the oxide, or has a high etching selectivity between the two, so that the etching will stop on the oxide layer. Subsequently, a metal layer is subsequently deposited on the diced polycrystalline silicon layer and the dielectric layer described above. For example, a refractory or noble metal can be deposited. For example, Ti, Pt, Co, W, Ni, Pd, Cr or any suitable material can be deposited on the dielectric layer and the patterning compound. Crystalline silicon layer. Ti / TiN can also be deposited as the above-mentioned metal layer. A rapid thermal tempering was performed at 350 to 700 ° C in nitrogen to react the above-mentioned polycrystalline layer and metal layer to form a silicided metal thereon. Finally, the metal not participating in the reaction is removed, and the silicided metal is aligned on the surface of the polycrystalline silicon layer. Finally, an insulating film layer is formed as a protective layer. This paper size applies to Chinese National Standard (CNS) A4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page)

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1222466 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (Circular brief description: The preferred embodiment of the present invention will be supplemented by the following figures in the following explanatory text for a more detailed explanation: First The figure is a cross-sectional view of a semiconductor wafer, used to describe the steps of forming a dream layer and a dielectric layer in the present invention. The second figure is a cross-sectional view of a semiconductor wafer, used to describe the steps of forming a metal layer in the present invention. The third figure is a cross-sectional view of a semiconductor wafer, which is used to describe the steps of performing heat treatment of the present invention. The fourth figure is a cross-section of a semiconductor wafer, which is used to describe the formation of a gate structure on a circle in the present invention. The fifth figure is a cross-sectional view of a semiconductor wafer, which is used to describe the step of forming a sidewall gap in the present invention. The sixth figure is a cross-sectional view of a semiconductor wafer, which is used to describe the formation of oxides in the present invention. The seventh figure is a cross section 圊 of a semiconductor wafer, which is used to describe the step of forming an opening in the wafer in the present invention. The eighth figure is a cross section 囷 of a semiconductor wafer, which is used to describe this step. The step of forming a polycrystalline silicon pattern in the Ming. The ninth figure is a cross-sectional view of a semiconductor wafer, which is used to describe the step of forming a metal layer in the present invention. The tenth figure is a cross-section of a semiconductor wafer, used to describe this. Steps to form Shixi compounds in the invention. This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)

1222466 A7 B7 __ 5. Description of the invention () ^ Η The figure is a cross-sectional view of a semiconductor wafer, which is used to describe the steps of forming a protective layer in the present invention. Detailed description of the invention: The present invention discloses a process for silicidating metal for forming self-aligned metal lithium oxide on the lithium layer. In the conventional technology, a metal layer is first formed on a stone layer, and then heat treatment is used to react silicon and metal, thereby forming a silicon metal, and then patterning the silicide metal and the silicon layer. As mentioned earlier, when the Shixi layer is formed on the oxide layer, it will be difficult to control the etching process or cause an increase in cost. This method will provide a new process to solve problems that are not easily overcome by tradition. The following description will be given by accompanying the drawings with examples. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs In the preferred embodiment with reference to the first figure, a semiconductor material with a crystal plane of < i 〇 〇 > is used as the substrate as an embodiment. A silicon layer 6 is formed on the oxide dielectric layer 6 on the substrate 2 as an abrasive layer for electrical conduction. The important step is to pattern the silicon layer first to make the desired pattern, as shown in the second figure. The etchant used in the above-mentioned etching process must be highly selective between silicon and oxide. This step is completely different from the traditional concept of the process, or you can use a completely unrefined oxide to attack only the name of the dream material. In one embodiment, HBr / Cl2 can be used as an etchant. Next, a metal layer is formed on the patterned silicon layer 6 and the dielectric layer 4. 6 1222466 A7 B7 V. Description of the invention () The next step is to make self-aligned petrified metal. For example, refractory metal or refractory metal (metal) can be deposited first, for example, ^ i 'Pt' C〇 '% Ni, Pd, Cr or any suitable material can be deposited on the dielectric layer 4 and the pattern fossil Evening layer 6 above. Ti / TiN can also be used as the above-mentioned metal layer. A quick heat-tempering was then performed under nitrogen at 350-700. 〇 treatment, used to react the above-mentioned silicon layer 6 and metal layer 8 to form a silicided metal 10 on top of it, and then remove the metal 8 that is not involved in the reaction, then it is self-aligned and formed on the surface of the silicon layer, so no need Any step of etching metal silicide (such as tungsten silicide) is shown in the third figure. So traditional problems can be solved without adding steps or costs. The present invention can also be used to make DRAM, 3 ”, or other components' electrical connection (ConnCotor) structures. Referring to the fourth figure, a semiconductor substrate such as P-type or N-type 'monocrystalline silicon having a crystal orientation of < 丄 〇 〇> can be used as the substrate 20, for example. An insulating region such as a field oxidation region 24 is formed on a semiconductor substrate as an insulating region between elements. Of course, under different requirements, a trench isolation area can also be used as this insulation area. The field oxidized region 24 can be formed on the substrate 20 as an insulating structure between the elements using LOCOS or other related field oxidized insulating region technology. In general, the silicon nitride and silicon oxide composite layers can be etched by lithography and etching techniques, and then a field oxide layer 24 is formed on the substrate 20 by a chemical process. After the completion, the above silicon nitride layer is removed by hot phosphoric acid, and the silicon oxide layer is removed by hydrofluoric acid. The thickness of the field oxidation region 24 is about 3000-8000 angstroms. This paper is again applicable to China National Standard (CNS) A4 (210x297 mm) (please read the notes on the back before filling out this page) 4 Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 1222466 Central Standards Bureau of the Ministry of Economic Affairs Printed by employee consumer cooperative A7 _B7_ V. Description of the invention () Next, a silicon dioxide layer 26 is formed on the substrate 20 as a gate oxide layer of the MOS transistor. The silicon dioxide layer 2 6 is generally formed by a thermal oxidation method. The process temperature is about 800 to 1100C and the thickness is about 20 to 200 angstroms. Of course, general technology such as chemical vapor deposition uses TEOS as the reactant, and the process temperature is about 600 to 800 ° C, and the pressure is about 1 to 10 Torr to form the silicon dioxide layer 26. A conductive layer 28 is deposited on the silicon dioxide layer 2.6, the field oxide region 24, and the substrate 20. According to an embodiment, the conductive layer 28 is preferably formed by using a polycrystalline silicon layer 28 using a chemical vapor deposition (CVD) method. Other metals or alloys can be used under appropriate conditions. A silicide metal 30 and a cap layer or ARC 34 are formed on the polycrystalline silicon layer 28, respectively. The cover layer 34 may be formed of an oxide or a nitride. A TEOS oxide layer 32 may be provided between the silicide metal 30 and the cover layer 34 to eliminate the stress therebetween. Gate structures 36, doped regions, other electrical connection transfer structures 38, etc. are then formed using conventional techniques. Referring to the fifth figure, after completing the gate structure 36, a sidewall gap 40 is formed on the sidewall of the gate. Subsequently, referring to FIG. 6, a dielectric layer 42 as an insulation layer is formed on the gate structure 36, the field oxidation region 24, and the substrate 20 described above. In a preferred embodiment, the dielectric layer 42 is preferably an undoped TEOS emulsion or a similar material. Next, a 'opening 44' is formed in the dielectric layer 42 to expose a portion of the substrate 20 using lithography and etching techniques. In other words, the contact window 44 exposes the doped region of the transistor. (Please read the precautions on the back first

Order

This paper size applies to the Chinese National Standard (CNS) A4 specifications (210X297 public directors) 1222466 A7 B7 V. Description of the invention () No less than the seventh figure. As shown in FIG. 8 ', the first conductive layer 46 is formed on the dielectric layer 42 and is filled back into the contact window 44. The first conductive layer 46 is preferably composed of doped polysilicon or in-situ doped polysilicon. In a preferred embodiment, the first The conductive layer 46 is formed using a low pressure chemical vapor deposition (LPCVD) method to a thickness of about 1000 to 1500 angstroms. The first step is to form a photoresist pattern (not shown) on the first conductive layer 46. Generally, the photolithography process can be used to achieve the above purpose. The photoresist is used as a mask to etch the polycrystalline stone layer 46 to form a pattern. The last name of the # 刻 之 刻刻 剂 only engraved polycrystalline stone without attacking the oxide, or there is a high etching selectivity between the two, so that the etching will stop on the oxide layer 42. The Vss line and the landing pad are thus defined. Subsequently, a metal layer 48 is then deposited on the patterned polycrystalline silicon layer 46 and the dielectric layer 42 described above. For example, a refractory metal or a refractory metal can be deposited. For example, Ti, Pt, Co, W, Ni, Pd, Cr or any suitable material can be deposited on the dielectric layer 42 and patterned. Above the polycrystalline silicon layer 46. It is also possible to deposit Ti / TiN as the aforementioned metal layer 48 'as shown in the ninth figure. Refer to the tenth figure, perform a rapid thermal tempering in nitrogen at 350 to 700 ° C, which is used to reflect the polycrystalline layer 46 and metal layer 48 described above to form silicified paper. This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) One f: -Old- # one! · Three T.H -τ χΙ.ΓThree T.H.

Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 1222466 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description () Metal 50 is on it. Finally, the non-reactive metal 48 is removed, and the silicided metal 50 is aligned on the surface of the polycrystalline silicon layer by itself. Therefore, it does not require any step of etching the metal silicide such as tungsten silicide. Finally, an insulating film layer 52 is formed on the above structure as a protective layer, as shown in FIG. The present invention can obtain many advantages. For example, the element of the present invention accelerates the operation speed because of self-alignment of the lithium oxide, the gate resistance can be reduced due to the lithium oxide, and the etching of the oxide due to over-etching can be avoided. Simple, no extra cost. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention. Any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patents. 10

Claims (1)

The consumer property cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed 1222466 A8 B8 C8 D8 t, and applied for the scope of patent 6. If the method of the scope of patent application No. 1 is applied, the above thermal process is performed in an environment containing nitrogen. 7. The method of claim 1, wherein the second polycrystalline silicon layer is used to form a supporting pad on the dielectric layer. 8. The method according to item 1 of the patent application, wherein the above-mentioned metal layer comprises W 009. The method according to item 1 of the patent application, wherein the above-mentioned metal layer comprises TiN / Ti. 10. The method of claim 1 in which the above-mentioned metal layer contains Ti. 1 1. The method according to the scope of patent application, wherein the above-mentioned metal layer comprises Pt 〇 2. The method according to the scope of patent application, wherein the above-mentioned metal layer comprises C 〇 03. The method of item 1, wherein the metal layer includes Ni. This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) nnnnnnnnnn · It nnnunn I-0, I nnnnnnn I (Please read the precautions on the back before filling this page) 1222466 A8 B8 C8 D8 Patent application range 14. The method as claimed in item 1 of the patent range, wherein the above-mentioned metal layer contains Pd 015. As described above, the method as claimed in the claim 1, wherein the metal layer includes Cr. 16. A method of forming a conductive connection structure, the method includes: forming a gate electrode on a substrate; and the substrate is provided with a plurality of field oxidation regions; forming a dielectric layer on the substrate; Forming an opening in the dielectric layer to expose the doped region of the gate; forming a polycrystalline silicon layer over the dielectric layer and backfilling the opening Medium; etching the polycrystalline layer, the etchant for etching the polycrystalline silicon layer has an etching rate higher than that of the dielectric layer, and is used to form a carrier pad on the dielectric layer; forming a metal layer on the polycrystalline layer On the broken layer; performing a thermal process to react the polycrystalline silicon layer and the metal layer to form a silicided metal on the surface of the polycrystalline silicon layer; and removing the metal layer not participating in the reaction. 17. The method according to item 16 of the scope of patent application, wherein the above-mentioned dielectric layer contains an oxidized emission. 18 · The method according to item 16 of the scope of patent application, wherein the above-mentioned dielectric layer is formed using TEOS. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling out this page) -I 1 II 1 II «— — 111 — — — 1 ^ Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative-ϋ ϋ 1 · n ϋ nn ϋ nnnnn I ϋ nnnnu I The method according to item 16, wherein the above-mentioned etchant comprises HBr / Cl2 0 2 0. The method according to item 16 of the patent application scope, wherein the above-mentioned thermal process is about 350 to 700 ° C. 2 1 · The method according to item 16 of the scope of patent application, wherein the above thermal process is performed in an environment containing nitrogen. 2 2 · The method of claim 16 in the scope of patent application, wherein the second polycrystalline silicon layer is used to form a supporting pad on the dielectric layer. 23. The method according to item 16 of the patent application, wherein the aforementioned metal layer contains W 24. The method according to item 16 of the patent application, wherein the aforementioned metal layer comprises TiN / Ti. 25. The method according to item 16 of the patent application, wherein the above-mentioned metal layer contains Ti. 26. The method according to item 16 of the scope of patent application, wherein the above-mentioned metal layer includes P t 〇 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) _ n ill ln I— n I 丨····· IBIM aw 丨 · (Please read the precautions on the back before filling in this page) 1222466 A8 B8 C8 D8 The scope of patent application for the scope of gold is described in the above paragraph of its legal method 6 1X Please " φ- 〇 口 ο Taxi C 2 Including the cladding metal in the description of its method 6 rH No. Fan Li special application for 8 2 Ν In the cladding metal is the description of its method Item 6 of the IX Fan Fan special offer φ, 〇 Such as 2 9 2 Covered gold description of the French method of the item 6 IX of the Fan Fu special request. Such as cr ο) 3 Contains ▼ mum I— imn a w ·· * ·· > * »·· im ··· 丨 丨 (Please read the precautions on the back before filling this page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Consumer Cooperatives 5 This paper is sized for China National Standard (CNS) A4 (210 X 297 mm)