JP3127908B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device having a high operation speed.

[0002]

2. Description of the Related Art Conventionally, as a prior art of a semiconductor device in which a capacitor using a high melting point metal is used for both an upper electrode and a lower electrode for high-precision capacitance, Japanese Patent Application Laid-Open No. 6-33411 has been disclosed.
No. 8 discloses a technique disclosed in Japanese Patent Publication No. This is one in which an HTO film for a capacitor insulating film is formed after forming a gate electrode. In this conventional example, T is applied to both the gate electrode and the diffusion layer.
Although the iSi layer was not formed, in the latest semiconductor process, TiS was not formed on both the gate electrode and the diffusion layer.
An i layer is formed to reduce the resistance of the gate electrode and the resistance of the diffusion layer.

The lowering of the resistance of the gate electrode and the resistance of the diffusion layer depends on the performance required of the semiconductor device, and the performance required of the semiconductor device is increasing year by year. In particular, the required operation speed of a logic semiconductor device is increasing year by year. For example, the operating frequency of a central processing unit (hereinafter, referred to as "CPU") used in a personal computer (hereinafter, referred to as "PC") was about 100 MHz a few years ago. However, at present 333 MHz and sometimes 450 MH
z, and increasing the speed of the semiconductor device is an important issue.

The operating speed of the semiconductor device is restricted by the resistance and the capacitance in the CPU circuit. The operating speed can be increased by reducing the so-called parasitic resistance and parasitic capacitance. Generally, the parasitic resistance can be reduced by lowering the resistance of the gate electrode and the resistance of the diffusion layer. For this reason, the latest semiconductor manufacturing process employs a process of forming a TiSi layer on both a gate electrode and a diffusion layer.

[0005]

However, each of the above-mentioned prior arts has the following disadvantages. That is, predetermined heat treatment is performed in the course of the semiconductor manufacturing process. Here, the TiSi layer has a drawback that the resistance increases when a high-temperature heat treatment is applied for a long time. In particular,
It cannot withstand a heat treatment of about 800 ° C. for about one hour applied during the formation of the HTO film for the capacitive insulating film. Therefore, the capacitance forming method as in the conventional example has a disadvantage that the resistance of the TiSi layer increases, thereby increasing the resistance of the gate electrode and the resistance of the diffusion layer, thereby lowering the operation speed of the semiconductor device.

The mechanism by which the resistance of a TiSi layer is increased by a long-time heat treatment at a high temperature is as follows. That is, the TiSi layer undergoes a phase transition due to a high-temperature heat treatment, and when this phase transition occurs, aggregation is likely to occur. The phenomenon of agglomeration is that the TiSi layer that had been formed uniformly until then breaks up into several pieces, and a portion where the TiSi layer is not formed is formed. Agglomeration is more likely to occur as the width of the TiSi film becomes smaller, and it is expected that this will become more and more problematic as the width of the semiconductor wiring becomes finer. When the cohesion occurs, the TiSi layer is not formed partially, so that TiSi
By increasing the resistance in the area where no layer is formed, C
The resistance of the entire PU circuit rises.

In the process including the formation of the TiSi layer, the heat treatment after the formation of the TiSi layer is minimized in order to prevent the above-mentioned problem. To TiS
It had to be brought before the step of forming the i-layer.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of improving the disadvantages of the conventional example and, in particular, manufacturing a semiconductor device having a high operating speed by simple steps. And

[0009]

In order to achieve the above object, according to the present invention, a step of forming a field oxide film at a predetermined position of a MOS transistor forming region on a semiconductor substrate is provided. NchM
Forming a P-well in the OS transistor formation region and forming an N-well in the PchMOS transistor formation region, sequentially stacking a gate oxide film and a polysilicon film on the MOS transistor formation region and the field oxide film; A step of sequentially laminating a first metal layer, an insulating film, and a second metal layer on a polysilicon film for forming a capacitance, and a step of applying a first photoresist to a capacitance formation region in the second metal layer Removing the first metal layer, the insulating layer, and the second metal layer other than the capacitance forming region by etching; removing the first photoresist in the capacitance forming region; Applying a second photoresist around the gate electrode formation region, the capacitance formation region, and the periphery of the capacitance formation region of the MOS transistor; And removing the polysilicon film in a region other than the second photoresist by etching, and thereafter, and a step of removing the second photoresist, it adopts a method called. By employing the above method, in the present invention, since the formation of the capacitor electrode is performed before the formation of the gate electrode, it is possible to form the capacitor electrode in a flat state without any step of the gate electrode. Since there is no need to perform extreme over-etching without being affected by the etching residue in the portion, stable etching of the capacitor electrode is facilitated.

Further, according to the present invention, an HTO for a capacitor insulating film is provided.
Since the film is formed before the formation of TiSi, an increase in the resistance of the TiSi layer on the gate electrode and the diffusion layer can be suppressed, and a decrease in the operation speed of the semiconductor device can be suppressed.

[0011]

An embodiment of the present invention will be described with reference to the drawings. The features of the present invention will be described with reference to FIGS.

FIG. 1A shows that a P well 5 and an N well 7 are formed in a substrate 3 constituting a semiconductor device 1, and a field oxide film 9 is formed on the boundary region between the P well 5 and the N well 7. This shows the formed state. Next, FIG.
As shown in FIG. 2B, after forming the gate oxide film 11, a polysilicon film 13 for a gate electrode is formed. Here, the polysilicon film 13 is doped with phosphorus or the like during the formation to reduce the resistance. Next, a first metal layer (for example, a refractory metal layer made of WSi) 15 for a capacitor lower electrode is formed on the polysilicon film 13. This high melting point metal layer 15
An HTO film 17 for a capacitor insulating film is formed thereon, and a second metal layer (for example, a refractory metal layer made of WSi) 19 for a capacitor upper electrode is formed thereon.

Next, as shown in FIG. 2C, alignment is performed so that the first photoresist 21 remains only in the capacitance forming portion, and exposure and development are performed. Next, as shown in FIG. 2D, using the first photoresist 21 as a mask,
Capacitance in capacitance forming portion Second metal layer 1 for upper electrode
9. The HTO film 17 for the capacitor insulating film and the first metal layer 15 for the capacitor lower electrode are sequentially etched. At this time, the polysilicon film 13 for the gate electrode is left.

Next, as shown in FIG. 3E, after removing the first photoresist 21 remaining in the capacitance forming portion, the gate electrode forming portion, the capacitance forming portion, and the lower portion of the MOS transistor are removed. Exposure and development are performed by aligning the second photoresist 23 so that the second photoresist 23 remains in the electrode lead portion of the electrode. Next, as shown in FIG. 3F, using the second photoresist 23 as a mask, the polysilicon film 13 for the gate electrode is removed by etching, and the gate electrode lead-out portion 25 of the MOS transistor and the capacitor are removed. An electrode lead portion 27 for the lower electrode is formed.

According to the present invention, as described above, the formation of the capacitor electrode is performed before the formation of the gate electrode, and the electrode leading portion 27 of the capacitor lower electrode is formed by the gate electrode. Further, the present invention has a feature that the capacitance can be formed only by adding one step to the basic process of semiconductor manufacturing.

A specific embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 4A, a field oxide film 9 is formed in an insulating isolation region other than the diffusion layer region. Thereafter, a P well 5 is formed in the NchMOS transistor formation region by ion implantation, and an N well 7 is formed in the PchMOS transistor formation region.

Next, as shown in FIG. 4B, a gate oxide film 11, a polysilicon film for the gate electrode (which is doped with phosphorus or the like to reduce the resistance during the formation) 13, and a film for the capacitor lower electrode A first metal layer (for example, a refractory metal layer made of WSi) 15, an HTO film for a capacitor insulating film (a heat treatment at 800 ° C. for about 1 hour is applied at the time of forming the HTO film) 17, a second for a capacitor upper electrode A metal layer (for example, a refractory metal layer made of WSi) 19 is formed sequentially.

Next, as shown in FIG. 5C, alignment is performed so that the first photoresist 21 remains only in the capacity forming region, and exposure and development are performed thereon. Next, as shown in FIG. 5D, using the first photoresist 21 as a mask, the refractory metal layer 19 for the capacitor upper electrode, the HTO film 17 for the capacitor insulating film, and the high melting point metal for the capacitor lower electrode. The melting point metal layer 15 is sequentially etched and removed, leaving the polysilicon film 13 for the gate electrode.

Next, as shown in FIG. 6E, after removing the first photoresist 21 for forming a capacitor, the MOS
The second photoresist 23 is aligned so as to remain in the gate electrode forming portion 25 of the type transistor, the capacitor forming region, and the electrode lead portion 27 of the capacitor lower electrode, and exposure and development are performed.

Next, as shown in FIG. 6F, using the second photoresist 23 as a mask, the polysilicon film 13 for the gate electrode is removed by etching, and the gate electrode lead portion 25 of the MOS transistor is removed. An electrode lead portion 27 for the lower electrode of the capacitor is formed. Next, as shown in FIG. 7 (g), an N ⁻ diffusion layer 29 is formed on the diffusion layer in the NchMOS transistor formation region by ion implantation, and the Pch
P ⁻ diffusion layer 3 is used as the diffusion layer in the MOS transistor formation region.
Form one.

Next, as shown in FIG. 7H, an oxide film side wall 33 is formed on the side walls of the gate electrodes 32a and 32b. As a method of forming the oxide film sidewall 33, an oxide film is formed on the entire surface, and anisotropic oxide film dry etching is performed. At this time, the oxide film sidewall 35 is also formed on the side wall of the capacitor electrode. . Next, an N ⁺ diffusion layer 37 is formed in the diffusion layer in the NchMOS transistor formation region by ion implantation, and a P ⁺ diffusion layer 39 is formed in the diffusion layer in the PchMOS transistor formation region. At this time, the gate electrode 32a of the NchMOS transistor is N
⁺ Polysilicon, and the gate electrode 32b of the PchMOS transistor becomes P ⁺ polysilicon.

Next, as shown in FIG. 8 (i), after removing the oxide films on the gate electrodes 32a, 32b and the respective diffusion layers 31, a Ti film is formed on the entire surface, and a heat treatment at about 700 ° C. is performed. Add about a minute. Thereby, the gate electrodes 32a, 3
2b and the silicon of each diffusion layer 31 react with the Ti film to form an alloy, and a TiSi layer 41a is formed on the gate electrodes 32a and 32b and each diffusion layer 31. At this time, the TiSi layer 41 is also provided in the electrode lead portion 27 of the lower capacitor electrode.
b is formed. Thereafter, the TiSi layers 41a, 41b
The Ti in the other region where is not formed is removed with a mixed solution of aqueous ammonia and hydrogen peroxide.

Next, as shown in FIG. 8 (j), after the interlayer insulating film 43 is formed, the interlayer insulating film 43 is planarized by using chemical mechanical polishing (hereinafter referred to as "CMP"). After that, a contact plug (for example, formed of a W layer) 45 is formed after opening the contact via.

Next, as shown in FIG. 9K, a first aluminum wiring 47 is formed. Next, as shown in FIG. 9 (l), after the aluminum wiring interlayer film 49 is formed, the aluminum wiring interlayer film 49 is flattened using CMP or the like, and a via plug (formed of, for example, a W layer) is formed after opening the via hole. 51 are formed, and the second aluminum wiring 53 is formed. Through the steps described above, the semiconductor device 1 including the capacitance formation of the present invention is formed.

[Explanation of Function] In the present invention, as shown in FIGS. 4 to 9, the capacitor electrode is formed before the gate electrode is formed, and as shown in FIG. The formation of the electrode lead portion is performed simultaneously with the formation of the gate electrode. Further, as shown in FIG. 7H, when the oxide film sidewall is formed on the side wall of the gate electrode, the oxide film sidewall is simultaneously formed on the side wall of the capacitor electrode.
Good insulation is obtained between the capacitor upper electrode and the capacitor lower electrode.

As shown in FIG. 8 (i), when the TiSi layer is formed on the gate electrode and the diffusion layer, the TiSi layer is also formed on the electrode lead-out portion of the capacitor lower electrode. The resistance of the lead portion can also be reduced.

Further, as shown in FIG. 8 (j), the contact opening of the capacitor upper electrode and the capacitor lower electrode can be simultaneously performed at the time of the normal contact opening, so that an additional process for forming the contact for the capacitor electrode is not required.

[0028]

According to the present invention, since the formation of the capacitor electrode is performed before the formation of the gate electrode, the capacitor electrode can be formed in a flat state without any step of the gate electrode, and the etching residue at the step portion can be obtained. It is not necessary to perform an extreme over-etching without being affected by the above, so that stable etching of the capacitor electrode becomes easy.

Further, according to the present invention, an HTO for a capacitor insulating film is used.
Since the film is formed before the formation of TiSi, an increase in the resistance of the TiSi layer on the gate electrode and the diffusion layer can be suppressed, and a decrease in the operation speed of the semiconductor device can be suppressed. Produces an effect.

[Brief description of the drawings]

FIG. 1 is a view showing a process of a manufacturing method according to an embodiment of the present invention, and FIG. 1A shows a state in which a field oxide film, a P well and an N well are formed, and FIG.
Indicates a state in which each metal layer and an insulating layer for forming a capacitor are formed.

FIG. 2 is a view showing a process of a manufacturing method following FIG. 1; FIG. 2 (c) shows a state in which a photoresist is applied to a capacity forming region; FIG. 2 (d) shows a state in which a metal layer and an insulating layer are formed; , Respectively, are shown.

FIG. 3 is a view showing a process of a manufacturing method following FIG. 2; FIG. 3 (e) shows a state in which a photoresist is applied to a gate electrode formation region and a capacitance formation region; FIG. 3 (f) shows polysilicon; The state after removing the film is shown.

FIG. 4 is a diagram showing a specific embodiment of the present invention, and FIG.
4A shows a state in which a field oxide film, a P well and an N well are formed, and FIG. 4B shows a state in which each metal layer and an insulating layer for forming a capacitance are formed.

FIG. 5 is a view showing a process of a manufacturing method following FIG. 4; FIG. 5 (c) shows a state in which a photoresist is applied to a capacity forming region; FIG. 5 (d) shows a state in which a metal layer and an insulating layer are formed; , Respectively, are shown.

6 is a view showing a process of a manufacturing method following FIG. 5; FIG. 6 (e) shows a state where a photoresist is applied to a gate electrode formation region and a capacitance formation region; FIG. 6 (f) shows polysilicon; This shows a state where the film has been removed.

FIG. 7 is a view showing a process of a manufacturing method following FIG. 6; FIG. 7 (g) shows a state where the photoresist is removed; and FIG. 7 (h) shows a state where an oxide film sidewall is formed. Shown respectively.

8 is a view showing a process of a manufacturing method following FIG. 7; FIG. 8 (i) shows a state in which a TiSi layer is formed by heating; and FIG. 8 (j) shows a state in which an interlayer insulating film is formed. Show.

FIG. 9 is a view showing a process of a manufacturing method following FIG. 8; FIG. 9 (k) shows a state in which a first aluminum wiring is formed on an interlayer insulating film; The state where the second aluminum wiring is formed on the aluminum wiring interlayer film on the insulating film is shown.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor device 3 Substrate 5 P well 7 N well 9 Field oxide film 11 Gate oxide film 13 Polysilicon film 15 First metal layer (high melting point metal layer) 17 Capacitive insulating film (HTO film) 19 Second metal layer ( High melting point metal layer) 21 First photoresist 23 Second photoresist 25 Gate electrode lead portion 27 Capacitor lower electrode lead portion 29 N ^- diffusion layer 31 P ^- diffusion layer 32a Gate electrode 32b Gate electrode 33 Oxide film sidewall 35 Oxide film sidewall 37 N ⁺ diffusion layer 39 P ⁺ diffusion layer 41 a TiSi layer 41 b TiSi layer 43 interlayer insulating film 45 contact plug 47 first aluminum wiring 49 aluminum wiring interlayer film 51 via plug 53 second aluminum wiring

Continuation of the front page (56) References JP-A-9-36313 (JP, A) JP-A-8-274257 (JP, A) JP-A-6-334118 (JP, A) JP-A-7-273281 (JP, A) JP-A 9-139479 (JP, A) JP-A 8-139283 (JP, A) JP-A 10-74894 (JP, A) JP-A 4-278537 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822

Claims (7)

(57) [Claims] A step of forming a field oxide film at a predetermined portion of a MOS transistor forming region on a semiconductor substrate;
Forming a P-well in the OS transistor formation region and forming an N-well in the PchMOS transistor formation region, sequentially stacking a gate oxide film and a polysilicon film on the MOS transistor formation region and the field oxide film; A step of sequentially laminating a first metal layer, an insulating film and a second metal layer on the polysilicon film for forming a capacitor, and applying a first photoresist to a capacitor forming region in the second metal layer. Removing the first metal layer, the insulating layer, and the second metal layer other than the capacitance forming region by etching; removing the first photoresist in the capacitance forming region; A second region is formed in a predetermined region of the polysilicon film around the gate electrode formation region of the MOS transistor, the capacitance formation region, and the periphery of the capacitance formation region. A step of applying a photoresist, a step of removing a polysilicon film in a region other than the second photoresist by etching, and a step of removing the second photoresist thereafter. A method for manufacturing a semiconductor device. 2. The method according to claim 1, wherein each of the metal layers is made of WSi. 3. The method according to claim 1, wherein the polysilicon film is a P-doped film. 4. After removing the second photoresist,
NchMOS in the MOS transistor forming region
Forming an N ⁻ diffusion layer around the transistor formation region by ion implantation, forming a P ⁻ diffusion layer around the PchMOS transistor formation region, forming a side wall of the gate electrode formed in the gate electrode formation region, and forming the capacitance forming oxide film sidewall on the sidewall of the capacitance formed in a region, the N ^- a step of the N ⁺ diffusion layer by ion implanting the peripheral portion of the diffusion layer, the P ^- peripheral diffusion layer Forming a P ⁺ diffusion layer by ion implantation, removing the oxide film sidewalls, forming a Ti film on the entire surface of the semiconductor device, and heating the semiconductor device at a predetermined temperature. 4. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a TiSi layer in a predetermined region and a step of removing a remaining Ti film. 5. The method according to claim 4, wherein the formation of the TiSi layer is performed by heating at a temperature of 600 to 700 ° C. for 1 to 5 minutes. 6. The method for manufacturing a semiconductor according to claim 4, wherein the removal of the Ti film is performed using a mixed solution of aqueous ammonia and hydrogen peroxide. 7. A step of covering the surface of the semiconductor device with an interlayer insulating film after removing the Ti film, a step of forming a contact plug at a position of the interlayer insulating film corresponding to the gate electrode, and forming the capacitor. Forming a contact plug in a capacitor electrode lead-out portion formed in a peripheral portion of the region, and forming a first aluminum wiring on the interlayer insulating film for electrically connecting the corresponding contact plugs to each other; A step of forming an aluminum wiring interlayer film on the interlayer insulating film; a step of forming a via plug connected to the first aluminum wiring in the aluminum wiring interlayer film; 7. A method of manufacturing a semiconductor device according to claim 4, wherein a second aluminum wiring for electrically connecting via plugs to be formed is formed on said aluminum wiring interlayer film. Law.