448979 Λ7 經濟部中央標準局員工消費合作社印製 B7 五、發明説明（1 ) 本發明是有關於一種自我對準接觸窗之製程，且特別 是有關於一種免增光罩可整合金屬碎化物與自我對準接觸 窗之製程。 一般的邏輯產物已經在閘極以及源極/汲極上利用自 我對準矽化物（例如：矽化鈦）製程來獲得具有高效率的邏 輯電路；而自我對準接觸窗（self-alignment contact ; SAC) 則已被廣泛地用來節省記憶胞的尺寸。若自我對準矽化物 製程以及自我對準接觸窗製程可被整合在一起，則可得到 同時具有高邏輯效率以及高密度記憶容量的半導體元件。 故本發明針對此構想，提出一種免增光罩可整合金屬 矽化物與自我對準接觸窗的製程，其步驟包括：提供一包 含邏輯區以及記憶區之半導體基底，其中該邏輯區以及該 記憶區並分別包含至少有一MOS >且該MOS包含一閘極、 一源極/汲極，以及一位於該閘極上方供定義閘極用的保護 層以及硬罩幕層，其中在該閘極結構兩侧更含有一侧壁 子；形成一第一絕緣層於該邏輯區以及該記憶區之表面； 形成一下光阻層於該第一絕緣層上；形成一上光阻層於該 記憶區中之該下光阻層上；去除該邏輯區中位在該保護層 以上區域之該下光阻層、該第一絕緣層、該硬罩幕層以及 部分該側壁子；去除該邏輯區_之該保護層；去除該邏輯 區内殘餘的下光阻層以及該源/汲極上之第一絕緣層；去除 該記憶區内之該上光阻層及下光阻層；在該邏輯區中之 MOS之閘極以及該源極/汲極表面分別形成一自我對準财 熱金屬矽化物；以及形成一第二絕緣層於該邏輯區以及該 ----------^------'訂------^ 1 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ29?公釐） 4 489 7 9 A7 B7 經濟部中央標準局*；工消費合作社印裝 五、發明説明（2 ) 記憶區表面，並在該記憶區内形成一自我對準接觸開口， 裸露出該源極/汲極之基底表面。 為讓本發明更淺顯易僅，玆將配合實施例以及相關的 圖示於後作詳細說明。 圖式之簡單說明： 第1A〜1E圖是剖面示意圖，顯示的是根據本發明之尤 摩龙孑可整合金屬矽化物與自我對準接觸窗製程。 符號說明： 10 半導體基底 11 複晶矽閘極 14 氧化矽保護層 16 氮化矽硬罩幕層 18 源極/汲極 20 側壁子 22，30 二氧化矽層 24 下光阻層（Bottom Photo resist) 24a 位在邏輯區内的殘餘光阻層 · 24b 位在記憶區内的殘餘光阻層 26 上光阻層 28a 複晶矽閘極上之自我對準矽化物 28b 源極/汲極上之自我對準矽化物 32 自我對準接觸窗 34 導電層 100 邏輯區 ---------装------訂------線1 c請先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨OX297公釐） 4 4897 9 Λ7 B7 五、發明説明（3 ) 110 記憶區 實施例： 首先，請參照第1A圖，提供一半導體基底10，其上 並包含形成有MOS之邏輯區100，以及記憶區110。其中 MOS是由複晶矽閘極12，以及位於閘極12兩側下方之源 極/汲極18，且更包括一位於閘極12上方保護閘極12用 的二氧化矽保護層14以及定義用的氮化矽硬罩幕16，其 中在閘極12/二氧化矽保護層14/氮化矽硬罩幕16所形成 之結構兩側更含有一二氧化矽側壁子20。然後，利用習知 的製程技術在邏輯區100以及記憶區110之基底以及MOS 表面沉積一二氧化矽層22。接著，形成一下光阻層（Bottom photo resist ; BPR) 24於二氧化矽層22上；其中該B ARC 層2 4之材質是一種對光、有機溶劑以及光阻顯影劑均不反 應性的材質，其通式如下所示： R1 R2448979 Λ7 Printed by the Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, B7 V. Description of the invention (1) The present invention relates to a process for self-aligning contact windows, and in particular, to a non-light-enhancing mask that can integrate metal fragments and self The process of aligning the contact window. General logic products have used self-aligned silicide (eg, titanium silicide) processes on the gate and source / drain to obtain high-efficiency logic circuits; and self-alignment contact (SAC) It has been widely used to save the size of memory cells. If the self-aligned silicide process and the self-aligned contact window process can be integrated together, a semiconductor device having both high logic efficiency and high density memory capacity can be obtained. Therefore, the present invention is directed to this idea, and proposes a process for integrating a metal silicide and a self-aligned contact window without a light-enhancing mask. The steps include: providing a semiconductor substrate including a logic region and a memory region, wherein the logic region and the memory region And each includes at least one MOS > and the MOS includes a gate, a source / drain, and a protective layer and a hard cover layer above the gate for defining the gate, wherein the gate structure A sidewall is further formed on both sides; a first insulating layer is formed on the surface of the logic region and the memory region; a lower photoresist layer is formed on the first insulating layer; an upper photoresist layer is formed in the memory region On the lower photoresist layer; removing the lower photoresist layer, the first insulating layer, the hard cover curtain layer, and part of the sidewalls in the logic region above the protective layer; removing the logic region The protective layer; removing the remaining lower photoresist layer in the logic region and the first insulating layer on the source / drain; removing the upper photoresist layer and the lower photoresist layer in the memory region; Gate of MOS and the source / A self-aligned hot metal silicide is formed on the drain surface respectively; and a second insulating layer is formed on the logic region and the ---------- ^ ------ 'order --- --- ^ 1 (Please read the notes on the back before filling out this page) This paper size applies to Chinese National Standard (CNS) Α4 size (210 × 29? Mm) 4 489 7 9 A7 B7 Central Bureau of Standards, Ministry of Economic Affairs *; Consumption cooperative printing 5. Description of the invention (2) The surface of the memory area, and a self-aligned contact opening is formed in the memory area, exposing the substrate surface of the source / drain. In order to make the present invention more obvious, the embodiments and related figures are described in detail later. Brief description of the drawings: Figures 1A to 1E are schematic cross-sectional views showing the process of integrating a metal silicide and a self-aligned contact window according to the present invention. Explanation of symbols: 10 semiconductor substrate 11 polycrystalline silicon gate 14 silicon oxide protective layer 16 silicon nitride hard cover curtain layer 18 source / drain 20 sidewall 22, 30 silicon dioxide layer 24 bottom photo resist layer ) Residual photoresistor layer 24a in the logic area. 24b Residual photoresistor layer in the memory area 26. Photoresist layer 28a. Self-aligned silicide 28b on the polysilicon gate. Self-alignment on the source / drain. Quasi-silicide 32 Self-aligned contact window 34 Conductive layer 100 Logic area ------------------------- Order line 1 c Please read the precautions on the back first (Fill in this page) This paper size is in accordance with Chinese National Standard (CNS) A4 specification (2 丨 OX297 mm) 4 4897 9 Λ7 B7 V. Description of the invention (3) 110 Memory area example: First, please refer to Figure 1A, provide A semiconductor substrate 10 includes a logic region 100 on which a MOS is formed, and a memory region 110. The MOS is composed of the compound silicon gate 12 and the source / drain 18 located below both sides of the gate 12, and further includes a silicon dioxide protection layer 14 for protecting the gate 12 above the gate 12 and a definition. The silicon nitride hard mask 16 is used, and a silicon dioxide sidewall 20 is further included on both sides of the structure formed by the gate 12 / silicon dioxide protective layer 14 / silicon nitride hard mask 16. Then, a silicon dioxide layer 22 is deposited on the substrate of the logic region 100 and the memory region 110 and the surface of the MOS by using a conventional process technology. Next, a photoresist layer (Bottom photo resist; BPR) 24 is formed on the silicon dioxide layer 22; the material of the BARC layer 24 is a material that is non-reactive to light, organic solvents, and photoresist developers. The general formula is as follows: R1 R2
N ---------d------訂------線ί _ ' (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 例如商業上可獲得的BARLi ， XHRi-11或是 SWK365D等均可用來作為下光阻層24之材質，且其可利 用光阻塗佈機塗佈，然後再加以軟烤，便可在二氧化矽層 22上形成一下光阻層24。此外，殘餘的下光阻層24可在 去除曝光過的光阻時一同被去除，在操作上相當方便，並 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X2S»7公#_ ) 經濟部中央標準局員工消費合作社印繁 4 4897 9 at B7五、發明説明（4 ) 不需要添加額外的設備以及技術。接著，在下光阻層24 形成後，便以習知的微影程序在記憶區110的下光阻層24 上形成一上光阻層26。 其次，請參照第1B圖，利用N2/02構成的離子源進行 乾式回蝕刻，去除邏輯區100中未被光阻層26覆蓋的部分 下光阻層24，直至二氧化矽層22及氮化矽層16暴露出下 光阻層24。然後，用習知方法去除邏輯區100中的二氧化 石夕層22，接著再巧F base之chemistry去除定義閘極12用 的氣化石夕硬罩幕層16。 之後，先以習知技術去除邏輯區1〇〇中的MOS源極/ 汲極18上方的二氧化矽保護層14，然後再去除邏輯區100 以及記憶區110内所有殘餘的下光阻層24a、24b，以及 上光阻層26。 請參照第1C圖，再以習知的濺鍍製程將耐熱金屬， 例如金屬鈦/氮化矽濺鍍到邏輯區100表面，然後先施一第 一段快速熱退火處理，使金屬鈦與裸露的複晶矽反應，然 後去除未與矽反應的金屬鈦/氮化鈦，並再施予第二段的快 速熱退火處理，在邏輯區1〇〇之複晶矽閘極12以及源極/ 汲極18上之矽基底表面分別形成一自我對準的金屬矽化 物28a以及28b，以增加邏輯區100之邏輯效率。- 然後，請參照第1D圖，在第1C圖所示之結構表面形 成一由二氧化矽所構成之絕緣層30，並在記憶區110中的 電容器或是位元線之預定形成處定義出一自我對準的接觸 開口（self-alignment contact ; SAC) 32，裸露出一源極/沒 ---------A------ΐτ------'t (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印裝 44897 9 Λ7 —— _______ Β7 五、發明説明（5 ) 極18之基底表面。 最後’請參照第1E圖，在開口 32位置形成一由金屬 或複晶矽所構成之經定義的導電層34，可作為記憶區110 中的電容器下層電極或是位元線。 藉此’根據本發明所提出之免增光罩可整合金屬矽化 物與自我對準接觸窗製程，在邏輯區中利用对熱金屬 一鈦與複晶矽閘極12以及源極/汲極18中的複晶矽反應， 產生自我對準矽化鈦28a、28b，可使邏輯電路1〇〇具有 較高的效率。另外，利用本發明所提出之製程，更可在記 憶區110中形成可作為電容器下層電極或是位元線之自我 對準接觸窗32，以製作出高密度記憶胞，且其製程可配合 前述之自我對準矽化物的製造，不需要額外的光罩，而可 同時在一晶片中製作出具有高效率的邏輯電路以及高密度 δ己憶胞之半導體元件。 依據前述，本發明並未曾有雷同或近似的製造方法揭 露或使用於此一技術領域上，固本發明具有新穎性 '進步 性及產業之價值性等專利要件，爰依專利法之規定提出申 請。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内所作之各種更動與潤飾，均^本發明的範圍 内。另外’本發明之保護範圍當視後附之申請專 界定者為準。 8 本纸張尺度適用中國國家標準（CNS)A4規格（2[0>< 297公釐） --------—裝------訂-------1 (請先閲讀背面之注意事項再填寫本頁)N --------- d ------ Order ------ line ί _ '(Please read the precautions on the back before filling out this page) Staff Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs For example, commercially available BARLi, XHRi-11 or SWK365D can be used as the material of the lower photoresist layer 24, and it can be coated with a photoresist coater, and then soft-baked. A photoresist layer 24 is formed on the silicon dioxide layer 22. In addition, the remaining lower photoresist layer 24 can be removed when the exposed photoresist is removed, which is quite convenient in operation, and the paper size applies the Chinese National Standard (CNS) Λ4 specification (210X2S »7 公 #_). Ministry of Central Standards Bureau, Consumers' Cooperatives, Yinfan 4 4897 9 at B7 V. Invention Description (4) No additional equipment and technology need to be added. Next, after the lower photoresist layer 24 is formed, an upper photoresist layer 26 is formed on the lower photoresist layer 24 in the memory area 110 by a conventional lithography process. Secondly, referring to FIG. 1B, dry etchback is performed using an ion source composed of N2 / 02 to remove a portion of the lower photoresist layer 24 in the logic region 100 that is not covered by the photoresist layer 26, until the silicon dioxide layer 22 and the nitride The silicon layer 16 exposes the lower photoresist layer 24. Then, the conventional method is used to remove the dioxide layer 22 in the logic region 100, and then the F base chemistry is used to remove the hardened curtain layer 16 for defining the gate electrode 12. After that, the silicon dioxide protection layer 14 above the MOS source / drain 18 in the logic region 100 is removed by conventional techniques, and then all the remaining lower photoresist layers 24a in the logic region 100 and the memory region 110 are removed. 24b, and an upper photoresist layer 26. Please refer to FIG. 1C, and then heat-resistant metal, such as metal titanium / silicon nitride, is sputtered onto the surface of the logic region 100 by a conventional sputtering process, and then a first stage of rapid thermal annealing is performed to expose the metal titanium and the bare metal. The polycrystalline silicon is reacted, and then the titanium / titanium nitride that is not reacted with silicon is removed, and then a second stage of rapid thermal annealing is performed, and the polycrystalline silicon gate 12 and the source / A self-aligned metal silicide 28a and 28b are formed on the surface of the silicon substrate on the drain 18 to increase the logic efficiency of the logic region 100. -Then, referring to FIG. 1D, an insulating layer 30 composed of silicon dioxide is formed on the surface of the structure shown in FIG. 1C, and is defined in the capacitor or the bit line in the memory area 110 at a predetermined formation position A self-alignment contact opening (SAC) 32, which exposes a source / no --------- A ------ ΐτ ------ 't ( Please read the notes on the back before filling in this page) This paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 44897 9 Λ7 —— _______ Β7 V. Description of the invention (5) Base surface of the pole 18. Finally, please refer to FIG. 1E. At the position of the opening 32, a defined conductive layer 34 composed of metal or polycrystalline silicon is formed, which can be used as a capacitor lower electrode or a bit line in the memory region 110. By this, the light-free mask proposed by the present invention can integrate the metal silicide and self-aligned contact window processes, and use the pair of hot metal-titanium and polycrystalline silicon gate 12 and source / drain 18 in the logic region. The polycrystalline silicon reaction produces self-aligned titanium silicides 28a, 28b, which can make the logic circuit 100 have higher efficiency. In addition, by using the process proposed by the present invention, a self-aligned contact window 32 that can be used as a capacitor lower layer electrode or a bit line can be formed in the memory area 110 to produce a high-density memory cell, and the process can cooperate with the foregoing The manufacture of self-aligned silicide does not require an additional photomask, and can simultaneously produce a high-efficiency logic circuit and a high-density δ-memory semiconductor device in one wafer. According to the foregoing, the present invention has not been disclosed or used in this technical field by the same or similar manufacturing methods. The invention is based on patent elements such as novelty, progressiveness, and industrial value, and is filed in accordance with the provisions of the Patent Law. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any modification and retouch made by those skilled in the art without departing from the spirit and scope of the present invention are within the scope of the present invention. Inside. In addition, the scope of protection of the present invention shall be subject to the application specifically defined below. 8 This paper size applies to China National Standard (CNS) A4 specification (2 [0 > < 297 mm) ---------- installation ------ order ------- 1 (Please read the notes on the back before filling this page)