TW419826B - Integration of bipolar and CMOS devices for sub-0.1 micrometer transistors - Google Patents

Abstract

Form a semiconductor device with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. Form a gate oxide layer above the isolation structures on the top surface of the silicon semiconductor substrate. Form a conductive polysilicon layer above the thin silicon oxide layer. Mask the NMOS and PMOS regions of the substrate with an emitter mask having a window over the emitter area of the substrate. Ion implant emitter dopant into a portion of the conductive polysilicon layer over the emitter area of the substrate through the window in the emitter mask. Strip the emitter mask. Anneal the substrate including the thin silicon oxide layer, and the polysilicon layer to drive the dopant into an emitter region in the emitter area in the substrate. Form doped source/drain regions and a base in the emitter area of the substrate.

Description

4] 9 82 6 "V. Description of the invention (1) [Background of the invention] 1. Field of the invention The present invention relates to a semiconductor device ', especially a ^ + conductor transistor device, and a method for manufacturing the same. , Yuli 2. Related technical description

Va j ana's patent ^ jk s ^ xa Complementary hybrid quilt transistor ", US patent No. ^ 7Qq η〇 [: # Table of the dual load '㈣I 扪 弟 {), No. 7 93, 08 No. 5, showing the source and base regions with ion implantation, or% pull-down implanted metal-oxide semiconductor process. Zhanzi Hu

Darfflawan's patent and process for manufacturing single-crystal polycrystalline silicon high-performance bi-carrier trans-gold semiconductors 〃, US Patent No. 5,681,765, shows a kind of bi-carrier complementary metal-oxygen semi-finger cedar system. It has a polycrystalline silicon layer 78 with a thickness of about 3250 ，, a polycrystalline silicon layer F and a female ^ 0 item. There is a patterned photoresist layer 80 on the top. The photoresist layer has an opening and is doped with sand. The photoresist layer is implanted through the opening to form a base-emitter region 84 'for use in an epitaxial layer 60 and a well 68 // the final bipolar transistor.

Harada's patent, a semiconductor integrated circuit with a double-carrier transistor and a lightly doped drain, a metal-oxide-semiconductor field-effect transistor #, US Patent No. 5,606'192, shows a dual-carrier complementary type The gold-oxygen semiconductor process has a polycrystalline dream layer and ion implantation of boron ions to form an N-type region in the polycrystalline silicon emitter electrode layer 23, which is formed on the gate oxide layer. On 12, the gate vaporization layer 丨 2 is formed on a base layer 丨 9, and the base layer 19 is formed on an n-type epitaxial layer 4 of a P-silicon substrate 1.

Ford's patent, manufacture of a bipolar transistor with a shallow trench

Page 4 4 1 9 82 6 -ί 5. Description of the invention (2) Bistatic complementary metal-oxide semiconductor integrated circuit with straight base contact, US Patent No. 4,902,639, describing a bipolar semiconductor In the process, in the third paragraph of the patent, line 23_41, the gold metal oxide region 27 is mentioned, and the second polycrystalline silicon layer is deposited on the previous polycrystalline silicon layer as the middle one of the second metal oxide semiconductor region 27. At that time, Hum 2: The crystalline silicon layer is doped with a large amount of dopants, and becomes a polycrystalline silicon N + layer containing N + dopants. One way is to use a continuous process to deposit the polycrystalline silicon as a mass layer. At that time, in the negative metal-oxide semiconductor region 27, a portion of the second polycrystalline silicon layer, which is now a polycrystalline silicon N + layer 40, will be used in a P well region 16 by the diffusion effect caused by the high temperature fire. An embedded contact area 41 is formed in line 4, in the fourth paragraph of the patent, line 4-43, a trench is formed where the NPN transistor is expected to be formed. First, by implanting boron in N well 19 to form an active pole region 67, an oxidized sidewall 68 is formed in the trench, and a polycrystalline silicon emitter is deposited in the trench between the oxidized sidewall 68. The implantation technique is doped with emitter 69 as N-type. Through this process or annealing, a very shallow N-type emitter junction is formed in the active emitter region from the doped polycrystalline silicon emitter 69.

Pe 1 e 1 1 a patent, electrostatic discharge protection device, U.S. Patent No. 5'504, 362, in paragraphs 7 and 8, and in Fig. 2 > The pole contact 4 8 / P + diffuses outward from the polycrystalline silicon base contact 4 4 to form a dual-carrier complementary metal-oxide semiconductor device. An NPN emitter region of an NPN bipolar transistor 15C diffuses out 39 / P + Base outward diffusion region 40.

Komuro's patent, a method for manufacturing a double-carrier metal-oxide semiconductor device, 'US Patent No. 5,652,154, shows a method for manufacturing a double-carrier complementary type

4 1 9 82 6 V. Description of the invention (3)-The process of the metal-oxide semiconductor device, paragraph 5 of line 7_37 in the patent, by-implantation of P-type dopants containing boron, to one? Type silicon substrate ⑴ of the "silicon region C, forming an intrinsic base region 109. Later in the process there is-polycrystalline silicon :: ion implantation 'The ion implantation is performed from a doped glass layer Driving dopants, or by implanting N-type dopants to the polycrystalline stone by ion implantation, is first modified to have -N-type conductivity, #Xiao, the shape of the doped polycrystalline stone is at the pole Electrodes U2a-112c, interelectrode U2a_n2c will be used to form field effect transistors in areas A and B, and one of the two-carrier devices in area C. Then, ^ # Emitter electrode U2C, located in a · The emitter ... "The evening layer is used as an -I diffusion region i to form a bipolar transistor. The step 00 is a heat treatment step for forming the N-type emitter region 113 (No. 1 of the P-type intrinsic region 109). Section 5 38_59 i [Inventive Summary] When the complementary metal-oxide semiconductor transistor is used, the thickness of the intermetallic oxide will be approximately 5 Angstroms to 4. The Angstrom] in =, the double-carrier device and the metal-oxide semiconductor # In this case, the gate structure of the two devices in the P device will be more similar to each other than the same device in the large-sized device. According to the present invention, a simple way is provided to realize the connection with the metal oxide semiconductor device, and the manufacturing method: it is very compatible with the complementary metal oxide semiconductor process, and only requires steps to form a standard complementary metal oxide. Oxygen semiconducting step-by-step carrier transistors. 1 Automatic alignment of Shuangyizhen semiconductor substrate in semiconductor process—the top table separates the substrate into a plug region. According to the method of the present invention, the in-plane dielectric, Insulation structure

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V. Description of the invention (4)-the emitter region, a negative metal-oxide semiconductor region and a positive metal-oxide semiconductor region to form a semiconductor device, the plug region and the emitter far from the negative metal-oxide half region and the positive metal-oxide semiconductor region Areas are juxtaposed, and a dopant layer is formed in the plug area and the emitter area of the substrate from the substrate / Zhu. A surface of a collector plug region substrate formed in the plug region extends to an embedded dopant layer, and a gate oxide layer is formed on the surface of the silicon semiconductor substrate, covering the insulating structure to form | A conductive polycrystalline silicon layer connected to the thin silicon oxide layer. Above the emitter field of the substrate, there is an open one emitter shield which covers the negative semiconductor region and the positive metal oxide semiconductor region of the substrate. In the emitter mask, the emitter region of the | On the other hand, through the opening, the ion implanted emitter is doped to the part of the | polycrystalline f, the emitter cover is removed, the substrate is annealed, and the thin silicon oxide layer and the polycrystalline silicon layer are driven to drive the The dopant enters one of the emitter regions of the substrate's emitter region. In the emitter region of the substrate, a tritium or drain electrode and a base are formed. The annealing process is preferably a rapid thermal annealing. The edge structure is a trench formed in the substrate and filled with a silicon oxide dielectric. The gate oxide has a thickness of about 5 angstroms to angstroms. According to another aspect of the present invention, a semiconductor device includes a dielectric and insulating structure on the top surface of a silicon semiconductor substrate. The substrate can be separated into an emitter region, a negative metal oxide semiconductor region, and a positive metal oxide. In a half region, on the top surface of the Shixi semiconductor substrate, a gate oxide layer is overlaid on the insulation structure, and a conductive polycrystalline silicon layer is overlaid on the siliconized layer. Above the emitter region of the substrate, the emitter dopant has been ionized to a part of the conductive polycrystalline silicon layer, and the region conductor including the thin silicon oxide layer is separated from the surface crystal, and a gold oxide bottom is covered from the top The material is insulated, including the source D of the polar region, so that the conductor is covered with a silicon substrate.

4 1 9 82 6 V. Description of the invention (5) Fire to drive dopants from the polycrystalline silicon layer into the substrate emitter region to guide the source of the micro-ST dopants " and the negative metal formed on the substrate Oxygen half: body region and positive metal-oxide semiconductor region, i-base region is good, and the "annealing process" is the most important thermal annealing process. The closed-oxide has a thickness of about 5 angstrom to 40 ohms of electrical insulation,. '. The structure is formed; ^ the bottom of the trench, i filled with oxidized stone Yusuke [Schematic explanation] and other points of view, as well as advantages, will be used in the drawings Middle: Figures 1 through 1 are cross-sectional front views of a part of a device according to the present invention, showing different stages of the process. Fig. 13 is a front view of the invention showing one part of the semiconductor device. [Detailed description of the preferred example] The present invention is a dual-carrier complementary metal-oxide-semiconductor process used in the standard complementary metal-oxide-semiconductor process to manufacture a double-carrier transistor; please refer to FIGS. 5 to 7 The figure shows a semiconductor device 10 of the present invention—partly in the manufacturing phase; as shown in FIG. 5, in the process stage of the present invention, a bipolar polysilicon is passed through one of the masks 20 The emitter opening 20 'is subjected to an N-type dopant implantation step to form a polycrystalline silicon layer "of-N + doped site 18," followed by Figure 6, the polycrystalline silicon layer is being patterned into an N + dopant. The emitter portion 18E and the gate electrodes 18N and 18P; in FIG. 7, the device has been annealed and caused in the silicon semiconductor substrate 12 of the device 10,

Page 8 '4 1 9 82 6 ~ "-. _ V. Description of the invention (6)' — An emitter region Em is formed below the emitter portion 18 ′. [Process flow] 1) On; STI (shallow trench insulation) insulation structure, and other pre-operations. FIG. 1 is a cross-sectional front view of a part of the half-body device 10 in the initial stage of display manufacturing of the present invention. The semiconductor device 10 includes-a P-doped silicon semiconductor substrate II. On the P-doped silicon semiconductor substrate 丨, an N-Epi-silicon semiconductor substrate 12 is formed. In the N ~ Epi layer 12, according to the present invention, four shallow trench insulation structures ST I formed in four equal trenches are shown. A structure is illustrated, and the insulation structure STI is filled with a silicon oxide dielectric. The insulation structure STI is formed from N ~ The surface of the Epi layer 12 reaches a substantial depth downward. The insulation structure ST is designed to isolate the emitter region E from the negative metal-oxide semiconductor region N. The emitter region E is located at the left end of the device 10, and the negative metal-oxide semiconductor region N is located in the middle of the device 10. The region ν is also The positive metal oxide semiconductor region P is located at the right end of the device 10 and isolated from the positive metal oxide semiconductor region. The emitter region E is between the first and the second from the left of the four insulating structures stI. The negative metal-oxide semiconductor region N is between the second and the third from the left of the four insulating structures STI. Among them, the ortho-metal oxide semiconductor domain P is located between the four insulating structures STi from the left to the third and fourth gates from the left. In the first figure, a mask 1 3M has been formed. On the surface of the N-Epi layer 12, three of the four insulating structures STI are counted from the right, so that the four insulating structures STI are exposed between the first and the second of the four insulating structures STI from the left. Emitter region E, which allows deep implantation of N + ions 301 in the device 10 to

Page 9 41 9 82 6 V. Description of the invention (7) Formation of the bridge and bridge siibU and N-EpU12 located in the Jieshi 2 = embedded people 13, that is, P_ typical double respect as early as shown in Figure 1, Basis — Oxygen Semiconductor ΐϊΪ The oxygen semiconductor manufacturing process 'The amphiphilic complementary gold M ^ Μ ^' In the silicon wafer 11, there is an initial process for the NPN transistor, and it is doped with -N lock dopant ions i 3 [Can J + intersperse layer 1 3 cover one of N — worm crystal layer 12 and enter 13. The aunt is Sb or arsenic, forming N + dopant insert = 13 ' The dose and energy of the ion 131 and the degree of M ^, ^ Trade ”Chen degree 'are within the range of practice, which will be understood by those enthusiastic about this technology. 2) Forming the N + collector plug. The second picture is the device 10 of the first picture. A curtain ⑶ has been formed on the surface of the N-Epo layer 12 and covers the number from the left of the first insulation structure §τι. Next, the four insulation structures STI extend to the right. The purpose is to expose an area on the left side of the emitter region E to allow the implantation of N + ions CI to form an N + collector plug on the left side of the leftmost insulation structure STI. Plug c, the N + collector plug C extends downward from the top surface of the M Epi layer 12 to cover and directly contact the top surface of the embedded t layer 13. The amount and energy of the ion implanted when the collector plug c is formed, and the concentration of the dopant in the collector plug C are all within the range of practice, which will be understood by those skilled in the art. 3) Growth gate oxide Figure 3 shows the device 10 of Figure 2. A blanket gate oxide layer GOX has been formed on the surface of the N-Epi layer 12 and covers and contacts the N-Epi layer. 12 and the top surface of the insulating structure ST I, that is, covering the N-Epi layer 12 and the insulating structure ST I. The gate oxide layer GOX is a thin silicon oxide layer with a thickness

Page 10 41 9 826 V. Description of the invention (8) About 5 Angstroms to 40 Angstroms. 4) Formation of polycrystalline silicon The device 10 shown in FIG. 3 also includes a blanket polycrystalline silicon layer 18, which is formed in a step under 3) in a conventional process order, and is covered with the gate oxide GOX ' It will be understood by those skilled in the art that the polycrystalline silicon layer 18 has a thickness that is typically the same as the polycrystalline silicon layer of the gate electrode of a field effect transistor. 5) Forming the mask of the bipolar transistor emitter Figure 4 is the device 10 of Figure 3, a photoresist doped mask 20 has been formed and covers the blanket polycrystalline silicon layer 18, and The surface of the polycrystalline silicon layer 18 is exposed, and a shallow surface is formed in the surface of the N-Epi layer 12 between the first and second STI regions counted from the left, as in the emitter region E of the N-Epi layer 12 As shown, the canopy 20 includes an opening 20 'between the leftmost two of the four insulating structures ST I. Below the gate oxide layer GOX, a sufficient amount of N-Epi. Layer 12 is implanted. The energy of the ions 21 'ion implanted difluorinated decay (βρ2) dopant ions 21 can be formed on the surface of the N-Epi layer 12 between the first and second STI regions from the left to form the shallow p -Zone 17, the amount and energy of the implanted ions 2 i at the time of the formation of tadpoles, and the quality of the inferred quality are all in the range of practice. ^ This will be understood by acquaintances. 6) Implanting polycrystalline stone only for the bipolar transistor. Figure 5 is the device 10 of Figure 4 (the original place of the mask in Figure 4), which is located at the N + doped site 18 of polycrystalline silicon 18, ( In the N-emitter region (p-on the dopant region π) is being ion-implanted, the P1 layer uses an energy of about 20 仟 electron volts to over 50% of the plant's N +. ion

4 1 9 82 B-V. Description of the invention (9) 22, through the opening 20 in the mask 20, about lxl 015 ions / cm2 to lxlO16 ions / cm2 arsenic (N +) dopant ion 22 The dosage will cause the concentration in this process stage to be about lxlO19 atoms / cm3 to lxl02i atoms / cm3. 7) Patterned emitter and complementary metal-oxide semiconductor gate. Figure 6 shows the device 10 of Figure 5. A patterned mask 30 has been formed on the polycrystalline silicon layer 18 including the part 18 '. There are four large openings 30 ′ through which can be used for etching to form an NPN N + doped emitter site 18E ′ and complementary metal-oxide semiconductor gates 18N and 18P. The four openings of the pattern forming mask 30 30, 'centered on the insulating structure STI, using the mask 30, through the opening 30', the polycrystalline silicon layer 18 has been etched down to the gate oxide layer GOX. As a result, the N + doped polycrystalline silicon emitter site 18E, On the emitter region E of the N-Epi layer 12, an N + doped site 18 is formed, and a negative metal oxide semiconductor gate electrode 18N is formed on the N region of the N-Epi layer 12 and a positive metal oxide semiconductor. The gate electrode 18P is formed on the P region of the N-Epi layer 12. 8) Rapid thermal annealing (RTA) to drive the dopant dopant. Figure 7 shows the device in Figure 6. 10 has been etched to remove the 18E and negative metal-oxide semiconductor gates of the non-doped N + doped polycrystal evening emitter. The electrode oxide layer 18N and the gate oxide layer G0x protected by the positive metal oxide semiconductor gate-pole 18P. Secondly, performing a rapid thermal annealing process can drive the polycrystalline silicon emitter site 18E to dopant, and pass downwards through the polar oxide layer Gox site that is still remaining under the "doped polycrystalline silicon emitter site 18E" and enters the formation. In layer 1 ^, a new emitter substrate N + doped region EM is used as part of the NpN device. The N + doped region EM and the N + doped polycrystalline silicon emitter region are automatically aligned.

Page 12 4 1 9 82 6 V. Description of the invention (10) 0 9) Forming the pldd / plds of the double carrier base and the positive metal oxide semiconductor region Figure 8 shows the device 10 of Figure 7 and a cover has been formed MP, during ion implantation of a slightly doped P-type boron doped ion PL into the slightly doped drain / source (LDD / LDS) region P-, the upper surfaces of regions e and p may be exposed, but covered Region N 'at this time' is for doped polycrystalline silicon emitter site 8E and gate 18P 'slightly doped drain / source (LDD / LDS) region p_ has been formed and can be automatically aligned with both. The implantation energy of the doped ion PLi is about 仟 electron volts to 50 仟 electron volts, and the implantation dose is about 1 × 1017 ions / cm 2 to 5 × 10 “ions / cm 2” so that the concentration at this stage of the process is about & 1〇16 Atoms / cubic centimeters to 5x1 atoms / cubic centimeters. 10) Forming the p + region of the double carrier base and the positive metal oxide semiconductor region. The ninth picture is the device of the eighth picture. A gap wall sp is formed around the spar evening emitter site 1 E and the gate electrode 18 P, covering the area on either side of the emitter site 18E and the gate electrode i8P, and given at the full dose of ion implanted P-type doped PF. During implantation of doped polysilicon emitters 丨 8E and gate electrodes 18 P, the implantation dose of boron doped ion PF is preferably about 1 × 10 ions / .cm 2 ΙχΙΟ16 ions / cm 2, the energy is about 0i 仟 electron volts to 50 仟 electric volts | sub volts, and the concentration at this stage of the process is about 1 × 10〇 9 atoms / cubic cm to 1 χΐ〇21 atoms / cubic cm.! Result , A P + base region β and a P + doped region 44 and the adjacent emitter portion | Self-aligned spacer SP 'plus p + s / I ^ gap is also very busy with the adjacent wall SP Shu electrode 18P of self-alignment, p + base region and the β-doped Bu 4-bit transfer zone Shu

Page 13 4 1 9 82 6 ',, V. Description of the invention (π) on the left side of the emitter site 18E' The P + doped region 44 and P- doped region 46 are located on the right side of the emitter site 18E 'is used in practice In one positive metal oxide semiconductor device, the P + S / D region and the slightly doped (LDD / LDS) region P− are located on the left and right sides of the gate electrode 18 p. 11) Form the NLDD / NLDS region of the negative metal-oxide semiconductor region. Figure 10 is the device of Figure 9. 10 has formed a curtain foot, and a small dose of N-type doped NL to lightly doped ion is implanted in the ion implantation. During the M- period of the LDD / LDS region, the upper surface of the exposed region, and the coverage regions e and p, at this time, the slightly doped drain / source (LDD / LDS) region ^ has been formed at the gate 18N. Left and right, and automatically align with it. The dopant is preferably arsenic (As) or filling (P) dopant ions, the implantation dose is about 丨 \ 10! 2 ions / cm2 to 5x10 "ions / cm2, and the energy is about 0 1 仟 electron volt To 50. 仟 electron volts, the dopant concentration in this process stage is about 丨 from 6 atoms / cubic centimeter to 5xl018 atoms / cubic centimeter. 12) The region forming the negative metal-oxide semiconductor region is shown in Figure 11 as shown in Figure 10. The device 10 still retains the mask MN, and a gap SP has been formed around the electrode 18N. During ion implantation of a full dose of N-type doped NF, the upper surface of the area N is exposed to form the gate electrode 1⑽. The source / drain region is S / D, and it is automatically aligned with the gap sp. The doped liver is preferably arsenic (N-type) doped ions, and the implantation dose is about 1? ^ 1015 ions / cm2 to lxltP6 ions / cm 2, energy is about 0.1 仟 electron volts to 50 仟 electron volts, and the concentration at this stage of the process is about 1 × 1019 atoms / cubic centimeter to 1 × l 019 atoms / cubic centimeter. In an oxygen semiconductor device, the N + s / D region is slightly doped

Page 14 41 982 6 · 4 V. Description of the invention (12) The mass (LDD / LDS) region N- is located on the left and right sides of the gate electrode 18N. 1 3) Remove the cover, Figure 12 is the device of Figure 11. 10 The cover MN has been removed. The NPN transistor area includes P + replacement areas 40 and 44, from the emitter located below the gap wall. Parts 18E and P-slightly doped regions 42 and 46 are separated by a gap wall. The N + emitter region E is between P-slightly doped regions 42/44. A thin oxide layer 32 has been formed and overlapped. (Upper) The collector region c in the N-Epi layer 12 is located above the Sn region (the periphery of the P + / N + region of the device 10). 1 4) Subsequent process Figure 13 is the device of Figure 12. 10 has formed a conductive region composed of titanium silicide (TiSix) 50, 51, 52, 5 3 above the N + / p + region where it is placed. , 5 4 and 5 5 to reduce resistance. In addition, a titanium silicide (TiSix, where x is preferably a positive integer 2, that is, T 1 S ζ) layer 28A has been formed over the polycrystalline silicon emitter site 8E and the gate electrodes 18N and 18P. The present invention has been described based on the above specific examples, and those skilled in the art will understand that the present invention is within the scope and spirit of the patent application for subsidiary applications :: Modification and practical application, that is, form and details can be added; Without departing from the spirit and scope of the invention. Because of & such changes will be within the scope of the scope of the present invention, and the present invention includes the following patent applications ^ Brief description of the drawing number | ίο Semiconductor device I 11 P-push silicon semiconductor substrate!

41 9 826 V. Description of the invention (13) 12 Doped epitaxial (N-Epi) silicon semiconductor layer 13 N + drum layer 131 N + doped ion 13M mask 17 shallow P-region 18 blanket polycrystalline silicon layer 1 8 'N + doped site i 18E NPN N + doped emitter site | 18N complementary metal oxide semiconductor gate 丨 18P complementary metal oxide semiconductor gate J 19 base layer • 20 screen I 20' opening 21 ion 22 N + ion 28A titanium silicide 2 8B titanium silicide 丨 2 8 C titanium silicide 30 mask 3 0 'opening 32 thin oxide layer | 42 P-slightly doped region 44 P-slightly doped region 46 P-slightly doped region; 50 conductive region 5 51 conductive area

Page 16 4 1 982 6 V. Description of the invention (14) 52 Conducting area 53 Conducting area 54 Conducting area 55 Conducting area

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Claims (1)

4 1 9826 VI. 1. Scope of patent application p.:^j The methods for forming a semiconductor device include: constructing a top of a silicon semiconductor substrate, the insulating structure separating the bottom 2. 3. 4. ， Forming a dielectric and insulating junction ^-a bi-carrier region, a negative metal-oxide semiconductor region, and a positive metal-oxide semiconductor region; on the top surface of the semiconductor substrate, a thin silicon oxide layer is formed and covered The insulating structure; forming a conductive polycrystalline silicon layer, covering the thin silicon oxide layer; covering the negative metal-oxide semiconductor region and the positive metal-oxide semiconductor region of the substrate, which are used on the carrier region of the substrate, having An open double carrier curtain is used for this purpose; through the openings of the double carrier mask, ion implanted dioxygen dopants enter a part of the conductive polycrystalline layer on the double carrier region of the substrate; Lowering the dual-carrier mask; annealing the substrate of the thin silicon oxide layer and the polycrystalline silicon layer to drive the dopant into the substrate, one of the dual-carrier regions; and In the double-carrier region of the substrate, the shape of the substrate is doped into the source / drain region. One pair of carrier base. For example, in the method of applying for the first item of the patent scope, A,, and Xihai annealing is rapid thermal annealing. For example, the method of claim X in the patent application range, wherein the silicon oxide has a thickness of about 5 to 40 angstroms. f As in the method of applying for the first item of the patent scope, the middle ^ long Y anneal is annealed to a long distance fire, and the silicon oxide contains open-pole oxygen * '' 'The pore compound has a thickness of about 5 angstroms Younger page 18 419826 ί 6. The scope of patent application is 40 Angstroms. 5. If the scope of the patent application is' formed on the substrate 6.-A method of forming half of the semiconductor substrate, the plug in the substrate body region, the plug and the method of the first item, and filling the body, The body region that separates the oxygen semiconductors from the juxtaposition is formed on the substrate for the plug to extend downwardly from the silicon half to cover the one of the top surface to become a plug and a positive metal oxide. The insulating structure is a trench. Chemical dielectric. Including: forming a dielectric, an insulating structure, an emitter region, and a negative gold region located at a depth of the gold-oxygen semiconductor from the surface, one of the plugs-one of the bipolar transistor embedded in one side of the semiconducting emitter region; A body region, and an emitter region region away from the negative metal-oxide-semiconductor region to form a collector extending to the bottom of the conductor, an insulating junction, the top surface of the embedded doped material, a plug layer, a surface region, and an emitter region A doped layer is formed into a region; from the surface of the substrate, a gate oxide layer is formed, a conductive polycrystalline silicon layer is formed, and the thin silicon oxide layer is covered; under the surface of the emitter region, a Slightly reverse doped region; the negative and positive metal-oxide semiconductor regions of the substrate are masked, using an emitter mask with an opening on the emitter region of the substrate; through the emitter An ion implanted emitter dopant of the electrode shield enters a portion of the conductive polycrystalline dream layer on the emitter region of the substrate; the emitter shield is removed; the complementary metal-oxide semiconductor gate is connected to the negative electrode. Metal oxide semiconductor region Page 19 4 1 982 6 6. On the conductor area of the patent application, an emitter conductor is patterned from the conductive polycrystalline silicon layer pattern on the emitter region; and annealed substrate including the thin silicon oxide layer and the polycrystalline evening layer are doped with ghosts. The mass enters the substrate, and one of the emitter regions is dynamically aligned; and “1 I is formed in the negative metal-oxide semiconductor region and the positive metal-oxide semiconductor region to form a source / drain of the material. The polar region and the formation of a base region are adjacent to the substrate ^! The emitter region in the emitter region. J 7. The method according to item 6 of the scope of patent application, wherein the annealing is a rapid thermal regression in which The gate oxide has a thickness of about 8 to about 5 angstroms to about 40 angstroms as in method 6 of the patent application range. 9. A method according to item 6 of the patent application range, wherein the annealing is rapid thermal annealing, and the gate The polar oxide has a thickness of about 5 angstroms to 40 angstroms. As described in the method of claim 6 of the patent application, wherein the insulating structure is wide, formed on the bottom surface, and filled with a silicon oxide medium 11. A semiconductor device ^ Includes: "": Quality k: junction formed on top of-silicon semiconductor substrate And the positive metal oxide semiconductor region, the double carrier £ region, the negative metal oxide + conductor region, a thin stone oxide layer, covering the silicon semi-insulating structure; the conductive polycrystalline silicon layer on the top β surface of the body substrate, covering The dopant doped ions are implanted on the bismuth oxide layer '-cai's bin region and implanted in the 4 1 982 6' The wasteful dopant dopant doped at 1 ^ has been removed from the substrate, and it includes the substrate from the polycrystalline silicon double carrier layer by annealing to drive the substrate into the sub-layer oxide layer, thereby doping the substrate. The source of the double dopant /, and the domain, and τα /, of the doped b-domain of the substrate are formed in the negative metal-oxide semiconductor region of the substrate—the second metal-oxide semiconductor region; and 1 2. The main base of Shen Yun is formed in the double carrier region of the substrate. The device for annealing a wide range of item 11 wherein the annealing is rapid heat 13 such as the device of Shen Shi Nao & Qing patent range for the device of item 11 wherein the silicon oxide contains a kappa Λ compound having a thickness of about 5 Angstroms to 40 Angstroms. Aye. The device of item 11 of the Ming patent claims that the annealing is rapid heating, and that the silicon oxide includes a gate oxide and has a thickness of about 5 to 40 angstroms. The trench is formed on the bottom 16, a semiconductor-mounted dielectric. The insulated junction surface separates the bottom 5 from the device in the scope of patent application No. 11 ', wherein the insulating structure is a trench and filled with a silicon oxide dielectric. Includes E formed on the top of a silicon semiconductor substrate. The top table is a plug region, an emitter region, a negative metal oxide semiconductor region, and a positive test. The oxygen semiconductor region is juxtaposed with the emitter region. The plug region 'is located on the side of the emitter region away from the negative metal-oxygen hemibody region and one of the positive gold and oxygen semiconductor regions; and I is embedded in a dopant layer for the substrate deep from the surface. One of the bipolar transistor in the plug region and the emitter region; Page 21 4 1 9 82 6 The scope of the patent application is a collection of plug regions, in the plug region, extending downward from the surface of the substrate to the embedded dopant layer; a gate oxide layer, Overlying the insulating structure on the top surface of the silicon semiconductor substrate: a conductive polycrystalline silicon layer overlying the thin silicon oxide layer and complementary metal oxide semiconductor gates on the negative metal oxide semiconductor region and the positive metal oxide semiconductor region, An emitter conductor is formed from the conductive polycrystalline silicon layer on the emitter region; a slightly reverse doped region is formed under the surface of the emitter region; the emitter is doped on the emitter region of the substrate, and Being ion-implanted into a part of the conductive polycrystalline debris layer; the substrate 'includes the thin stone oxide layer and its dopants, and the dopants are driven from the polycrystalline silicon layer into the substrate by annealing. In the emitter region, one of the emitter regions; the doped source / inverter region is formed in the negative metal oxide semiconductor region and the positive metal oxide semiconductor region of the substrate; and a base electrode is formed in In the emitter region of the substrate. 17. The device according to item 16 of the patent application, wherein the annealing is rapid thermal annealing. 18. The device according to item 16 of the patent application has a gate oxide having a thickness of about 5 angstroms to 40 angstroms. 19 'The device according to item 16 of the application, wherein the annealing is rapid thermal annealing, and the gate oxide has a thickness of about 5 to 40 angstroms. 20. The device according to item 6 of the patent scope of claim β, wherein the insulating structure is a trench formed in the substrate and filled with a silicon oxide dielectric. Page 22