TW418496B - Method of protecting sidewall of photosensitive low-dielectric interlayer via - Google Patents

Abstract

A method of protecting a sidewall of a photosensitive low-dielectric interlayer via comprises using a photosensitive low-dielectric layer as the intermediate insulating layer of a metal interconnect structure; directly exposing a specific region of the photosensitive low-dielectric layer in order to convert the material into a material that is not soluble to certain solvents while the unexposed regions on the same layer can be selectively removed to form the desired via; protecting the exposed surface of the photosensitive low-dielectric layer by depositing of silicon oxide and anisotropically dry etching to form a silicon oxide barrier layer on the inside of the via and cover the upper surface of the photosensitive low-dielectric layer with a layer of silicon oxide.

Description

418496 V. Description of invention d)

The present invention relates to a process for manufacturing a semiconductor device, and particularly to a process of forming a through hole in a dielectric layer to expose a lower conductive layer. (2) iLlL technology shows that the semi-conductor industry continuously strives to improve the performance of semiconductor components, and also strives to maintain or even reduce its manufacturing costs. Sub-micron or micro-miniaturized semiconductor industry technologies can meet both high performance and low cost. purpose. The miniaturization of the device can reduce the resistance and capacitance which destroy the performance, and improve the device performance. In addition, sub-micron devices on a substrate of a specific size have a higher device density ', thereby reducing the manufacturing cost of a specific semiconductor wafer. The miniaturization was achieved due to advances in special semiconductor processes, such as lithography and dry etching processes. Not only does it use more complex exposure techniques, but it also develops more sensitive photosensitive materials that enable sub-micron images to be formed on photoresist layers. In addition, the development of more advanced dry etching tools and processes enables the lithography formed on the photoresist layer to be successfully transferred to the underlying material in order to manufacture more advanced semiconductor components. However, in addition to strengthening semiconductor process training, it is still necessary to optimize specific processes' to reduce the manufacturing cost of semiconductor components. In the field of semiconductor manufacturing, the through-hole process is related to cost and performance optimization. As component sizes shrink, it becomes more difficult to make sub-micron vias in the dielectric layer. The sub-micron lithography in the photoresist layer is used as a mask for the dry etching process when making sub-micron through holes. The photoresist process is not only an expensive process.

Page 4 4 184 96 V. Description of the invention (2) ----------- It may cause unexpected damage to the exposed metal surface. The reason is that it is used to remove the shape of the photoresist when forming a through hole. Caused by reactants and processes. The present invention will explain a novel process for forming a through hole in a dielectric layer, exposing the interconnection structure of the underlying metal, but the through hole opening process of the present invention does not require the use of expensive photoresist materials. Through direct exposure and selective removal of the exposed areas, vias are formed in the photosensitive low dielectric constant layer. However, unlike the traditional photoresist process, the photosensitive low dielectric constant layer is not removed. When the via is filled with metal, the photosensitive low dielectric constant layer becomes an intermediate dielectric layer, which is located on the upper and lower metal interconnects. Between structures. The present invention further proposes an alternative process, that is, a chemical vapor deposition method is used to bond an insulating spacer layer on the side of the through hole to protect the photosensitive low dielectric constant layer exposed from the side from the subsequent steps. Previous technologies such as Chang et al. In US Patent No. 5,559, 055 used low dielectric constant materials to fill the interlayer between two metal wires, but did not describe the use of a photosensitive low dielectric constant layer as an intermediate. The electrical layer is also not used as a material for forming a through hole without using a photosensitive photoresist material. SUMMARY OF THE INVENTION An object of the present invention is to form a through hole in a dielectric layer, so that the upper surface of the inner speed line metal structure of the lower layer can be exposed. Another aspect of the present invention is the use of the shape of a photoresist to form a through hole in a photosensitive low dielectric constant layer through the steps of direct exposure and development. Another object of the present invention is to form an insulating protective barrier layer on the side surface of a via hole formed in a photosensitive low dielectric constant layer.

418493 V. Description of the invention (3) '-According to the present invention, a process is described in which through holes are formed in the pre-sensing low dielectric constant layer' but a photoresist process is not used. A lower interconnect metal structure is provided, and then a photosensitive low-dielectric constant layer is added to form a desired through-hole pattern on the photosensitive low-dielectric constant layer through direct exposure. The unexposed photosensitive low dielectric constant layer is selectively removed by wet etching to obtain the desired through hole, so that the upper surface of the underlying interconnect metal structure can be exposed. Next, the insulating layer is chemically deposited, planarized, and anisotropically reactive ion etching (R IE) steps are performed to form an insulating barrier layer on the sidewall of the through hole. In addition, the remaining insulating layer covers the photosensitive layer. The upper surface of the low dielectric constant layer. Finally, the vias are plated with metal to protect the insulation barrier. The second method of the present invention is that after the photosensitive low dielectric constant layer is deposited, the planarization step is followed by a patterning process, which includes exposing and developing the photosensitive low dielectric constant layer and the unexposed areas. Process to form vias. A marginal barrier layer is then formed on the inner sidewalls of the vias using the same plating and anisotropic reactive ion etching (CRIE) process as used in the previous examples. V '_ Schematic description of the purpose and other advantages of the present invention with reference to the attached drawings for a & entire description, in the drawings: & 1 to 8 are schematic cross-sectional views of the first example of the present invention Wherein, a photoresist process is not used, and a through-hole protected by an insulating spacer is formed on the photosensitive low dielectric constant layer. '

4 18 at 93 ------------------- ---- V. Description of the invention (4) Figures 9 to 11 are schematic diagrams of the cross section of the second example of the present invention. Wherein, the planarization of the photosensitive low dielectric constant layer is performed before forming the via hole. Comparative Example Explanation A method for forming a through hole in a photosensitive low dielectric constant layer without using a photoresist will now be described in detail. FIG. 1 schematically shows an interconnect metal structure 3 and an overlying insulating layer 2 on a semiconductor substrate 1. As shown in FIG. The interconnect metal structure 3 can be used to contact the dynamic device region (not shown in the figure), such as a metal oxide semiconductor field effect transistor (MOSFET), a source and drain region in a semiconductor substrate 1, and a via contact region (Not shown), insulating layer 2 and the like. The interconnecting metal structure 3 may also be connected to the underlying interconnecting metal structure (not shown) and the underlying insulating layer 2 through through holes in the insulating layer 2. The semiconductor substrate 1 is formed of a single crystal silicon wafer in the p-type < 100 > crystal orientation. The insulating layer 2 is a silicon oxide layer, which can be reinforced by low pressure chemical vapor deposition (LPCVD) or plasma. By chemical vapor deposition (PECVD). The insulating layer 2 may be borophosphosilicate glass (BPSG) or silicon-on-silicon glass (PSG). The inner velocity line metal structure 3 may be an aluminum alloy or a high melting point metal such as tungsten, copper, etc., which may be formed by a plasma deposition method or a chemical vapor deposition method, and then fabricated by a lithography and etching process. Next, a photosensitive low dielectric constant layer 4a is applied, as shown in FIG. 2, and has a thickness of about 20,000 angstroms to 8000 angstroms. The photosensitive low dielectric constant layer 4a may be CHEMAT-β or benzocylobutene (BCB) or other photosensitive low dielectric constant materials. BCB is a negative light-sensitive layer, that is, an exposed area or a speeding area 'is not dissolved in a specific solvent, and a non-exposed area is removable in the same solvent. The dielectric constant of these materials is between 1.3 and 3.0

418496 V. Description of the invention (5) The 'can be used as an insulation layer between interconnected metal structures. Using the required chrome film, directly expose it on CHEMAT-B or "8 or other photosensitive low-dielectric constant material photosensitive layer 4a. 'Exposure in the opening in the chrome film. For CHEMAT-β use a wavelength of 19 Deep ultraviolet rays of 〇 to ι95 nanometers, and I rays with a wavelength of 36 to 37 nanometers (nm) are used for BCB, and their exposure doses are all 0 to 80 (millijoules / cin2), resulting in an exposed area 4a. Father's connection, leaving an unexposed and non-crosslinked region, as shown in Figure 3. For the CHEMAT-B layer, the non-crosslinked region 4b is more soluble in toluene than the exposed region 4a (for the BCB layer For example, the non-crosslinked region 4b is easier to dissolve in triphenylbenzene than the exposed region 4a.) Therefore, the selective removal of the non-crosslinked region 4b using xylene or fluorene is used to form the through hole 5, as shown in Figure 4 As shown in the figure. Without using a photoresist process, a through hole 5 is formed, and the upper surface of the interconnect metal structure 3 is exposed. The traditional photoresist process used previously includes: forming a desired through hole in the photoresist layer. Image, and then dry-etch the step 'transfer the through-hole image to the underlying insulating layer. The expensive process then uses an oxygen plasma process to remove the photoresist layer. This photoresist removal process will cause unnecessary oxidation and damage to the interconnect metal structures exposed under the vias. However, a photosensitive low dielectric constant layer is used. It will not only remain a part of the structure, which reduces the cost of the photoresist process, but also does not cause oxidation and damage to the bare metal structure. Figures 5 to 8 schematically show the use of interface materials to form a low-sensitivity interfacial material. The process of passivation and protection of the dielectric constant layer. In Figure 5, a PECVD or high-density chemical vapor deposition (HDPCVD) method is used to deposit a silicon oxide insulating layer on the photosensitive low dielectric constant layer 4a. Upper surface sink

4 ^ δ43B V. Description of the invention (6) The insulating layer 6a with a thickness of 2000 angstroms to 8000 angstroms is deposited on the exposed surface of the photosensitive low dielectric constant layer 4a in the through hole 5 at a thickness of 200 angstroms to 1 0 0 0 angstrom insulation layer 6 b. FIG. 6 shows that the surface is subsequently planarized by a chemical mechanical polishing method to produce a smooth upper surface of the insulating layer δ a, and the metal structure 3 is formed across the lower interconnecting line caused by the photosensitive low dielectric constant layer 4 a. The unevenness and depression are flattened. FIG. 7 shows an anisotropic reactive ion etching (RIE) method using trifluorofluoride (CHF3) as a post-etching agent to remove the insulating layer 6b under the via 5 and form the insulating layer 6 on the sidewall of the via 5 b. The upper surface of the interconnect metal structure 3 is exposed. Then, as shown in FIG. 8, an upper-layer interconnect metal structure 7 is formed to be in contact with the lower-layer interconnect metal structure 3 in the through hole 5. The upper interconnecting metal structure 7 is an aluminum alloy, which is deposited by radio frequency sputtering, and is patterned using conventional lithography and reactive ion etching using gas as an etchant. The upper interconnecting metal structure 7 can also be a high-refined metal material, such as crane or steel, which can be plated using the LPCVD method and then formed into a desired pattern by conventional lithography and RIE etching methods. The photosensitive low dielectric constant layer is now completely protected by the insulating interlayer 6b in the through hole 5 and the insulating layer 6a on the upper surface of the photosensitive low dielectric constant layer 4a from the interconnect metal structure 7. 9 to 11 are second examples of the present invention, which are characterized in that the photosensitive low-dielectric constant layer 4a is planarized before an insulating layer is deposited and an insulating spacer is formed inside the through hole 5. Fig. 9 shows a step of applying a chemical mechanical polishing (CMP) to the photosensitive low dielectric constant layer 4a after the formation of the through hole 5. The photosensitive low-dielectric-constant layer 4a is coated on the lower interconnecting metal structure 3, and the resulting traverses the lower interconnecting metal structure 3 and the ruggedness between these structures.

418496 V. Description of the invention (7) The uneven upper surface is smoothed by the CMP process. In Fig. 10, a PECVD or HDPCVD method is used to deposit an oxide layer on the sidewall of the via 5 again, and then anisotropic reactive ion etching is used, and trifluoromethane (CHF3) is used as an etchant. An insulating barrier layer 6b is formed inside the hole 5, and an insulating layer 6a is formed on the planarized upper surface of the photosensitive low dielectric constant layer 4a, and the thicknesses of the two are about 2 0 0 Angstroms to 8 0 0 0 Egypt 2 0 0 Angstroms to 1000 Angstroms. FIG. 11 is the final step. An upper-layer interconnect metal structure 7 is formed in the through hole 5 to be in contact with a lower-layer interconnect metal structure 3. The material and manufacturing process of the interconnected metal structure 7 are the same as those of the first example of the present invention. The advantage of using a non-photoresistive process when forming the through hole 5 is that it protects the photosensitive low dielectric constant layer 4 a from subsequent overlying substances or processes through the protective effect of the insulating layer 6 a and the insulating spacer 6 b. 5 Although the present invention has been described with reference to preferred examples, please understand that professionals in the bank can make various changes without departing from the spirit and scope of the present invention.

Claims (1)

4 1 8 4 9 6 VI. Shen Qi's patent scope i · A method for forming a through hole in an insulating layer on a semiconductor substrate, including the following steps: preparing the semiconductor substrate, which contains a dynamic element region, and forming a An insulating layer covers the dynamic element region; a first interconnect metal structure is formed on the insulating layer; on the first interconnect metal structure and on the insulating layer not covered by the first interconnect metal structure Coating a photosensitive low dielectric constant layer; directly irradiating a light source to a first region of the photosensitive low dielectric constant layer to form an insoluble material, and leaving an unexposed in a second region The soluble region directly covers the first interconnecting metal structure; the soluble material is selectively removed in the second region, so that the through hole is formed in the photosensitive low dielectric constant layer, and the first inner The upper surface of the connecting metal structure is exposed; the first interconnect is exposed on the upper surface of the photosensitive low-dielectric constant layer, the photosensitive low-dielectric constant layer on the side of the via, and the lower layer inside the via, respectively. Upper surface of wire metal structure Deposit a silicon oxide layer; planarize where the silicon oxide layer covers the photosensitive low dielectric constant layer to form a smooth upper surface; use a non-isotropic dry name to engraved * on the side wall of the through hole Forming an oxidized dream barrier and forming a second interconnecting metal structure 'a first portion of the second interconnecting metal structure is in the through hole, and a second portion of the second interconnecting metal structure is covering the On the silicon oxide layer on the upper surface of the photosensitive low dielectric constant layer. 2. The method according to item 1 of the patent application scope, wherein the dynamic element area may be 418496 6. Scope of patent application Source and source of the semiconductor substrate; and polar region. 3. If the method of applying for the scope of the first item of the patent, the dynamic component area is a metal structure. 4. If the method of applying for the scope of the first item of the patent, the first interconnecting metal structure may be aluminum alloy, tungsten metal or Copper metal structure. 5. The method according to item 1 of the patent application range, wherein the photosensitive low dielectric constant layer is benzocylobutene (BCB), the dielectric constant is between 2.5 and 3.0, and the thickness is about 2000 Angstroms to 8 0 0 0 Angstroms. 6. The method according to item 1 of the patent application range, wherein the wavelength of light used for direct exposure of the photosensitive low dielectric constant layer is 360 to 370 nanometers (nm) for BCB, and the exposure dose is 0 to 800. Millijoules / cm2 to form the insoluble material. 7_ The method of claim 1 in the scope of patent application, wherein the solvent used in the selective removal of the dissolvable material is xylene to the non-exposed area of the BCB layer to form the through hole. 8_ The method of claim 1, wherein the silicon oxide layer is deposited by PECVD or HDPCVD, and the upper surface of the photosensitive low dielectric constant layer is about 200 angstroms to 800 angstroms thick. The thickness of the photosensitive low dielectric constant layer on the side of the hole is about 200 angstroms to 1,000 angstroms. For example, the method of applying for the first item of the patent scope, in which trifluoromethane (CHF3) is used as an engraving agent and a non-isotropic reactive ion etching method is used to form a silicon oxide barrier layer on the side of the through hole. 10'The method of claim 1 in which the second interconnecting metal structure is an aluminum alloy, tungsten metal, or copper metal structure. Page 12 11. A method for manufacturing a through hole on a presensing low dielectric constant layer without using a photoresist process and forming a silicon oxide barrier layer inside the through hole, comprising the steps of: forming a first interconnect metal structure; The photosensitive low dielectric constant layer is deposited on the first interconnected metal structure and on the lower layer not covered by the first interconnected metal structure; the chemically low dielectric constant is deposited on the photosensitive low dielectric constant by a chemical mechanical polishing method. A flat surface is formed on the layer; a first region of one of the photosensitive low dielectric constant layers is directly irradiated with a light source to form an insoluble material, and the photosensitive low dielectric constant layer is directly covered on the first A second region on an interconnected metal structure is not exposed; the unexposed second region is selectively removed in the photosensitive low-dielectric constant layer; and the via hole is formed in the photosensitive low-dielectric constant layer. And expose the upper surface of the first interconnect metal structure; deposit a silicon oxide layer; anisotropically etch the silicon oxide layer to form the silicon oxide spacer on the side wall of the through hole; and Form a second inner Gold eyebrow line structure, in contact with the upper surface of the connecting structure of the first metal within the through hole. 12. The method according to claim 11 in which the first interconnecting metal structure can be an aluminum alloy, tungsten metal, or copper metal structure. ′ 1 3. The method according to item 11 of the patent application range, wherein the photosensitive low dielectric constant layer is benzocylobutene (BCB), and the dielectric constant is about 2,5 Page 13 4iaAqq 4 ^ 8498 A _ ______ VI. The scope of patent application is between 3.0 and 3.0, and its thickness is about 2000 angstroms to 8000 angstroms. 14. The method according to item 11 of the scope of patent application, wherein the non-soluble material is directly exposed to an area of the photosensitive low dielectric constant layer to form 'the wavelength of light used for the BCB of 360 to 370 nanometers. Meters (nm) 'are all exposure doses from 0 to 800 millijoules / cm2. 15. The method according to item 11 of the scope of patent application, wherein the soluble material is selectively removed in the photosensitive low dielectric constant layer to form the through hole, and the solvent used is three times for the unexposed BCB layer. Toluene. 16. The method according to item 11 of the patent application, wherein the silicon oxide layer inside the through hole is obtained by PECVD or HDPCVD, and has a thickness of about 200 angstroms to 1,000 angstroms. 1 7. The method according to item 11 of the scope of patent application, wherein the silicon oxide barrier layer is formed inside the through hole, and trifluoromethane (CHF3) is used as an etchant to apply anisotropic reactivity to the silicon oxide barrier layer. Ion etch process. 18. The method according to item 1 of the scope of patent application, wherein the second interconnecting metal structure is an aluminum alloy, tungsten metal or copper metal structure " Page 14