TW418495B - Copper interconnect structure and method of formation - Google Patents

Copper interconnect structure and method of formation Download PDF

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Publication number
TW418495B
TW418495B TW088105369A TW88105369A TW418495B TW 418495 B TW418495 B TW 418495B TW 088105369 A TW088105369 A TW 088105369A TW 88105369 A TW88105369 A TW 88105369A TW 418495 B TW418495 B TW 418495B
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TW
Taiwan
Prior art keywords
copper
layer
interconnect
opening
dielectric layer
Prior art date
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TW088105369A
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Chinese (zh)
Inventor
Rabiul Islam
Avgerinos V Gelatos
Kevin Lucas
Stanley M Filipiak
Ramnath Venkatraman
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Motorola Inc
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Publication of TW418495B publication Critical patent/TW418495B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

In one embodiment, a copper interconnect structure is formed by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form interconnect openings (29). A layer of copper (34) is then formed within the interconnect openings (29). A portion of the copper layer (34) is then removed to form copper interconnects (39) within the interconnect openings (29). A copper barrier layer (40) is then formed overlying the copper interconnects (39). Adhesion between the copper barrier layer (40) and the copper interconnects (39) is improved by exposing the exposed surface of the copper interconnects (39) to a plasma generated using only ammonia as a source gas.

Description

M8495 五、發明說明（1 > 參考先前的申請案 該專利申請案乃以專利申請案編號〇9/〇55,5 10於1998年4 月6日於美國提出申請。 發明領域 該發明大致上乃係關於半導體裝置，且更爲特別地乃針 對位於一半導體裝置内的一種銅互連結構及其形成法。 發明背景 於半導體工業中，傳導性的互連在慣例上係利用鋁所形 成，然而，具有一阻抗低於鋁所給予者之傳導性互連現需 符合先進的半導體裝置之速度需求，銅基於它較低的阻抗 ’近來已被提議當成傳統的鋁互連的一種替代，銅不像鋁 ’乃於目前通常所使用於製造半導體裝置之許多材料中爲 高度機動性者。因此在半導體裝置中銅互連的使用需要使 用銅的障礙層以防止在該半導體裝置内不想要的銅擴散， 然而’該障蔽層對於銅互連的黏附力係有問題的且時常會 造成半導體裝置的失敗，所以對於允許得以可靠地改善製 造具備銅互連的半導體装置之金屬化製程存在一種需求。 簡單圖示説明 圖1至7以橫剖面圖舉例説明了根據本發明之一具體實例 的製程步驟。 詳細圖示説明 圖1中所顯示者乃爲根據本發明之一具體實例的—個半導 體裝置結構之一部份5，該半導體裝置結構包含一半導體基 質10，場隔離區域12，一電晶體14，傳導检24，一介電層 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 ίι — tlllilln — - — — If — — — * — — 1 — - — II - - (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 經濟部智慧財產局員工消費合作社印製 4 18495 A7 --—------ B7_____ 五、發明說明（2 ) 22，一蝕刻停止層26，和一介電層28 ,電晶體14包含源/没 極區域16，一閘極介電層18，和—閘極電極2〇，於一具體 實例之半導體基質10乃爲—單晶矽積質，半導體基質1〇在 替代上可爲一絕緣體上梦基質’一 Sapphire上带基質或類 似之物。 一具體實例中之場隔離區域12係爲排溝渠隔離區域.，其 乃是使用傳統的蝕刻法和化學機械的研摩技術所形成。在 替代上場隔離區域12可爲使用傳統的技術（像是矽的局部氧 化（LOCOS) ’聚緩衝LOCOS(PBL)，多矽囊形局部氧化 (PEL0X)或類似之物）所形成的場氧化物區域。 一具體實例中之閘極介電層】8可爲一層由一熱氧化部份 的基質1 〇所形成之熱矽二氧化物的層，在替代上閘極介電 層丨8可爲一矽氮化物層，一矽氮氧化物層，或一化學汽相 沉積矽二氧化物層，一氮化氧化物層，或其之—種個組合。 於一具體實例之閘極電極20係爲一是多矽層，在替代上 閘極電極20寸爲一金屬層（像是鎢或鉬），一金屬氮化物層 (像是妖氮化物或鎢氮化物），或者其之一種個組合，此外閘 極電極20可爲一聚合物層，包含一金屬矽石層（像是鎢矽石 ，鈦矽石，或鈷矽石覆蓋一多矽層）。 一具體實例中之介電層22係爲一電漿沉積氧化物，其乃 使用TE0S當成一源氣体所形成者。介電層22在替代上可爲 —石夕氣化物層，一 PSG層’一 BP$G層，一 S0G層，·—<5夕氮 氧化物層，一聚酿亞胺層，或其之一组合。 一具體實例中之傳導性栓24乃使用一鈦/鈦氮化物障蔽層 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） fl — fiii·裝 i!1ri!-線 〈請先間讀背面之注意事項再填寫本頁) A7 418495 ----------B7_____ 五、發明說明（3 ) η個鶴接觸填充加以形力。在該嫣的部分被沉積後，使 用傳統的蚀刻法或化學機械研磨技術移除置於其下之鈦/鈇 氮化物障蔽層以便形成傳導栓24，傳導栓24在替代上可使 用多矽當成一種接觸填充材料加以形成。 一具體實例中之蝕刻停止層26係爲一矽氮氧化物層，其 乃使用傳統的電漿沉積技術加以形成，蝕刻停止層26在替 代上可爲一電漿沉積矽氮化物層，一硼氮化物層，或類似 之物。 —具體實例中之介電層28係爲一層使用TEOS當成一源氣 体所形成之電漿沉積氧化物層，介電層28在替代上可爲一 矽氬化物層，一PSG層，一 81>3(}層，一 s〇G層，—矽氮化 物層，一聚醯亞胺層，或類似之物，此外該前面提及之介 電材料之一组合亦是通常可用於形成介電層28者。 圖2中，一部份的介電層28和—部份的蝕刻停止層％接著 被移除以便曝光—部份的傳導栓24和形成互連開口 29，一 傳導性的障蔽層3〇接著形成在互連開口 29之内，於一具體 實例中之傳導性的障蔽層3〇乃爲一層钽氮化物，傳導性的 障蔽層30在替代上可爲—鈦氮化物層，一鎢氮化物層，一 钽矽氮化物層，一钽層，一鈦化鎢層（Tiw)，或類似之物 ，傳導性的障蔽層3〇可使用傳統的濺鍍或化學汽相沉積技 術加以沉積。 一第一銅層32接著加以形成而覆蓋傳導性的障蔽層3〇 , 第一銅層32具有如圖2中所顯示不足以填充互連開口29之一 厚度，於一具體實例中之第一銅層32係用一種濺鍍沉積製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） till — ,--II--I i i I I I--訂-— — — — — , - <請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 418495 五、發明說明（4 ) 程所沉積，第-銅層32在替代上可用一化學汽相沉積製程 加以形成。 一電鍍的製程接著被用於形成—第二的銅層34而覆蓋第 —銅層32,第二鋼層34具有如圖2中所顯示足以填充互連開 口 29之厚度，於一具體實例中之第二的銅層34係使用包 括銅（Cu)，瓴酸銅（CU2S〇4)，硫酸（hjoj，與氣化物離子 (像是從氫氣酸（HC1)所得者）之一種電鍍溶液加 以沉積，於 此特別的具體實例中，該電流密度於銅電鍍製程期間在接 近该些半導體基質的邊緣處係加以改良以期改善該銅電鍍 之_一致性，如同敘述於美國申請專利申請案编號〇8/856 459 中所敘述者，其乃被予本專利申請案的受讓人，美國專利 申請案編號08/856,459的題材係表述地被結合於此當作參考 ，在替代上第二銅層3 4可使用其他的電鍍技術及其他電鍍 解決方式加以形成，此外第二銅層34可使用其他技術像是 化學汽相沉積方式加以形成。 於圖3中的部份第二銅層34，第一銅層32和傳導性的障蔽 層30係被移除以在互連開口 29内形成銅互連39，其中鋼互 連39包含傳導性障蔽層30的殘留部份％，第—銅層32的殘 留邵份37，和第一銅層34的殘留部份π，於一特殊具體實 例中’傳導性的障蔽層3〇包含鈦，鎢’或者鈕，鋼互連39 可使用包含氫過氧化物，氨鹽基檸檬酸鹽，礬土（氧化銘）， 丨，2’4-二氮氣’和去離子水之—块磨漿液之—化學機械研磨 製权加以形成，如被敌述於美國註册專利申請案編號 08/954,190中者，其乃被予本專利申請案的受讓人，美國專 本紙張义度適用中國國家標準（CNS)A4規柊（210 x 297公釐） — ---— — I— ^M-ilm — ί^ <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產居員工消費合作社印製 A7 _ B7 五、發明說明（5 ) 利申請案編號08/954,190的題材係表述地被結合於此當作參 考，銅互連39在替代上可以使用習知的蝕刻技術加以形成 ’諸如：離子束研磨，反應離子束银刻，與電漿蚀刻，或 使用蝕刻與研磨技術的組合。 包含矽和氮之一銅障蔽層4〇接著被形成於铜互連39之上 ’輕屢蔽層4〇用於防止銅互連39内之銅原子擴散進入後續 會加以沉積於鋼互連39上之介電層，於一具體實例中之銅 障蔽層40對於在或者低於365毫微米之下的光阻曝光波長具 有範圍大約爲0.0至約〇. 15之一吸收係數（k)，更特別地銅障 蔽層40具備對於365毫微米及248毫微米之光阻曝光波長處 具有範園從大約0.0到大約〇. 1 5之一吸收係數。 爲了改善位於銅互連39和銅障蔽層40間之黏附力，銅互 連39被曝光於包括氫氣之一無矽的電漿，包含氫之該無矽 的電漿使用一被供給至電漿室之一無矽源氣体或無矽源氣 體們加以製成，譬如，於一具體實例中之—含氫無矽電漿 僅使用氨氣（NH3)當作源氣体來加以產生，以便產生本質上 由氫和氮所組成之一電漿’於該特別的具體實例中.，本質 上由氫和氮所组成之該電漿係在以下的條件之下產生：約 8.0 torr的一個此積恩力；—大約4〇〇 sccm的氨氣流率；大 約200瓦之一RF功率；大約65〇密耳之一間隔，以及大約 攝氏400度之一沉積溫度，在替代上含氫之—無矽電漿可以 僅使用氫（h2)當作—源氣体或與如同氮氣，氦，或 者氬（Ar)的一種惰性源氣体加以產生，據信該電漿製程從銅 互連39的曝光表面除去銅氧化物，其可使銅障蔽層和铜 r---^------I---•裝 ----- I 訂·！—線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 18 A 9 5 A7.________B7___ 五、發明說明（6 ) 互連39間的黏著力退化，據信電漿中的氫與铜互連的表面 上之銅氧化物起反應以形成被抽出之揮發性水，且電疲中 之氮藉由衝撞該銅表面而有助於該銅氧化物的減少，此外 藉由在隨後的銅障蔽層沉積時於此相同的室内實行清洗製 程’該潔淨的銅表面不再次被暴露的到空氣中以及在沉積 前再次被氧化’應注意該先前提到的電漿製程可在不退化 銅互連的阻抗及不退化鄰接銅互連間的戍露電流而改善黏 附力。 於一具體實例中之銅障蔽層40係爲一矽氮氧化物 (SixOyNz) ’於此特別的具體實例中之銅障蔽層40係於下列 條件下在設有一DXZ室之一應用材料Centura電漿沉積系統 中加以形成·约5.0 torr的一個沉積壓力；—大約73 seem的 硅烷流率；約5>2 seem之一氮氧化物流率；大约3900 seem之 —氮氣流率；大約5〇〇瓦之一 RF功率；大約475密耳之一間 隔，以及大約攝氏400度之一沉積溫度，在約365毫微米之 一個光阻曝光波長下，前面所提及的矽氮化物層具有大約 爲1.66之一折射率和大約〇.〇的一個吸收係數。 於一替代的具體實例中之銅障蔽層40係爲一電漿沉積矽 氮化物（SisNy)，於此特別的具體實例中之銅障蔽層40係於 下列條件下在設有一 DXZ室之—應用材料Centura電漿沉積 系統中加以形成：约5·0 torr的一個沉積壓力；一大約100 seem的硅烷流率；約140 seem乏一氮氧化物流率；大約 4000 seem之一氮氣流率；大約450瓦之一RF功率；大約 6 10密耳之一間隔’以及大約攝氏400度之—沉積溫度’在 -9 * 本紙張尺度適用中國國家標準（cNS)A4規格（210 x 297公釐） t I I Γ — .1 1!1[11 ^ I I «Κ I Ί I I » — — —1 — — — — <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A 18 4 9 5 A7 ____B7五、發明說明（7 ) 約365毫微米之一個光阻曝光波長下，前面所提及的矽氮化 物層具有大約爲2·05之一折射率和大约〇·〇的一個吸收係數。 應注意銅障蔽層4〇可以可靠地與嵌入銅金屬化整合；因 爲其黏著於銅互連39及因其不致於反向影響銅互連39的阻 抗或位於鄰近嵌入銅互連間之淺漏電流，特別地在其由銅 障蔽層所遮蓋40時，已發現到分隔約2400埃之嵌入銅互連 間之洩漏電流係爲少於一毫微安培，所以本發明如亦允許 製成具備銅互連而具有低的洩漏電之流半導體裝置。 一具體實例中包含矽和氮之一抗反射層41接著形成對接 的銅障蔽層40，抗反射層41具有範圍大約爲5毫微米至100 毫微米之一厚度，抗反射層41對於在或者低於365毫微米之 下的光阻曝光波長具有範園大約爲0.2至約1.0之一吸收係數 (k) ’抗光阻層4 1特別地在365毫微米及248毫微米之光阻曝 光波長處具有範圍從大約0.2到大約1.0之一吸收係數，所以 對於相同的光阻曝光波長，銅障蔽層40將會有較抗反射層 4丨之吸收係數爲少的一個吸收係數。 —具體實例中之抗反射層4丨係爲一層矽氮化物（Six〇yNz) ，於此特殊的具體實例中之抗反射層4 1係於下列條件下在 設有一 DXZ室之一應用材料Centura電漿沉積系統中加以形 成：約5,0 torr的一個沉積壓力：一大約3〇〇 SCC1T1的硅烷流 率：約92 seem之一氮氧化物流率；大约39〇〇 sccmt_氮氣 流率：大約520瓦之一 RF功率；尖約475密耳之一間隔，以 及大約攝氏400度之一沉積溫度，在约365毫微米之一個光 阻曝光波長下’前面所提及的矽氮化物層具有大約爲2 8之 10- ΓΙΙΓί — Ι— ! — — -Hr — — —— ^ *[ — —1 — — !— (請先閱讀背面之注項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4 184 95 a7 一_____ B7_ 五、發明説明（8 ) 一折射率和大約0.3的一個吸收係數。 應瞭解該銅障蔽層40和抗反射層4 1的光學性質可個別地 藉由調整其各自的沉積製程流來加以整理，譬如，若以上 所檢討而用於沉積該抗反射層41的之硅烷流率被改變為大 約330 seem時，此舉導致處於約365毫微米之一光阻曝光波 長處具有約〇·40的一個吸收係數，抗反射層41的吸收係數因 較高硅烷流率增加了在矽氮氧化物層中的矽濃度而增加， 相似地減少該娃燒流率將減少在夕氮氧化物層中的矽濃度 以及減少其吸收係數，所以抗反射層41和鋼障蔽層40的光 學性質可以獨立地加以整理，譬如，銅障蔽層40能被形成 為具有較抗反射層41之矽濃度為少之一矽濃度，且因此該 鋼障蔽層40可具有一吸收係數較用於相同光阻曝光波長之 抗反射層41者為小，此外，應注意除了矽以外，氧和氮可 層被包含於該矽氮氧化物中而用於形成銅障蔽層40及抗反 射層41，更進一步地說除了矽和氮的成份可被包含於該矽 氮化物層中用於形成銅障蔽層40，譬如，氫可出現於此等 氮化物層中。 一中階介電層48係形成於抗反射層41上，於一具體實例 中之中階介電層48包含介電層42，蝕刻停止層44和介電層 46，如同顯示於圖4中者。 介電層42可為一電漿沉積氧化物層，其可使用te〇S當成 一源氣体來加以形成，介電層42-在替代上可為一PSG層，一 BPSG層，一SOG層，一聚醯亞胺層，一低介電性常數隔離 器，或類似之物3 -11 - 本紙張尺度適h中國國家標準（CNS ) Λ4規格公赛） --- ----------裝--------訂------一-線 {請先閱讀背面之注意事項再填寫本頁) A7 4 18493 ____B7 五、發明説明（9 ) 蝕刻停止層44可為一電漿沉積矽氮氧化物層，蝕刻停止 層44在替代上可為一電漿沉積矽氮化物層，—硼氮化物層 或類似之物。 介電層46可為一電漿沉積氧化物層，其使用te0S當作一 源氣体來加以形成，介電層46在替代上可為一PSG層’一 BPSG的層，一 SOG層，一聚醯亞胺層，—低介電性常數隔 離器’或類似之物’應瞭解中階介電層48毋需使用不同的 介電性材料加以形成’譬如，中階介電層48可使用一個單 一介電性的物質，諸如··電漿沉積氧化物，pS(3，BPSG， SOG ’聚醯亞胺’一低介電常數隔離器或類似之物加以形 成。 一光阻遮罩51接著形成於介電層48上，光阻遮罩51使用 具有一受選擇光阻曝光波長，諸如：365毫微米或248毫微 米的電磁輕射來加以形成’須知抗反射層41減少了在光阻 遮罩51中的反射刻槽，其可導致在高度反射銅互連39上之 光阻被平版刻法所曝光’光阻遮罩5丨接著被用至佈型如圖5 中所顯示之一部份位於其下之介電層48，更特別地係一部 分的介電層46與蝕刻停止層44受到移除以於介電層48中形 成一互連開口 52 ’光阻遮罩51在互連開口 52形成之後接著 加以移除。 於圖6中’一光阻遮罩53接著形成於介電層48上，光阻遮 罩53使用具有一受選擇光阻曝光波長，諸如：365毫微米或 248愛微米的電磁輻射來加以形成，須知抗反射層4丨減少了 在光阻遮罩53中的反射刻槽，其可導致在高度反射銅互連 -12- 本紙張尺度賴 fcNS ) A4^m ( 2I0X297/av# ) ----------扯衣----------IT------—線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智葸財產局員工消費合作社印製 經濟部晳慧財產局員K消費合作社印製 A 18495 ;、發明説明（10 ) ---- 39上<光阻被平版刻法所曝光，光阻遮罩53接著被用至侔 型如圖6中所顯示之—部份位於其下之介電層“，更特別地 係-部分的介電層42,抗反射層41以及銅障蔽㈣係受到 移除以便形成曝露一部份銅互連39之—通孔開口 Η，此舉 亦導致在於介電層48中形成一雙嵌入開口5〇，其中雙嵌入 開口 50包含互連部份52與通孔部份54 ,光阻遮罩53接著係 在中形成一雙嵌入開口 50於介電層48中形成之後接著加以 移除。 於圖7中，一第二導電障蔽層係接著被形成於雙嵌入開口 5〇义内，該第二傳導障蔽層於一具體實例中係為—層钽氮 化物。該第二傳導性的障蔽層在替代上可為—鈦氮化物層 ’ 一鶴氮化物層，一鈕矽氮化物層，一妲層，一鈦化鶏層 (TiW) ’或類似之物’該第二傳導性的障蔽層可使用傳統的 濺鍍或化學蒸氣沉積技術加以沉積。 一第三鋼層係接著加以形成而覆蓋該第二傳導性的障蔽 層’該第三鋼層具有如圖7中所顯示不足以填充雙嵌入開口 50之一厚度，於—具體實例中之第三銅層係用一種濺鍍沉 積製程所沉積。該第三銅層在替代上可用一化學蒸氣沉積 製程加以形成。 一電鍍的製程接著被用於形成一第四銅層而覆蓋第三銅 層’該第四鋼層具有足以填充雙嵌入開口 5〇之一厚度，於 一具體實例中之第四銅層係使用包括銅（Cu)，硫酸銅 (CuzSO4)，硫酸（h2S04)，與氣化物離子（像是從氫氣酸 (HC1)所得者）之一種電鍍溶液加以沉積，於此特別的具體實 -13- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ------裝------1T------^ f請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ^ 18 4 9 5 A7 ___ B7 五、發明說明（11 ) 例中，該電流笛度於銅電鍵製程期間在接近該些半導體基 質的邊緣處係加以改良以期改善該銅電鍍之一致性，如同 敘述於美國申請專利申請案編號08/856,459中所敘述者，其 乃被予本專利申凊案的受讓人’美國專利申請案編號 0δ/856,459的題材係表述地被結合於此當作參考，在替代上 第四銅層可使用其他的電鍍技術及其它的電鍍解決方式加 以形成’此外第二銅層3 4可使用其他技術像是化學蒸汽沉 積方式加以形成。 第四銅層之邵份，第三銅層和第二傳導性的障蔽層係接 著被移除以在雙嵌入開口 50内形成銅互連62，其中銅互連 62包含第二傳導性障蔽層的殘留部份57，第三銅層的殘留 部份59 ’和第四銅層的殘留部份60，於—特殊具體實例中 ，其中第二傳導性的障蔽層包含鈦，鎢，或者钽，鋼互連 62可使用包含氫過氧化物，氨鹽基檸檬酸鹽’礬土（氧化鋁） ，1,2,4-二氮氣，和去離子水之一研磨漿液之—化學機械研 磨製程加以形成，如被敍述於美國註册專利申請案编號 0S/954，190中者，其乃被予本專利申請案的受讓人，美國專 利申請案編號08/954,190的題材係表述地被結合於此當作參 考’銅互連62在替代上可以使用習知的蝕刻技術加以形成 ’諸如··離子束研磨，反應離子束蚀刻，與電漿蝕刻，或 使用蝕刻與研磨技術的纽合。 包含矽和氮之一銅障蔽層64接·著被形成於銅互連62之上 ’如先妁於圖3中加以敘述者，若不需額外的互連層，則銅 障蔽層64接著充當—最後的裝置被動層而黏接墊開口（未顯 -14 - 本紙張尺度適用中國國家標準（CNS)A4規格（21〇x 297公釐） IIIH III1— — — — - 1 I ί I I 1 I ^ ·!111111> (請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（12 示）後續經由此加以形式，在替代上若需額外的互連層，則 接著要重覆執行圖3到圖7中所述的步驟。 所以很明顯地根據本發明此處已提供了一金屬化製程， 其容許了使銅互連可信賴地製造半導體装置，雖然該發明 已於此加以敘述且參考特定具體實例加以說明’然而本發 明並不為此等舉例說明的具體實例所限，對於熟習於此技 藝者將認識到可在不偏離本發明的精神與範園之下作成各 種改良與變化’因此本發明意圖涵蓋所有落在隨附之申請 專利範圍内之變化與改良。 元件對照表 semiconductor substrate 丰導體基質 10 interconnect opening 互連開口 29 copper layer 銅層 34 copper interconnect 翻互連 39 field isolation region 場隔離區域12 transistor 電晶體 14 conductive plug 傳導检24 source/drainregion 源/汲極區域 16 gate dielectric layer 閘極介電層 18 gatee丨ectrode閘極電極20 conductive barrier layer 傳導性的障蔽層 3〇 first copper layer 第一銅層 32 second copper layer 第二銅層 34 remaining portion 殘留部份36,37,38 antireflective layer 抗反射層 41 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） J n n I ^^1 t^i I 1^1 1 (請先閱讀背面之注意事項再填寫本頁) A7 4 18495 〜——·—. ___B7 ___ 五、發明説明（13 ) interlevel dielectric layer 中階介電層 48 dilectric layer 介電層 22,28,42,46,48 etch stop layer 蝕刻停止層 26,44 photoresist mask 光阻遮罩51,53 interconnect opening互連開口 52 via opening 通孔開口 54 dual inlaid opening 雙振入開口 50M8495 V. Description of the invention (1 > Reference to the previous application The patent application was filed in the United States on April 6, 1998 under the patent application number 09/055, 5 10. Field of the invention The invention is roughly It relates to semiconductor devices, and more particularly to a copper interconnect structure and a method of forming the same within a semiconductor device. BACKGROUND OF THE INVENTION In the semiconductor industry, conductive interconnects are conventionally formed using aluminum, However, a conductive interconnect with a resistance lower than that given by aluminum now needs to meet the speed requirements of advanced semiconductor devices. Copper is based on its lower impedance. 'Recently, copper has been proposed as an alternative to traditional aluminum interconnects. Unlike aluminum, it is highly mobile among many materials currently used to make semiconductor devices. Therefore, the use of copper interconnects in semiconductor devices requires the use of copper barrier layers to prevent unwanted effects in the semiconductor device. Copper diffusion, however, 'the barrier layer's adhesion to copper interconnects is problematic and often causes failure of semiconductor devices, so it is possible to allow There is a need to improve the metallization process for manufacturing semiconductor devices with copper interconnects on the ground. Simple illustrations Figures 1 to 7 illustrate the process steps according to a specific example of the present invention in cross-sectional views. Detailed illustrations Shown in 1 is a part 5 of a semiconductor device structure according to a specific example of the present invention. The semiconductor device structure includes a semiconductor substrate 10, a field isolation region 12, a transistor 14, a conduction test 24, A dielectric layer-4- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) ίι — tlllilln —-— — If — — — * — — 1 — — — II--(Please first (Please read the notes on the back and fill in this page again.) Consumption cooperation between employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, 4 18495 A7 -------------- B7_____ V. Description of the invention (2 22), an etch stop layer 26, and a dielectric layer 28, the transistor 14 includes a source / inverted region 16, a gate dielectric layer 18, and a gate electrode 20, in a specific example semiconductor substrate 10 is for-single crystal As a substitute, the semiconductor substrate 10 may instead be a substrate on an insulator, a substrate on the Sapphire, or the like. The field isolation region 12 in a specific example is a trench isolation region. It can be formed by the etching method and the chemical mechanical research technology. In the alternative field isolation region 12 can be the use of traditional techniques (such as local oxidation of silicon (LOCOS) 'Poly buffered LOCOS (PBL), polysilicon-shaped local oxidation (PEL0X ) Or the like). The gate dielectric layer in a specific example] 8 may be a layer of thermal silicon dioxide formed by a thermally oxidized portion of the substrate 10, In place of the upper gate dielectric layer, the layer 8 may be a silicon nitride layer, a silicon oxynitride layer, or a chemical vapor deposition silicon dioxide layer, a nitrided oxide layer, or one of them. combination. In a specific example, the gate electrode 20 is a polysilicon layer. In place of the upper gate electrode 20 inches, it is a metal layer (such as tungsten or molybdenum) and a metal nitride layer (such as demon nitride or tungsten). Nitride), or a combination thereof, in addition, the gate electrode 20 may be a polymer layer including a metal silica layer (such as tungsten silica, titanium silica, or cobalt silica over a multiple silicon layer) . The dielectric layer 22 in a specific example is a plasma-deposited oxide formed by using TEOS as a source gas. The dielectric layer 22 may alternatively be a Shixi gaseous layer, a PSG layer, a BP $ G layer, a SOG layer, < 5 Nitrogen oxide layer, a polyimide layer, or One combination. In a specific example, the conductive plug 24 uses a titanium / titanium nitride barrier layer. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) fl — fiii · pack i! 1ri! -Line (Please read the precautions on the back first and then fill out this page) A7 418495 ---------- B7_____ V. Description of the invention (3) η cranes fill and exert force. After this portion is deposited, the titanium / rhenium nitride barrier layer underneath is removed using conventional etching or chemical mechanical polishing techniques to form a conductive plug 24. The conductive plug 24 may instead be made of polysilicon. A contact filling material is formed. In a specific example, the etch stop layer 26 is a silicon oxynitride layer, which is formed using a conventional plasma deposition technique. The etch stop layer 26 may instead be a plasma deposited silicon nitride layer, a boron A nitride layer, or the like. —The dielectric layer 28 in the specific example is a plasma-deposited oxide layer formed using TEOS as a source gas. The dielectric layer 28 may alternatively be a silicon argon layer, a PSG layer, and 81 > 3 () layer, a SOG layer, a silicon nitride layer, a polyimide layer, or the like, in addition, a combination of the aforementioned dielectric materials is also commonly used to form a dielectric layer 28. In Figure 2, a portion of the dielectric layer 28 and—a portion of the etch stop layer% are then removed for exposure—a portion of the conductive plug 24 and an interconnect opening 29, a conductive barrier layer 30 is then formed within the interconnect opening 29. In one embodiment, the conductive barrier layer 3 is a tantalum nitride, and the conductive barrier layer 30 may instead be a titanium nitride layer. A tungsten nitride layer, a tantalum silicon nitride layer, a tantalum layer, a tungsten titanium layer (Tiw), or the like, and a conductive barrier layer 30 may be applied using conventional sputtering or chemical vapor deposition techniques. A first copper layer 32 is then formed to cover the conductive barrier layer 30, and the first copper layer 32 has As shown in FIG. 2, the thickness is not enough to fill one of the interconnect openings 29. In a specific example, the first copper layer 32 is made by a sputter deposition. The paper size is applicable to China National Standard (CNS) A4 (210 X 297). (Public love) till —, --II--I ii II I--Order-— — — — — —, < Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 418495 V. Description of the invention (4) The first copper layer 32 can be formed by a chemical vapor deposition process instead. An electroplating process is then used to form a second copper layer 34 and cover the first copper layer 32. The second steel layer 34 has a thickness sufficient to fill the interconnect openings 29 as shown in FIG. 2, in a specific example The second copper layer 34 is deposited using a plating solution including copper (Cu), copper citrate (CU2S04), sulfuric acid (hjoj, and gaseous ions, such as those obtained from hydrogen acid (HC1)). In this particular specific example, the current density is improved near the edges of the semiconductor substrates during the copper plating process to improve the consistency of the copper plating, as described in the US patent application number. The subject matter described in 8/856 459 is the assignee of this patent application. The subject matter of U.S. Patent Application No. 08 / 856,459 is expressly incorporated herein by reference, in place of the second copper layer. 3 4 can be formed using other electroplating techniques and other plating solutions. In addition, the second copper layer 34 can be formed using other techniques such as chemical vapor deposition. Part of the second copper layer 34 in FIG. A copper layer 32 and conduction The barrier layer 30 is removed to form a copper interconnect 39 within the interconnect opening 29, wherein the steel interconnect 39 contains a residual portion of the conductive barrier layer 30, a residual portion 37 of the first copper layer 32, and Residual portion π of the first copper layer 34. In a specific embodiment, the “conductive barrier layer 30 contains titanium, tungsten” or a button, and the steel interconnect 39 may include a hydroperoxide and an ammonium citrate. Salt, bauxite (oxidized inscription), 丨, 2'4-dinitrogen 'and deionized water-block grinder-chemical mechanical grinding control rights, as described in the US registered patent application number 08 / Of the 954,190, it is the assignee of this patent application. The US paper speciality applies to the Chinese National Standard (CNS) A4 Regulation (210 x 297 mm) — --- — — I — ^ M -ilm — ί ^ < Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Printed by the Consumer Cooperative of the Ministry of Economic Affairs Printed by the Intellectual Property of the Ministry of Economic Affairs, Printed by the Consumer Cooperative of A7 _ B7 The subject matter of application number 08 / 954,190 is expressly incorporated herein by reference, Combination of ion beam milling, reactive ion beam engraved silver, and plasma etching, and polishing or etching technique: an interconnect 39 may be formed "such as using conventional etching techniques in the alternative. A copper barrier layer 40 containing silicon and nitrogen is then formed on the copper interconnect 39. A light shielding layer 40 is used to prevent copper atoms in the copper interconnect 39 from diffusing into the copper interconnect 39 and is subsequently deposited on the steel interconnect 39. The above dielectric layer, the copper barrier layer 40 in a specific example has an absorption coefficient (k) in the range of about 0.0 to about 0.15 for a photoresist exposure wavelength below or below 365 nm, and more In particular, the copper barrier layer 40 has an absorption coefficient having a range from about 0.0 to about 0.15 for the photoresist exposure wavelengths of 365 nm and 248 nm. In order to improve the adhesion between the copper interconnect 39 and the copper barrier layer 40, the copper interconnect 39 was exposed to a silicon-free plasma including hydrogen, and the silicon-free plasma containing hydrogen was fed to a plasma chamber using a silicon-free plasma. A silicon-free source gas or silicon-free source gas, for example, in a specific example-a hydrogen-containing silicon-free plasma using only ammonia (NH3) as the source gas to generate A plasma consisting of hydrogen and nitrogen 'is used in this particular embodiment. The plasma consisting essentially of hydrogen and nitrogen is produced under the following conditions: a productive force of about 8.0 torr ;-Ammonia flow rate of about 400 sccm; RF power of about 200 watts; interval of about 65 mils; and deposition temperature of about 400 degrees Celsius; in the alternative hydrogen-free silicon plasma It can be generated using only hydrogen (h2) as a source gas or with an inert source gas such as nitrogen, helium, or argon (Ar). The plasma process is believed to remove copper oxide from the exposed surface of copper interconnect 39 , Which can make copper barrier layer and copper r --- ^ ------ I --- • installation ----- I ·! —Line (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 18 A 9 5 A7 .________ B7___ V. Description of the invention (6) The adhesion between the 39 interconnects is degraded, according to The hydrogen in the plasma reacts with the copper oxide on the surface of the copper interconnect to form the extracted volatile water, and the nitrogen in the electrical fatigue contributes to the reduction of the copper oxide by impacting the copper surface. In addition, by performing a cleaning process in the same room during subsequent copper barrier layer deposition, 'the clean copper surface will not be exposed to the air again and will be oxidized again before deposition' should be noted that the previously mentioned electrical The slurry process can improve the adhesion without degrading the impedance of the copper interconnect and degrading the exposure current between adjacent copper interconnects. The copper barrier layer 40 in a specific example is a silicon oxynitride (SixOyNz). The copper barrier layer 40 in this particular specific example is under the following conditions. A Centura plasma is used as one of the DXZ chambers. A deposition pressure of about 5.0 torr is formed in the deposition system; a silane flow rate of about 73 seem; a nitrogen oxide flow rate of about 5 > 2 seem; a nitrogen flow rate of about 3900 seem; a nitrogen flow rate of about 500 watts An RF power; an interval of approximately 475 mils, and a deposition temperature of approximately 400 degrees Celsius at a photoresist exposure wavelength of approximately 365 nanometers, the aforementioned silicon nitride layer has approximately one of 1.66 Refractive index and an absorption coefficient of about 0.00. The copper barrier layer 40 in an alternative specific example is a plasma deposited silicon nitride (SisNy). The copper barrier layer 40 in this particular specific example is provided in a DXZ chamber under the following conditions-application Materials are formed in a Centura plasma deposition system: a deposition pressure of about 5.0 torr; a silane flow rate of about 100 seem; a flow rate of about 140 seemingly a nitrogen oxide; a nitrogen flow rate of about 4000 seem; a flow rate of about 450 One watt of RF power; approximately 6 to 10 mils at intervals 'and approximately 400 degrees Celsius-deposition temperature' at -9 * This paper size applies to China National Standard (cNS) A4 (210 x 297 mm) t II Γ — .1 1! 1 [11 ^ II «Κ I Ί II» — — — 1 — — — — < Please read the notes on the back before filling out this page) 18 4 9 5 A7 ____B7 V. Description of the invention (7) At a photoresist exposure wavelength of about 365 nanometers, the aforementioned silicon nitride layer has a refractive index of about 2.05 and a refractive index of about 0.0 An absorption coefficient. It should be noted that the copper barrier layer 40 can be reliably integrated with the embedded copper metallization; because it is adhered to the copper interconnect 39 and because it does not adversely affect the impedance of the copper interconnect 39 or a shallow leak between adjacent embedded copper interconnects The current, particularly when it is covered by a copper barrier layer 40, has been found to have leakage currents of less than one nanoampere between the embedded copper interconnects separating about 2400 Angstroms, so the present invention is also allowed to be made with copper Interconnected semiconductor devices with low leakage current. A specific example includes an anti-reflection layer 41 of silicon and nitrogen, and then forms an abutting copper barrier layer 40. The anti-reflection layer 41 has a thickness ranging from about 5 nanometers to 100 nanometers. The photoresist exposure wavelength below 365 nm has an absorption coefficient (k) of about 0.2 to about 1.0. The photoresist layer 41 is particularly at the photoresist exposure wavelengths of 365 nm and 248 nm. It has an absorption coefficient ranging from about 0.2 to about 1.0, so for the same photoresist exposure wavelength, the copper barrier layer 40 will have an absorption coefficient that is less than the absorption coefficient of the anti-reflection layer 4. —The anti-reflection layer 4 in the specific example is a layer of silicon nitride (SixoyNz). In this particular specific example, the anti-reflection layer 4 1 is provided in one of the DXZ chambers under the following conditions. Formed in the plasma deposition system: a deposition pressure of about 5,0 torr: a silane flow rate of about 300 SCC1T1: a nitrogen oxide flow rate of about 92 seem; about 3900 scmtt_ nitrogen flow rate: about RF power of 520 watts; tip spacing of approximately 475 mils, and deposition temperature of approximately 400 degrees Celsius at a photoresist exposure wavelength of approximately 365 nanometers' The silicon nitride layer previously mentioned has approximately It is 10 of 2 8- ΓΙΙΓί — Ι—! — — -Hr — — —— ^ * [— —1 — —! — (Please read the note on the back before filling out this page) This paper size applies to Chinese national standards ( CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 184 95 a7 A _____ B7_ 5. Description of the invention (8) A refractive index and an absorption coefficient of about 0.3. It should be understood that the optical properties of the copper barrier layer 40 and the anti-reflection layer 41 can be individually adjusted by adjusting their respective deposition process flows, for example, the silane used to deposit the anti-reflection layer 41 as reviewed above When the flow rate was changed to about 330 seem, this resulted in an absorption coefficient of about 0.40 at a photoresist exposure wavelength of about 365 nm, and the absorption coefficient of the anti-reflection layer 41 increased due to the higher silane flow rate. The silicon concentration in the silicon oxynitride layer increases, and similarly reducing the silicon firing flow rate will reduce the silicon concentration in the oxynitride layer and reduce its absorption coefficient, so the anti-reflection layer 41 and the steel barrier layer 40 The optical properties can be independently sorted, for example, the copper barrier layer 40 can be formed to have a silicon concentration less than that of the anti-reflection layer 41, and therefore the steel barrier layer 40 can have an absorption coefficient more suitable for the same The photoresist exposure wavelength of the anti-reflection layer 41 is small. In addition, it should be noted that in addition to silicon, oxygen and nitrogen can be included in the silicon oxynitride for forming the copper barrier layer 40 and the anti-reflection layer 41. further In addition to said nitrogen and silicon components may be contained in the silicon nitride layer 40 for forming a copper layer vasospasm, for example, hydrogen and the like may be displayed in this nitride layer. A middle-order dielectric layer 48 is formed on the anti-reflection layer 41. In a specific example, the middle-order dielectric layer 48 includes a dielectric layer 42, an etch stop layer 44 and a dielectric layer 46, as shown in FIG. By. The dielectric layer 42 may be a plasma-deposited oxide layer, which may be formed using teOS as a source gas. The dielectric layer 42 may alternatively be a PSG layer, a BPSG layer, a SOG layer, A polyimide layer, a low dielectric constant isolator, or the like 3 -11-This paper is suitable for the Chinese National Standard (CNS) Λ4 Specification Competition) --- ------- --- Installation -------- Order ------ One-line {Please read the precautions on the back before filling this page) A7 4 18493 ____B7 V. Description of the invention (9) Etching stop layer 44 A silicon oxynitride layer may be deposited for a plasma, and the etch stop layer 44 may instead be a silicon nitride layer, a boron nitride layer, or the like for a plasma. The dielectric layer 46 may be a plasma-deposited oxide layer, which is formed using te0S as a source gas. The dielectric layer 46 may instead be a PSG layer, a BPSG layer, a SOG layer, and a polymer layer.醯 Imine layer,-low dielectric constant isolator 'or similar' should understand that the middle-order dielectric layer 48 does not need to be formed using different dielectric materials. For example, the middle-order dielectric layer 48 may use one A single dielectric substance, such as a plasma-deposited oxide, pS (3, BPSG, SOG 'Polyimide', a low dielectric constant isolator, or the like is formed. A photoresist mask 51 follows Formed on the dielectric layer 48, the photoresist mask 51 is formed using an electromagnetic light having a selected photoresist exposure wavelength, such as: 365 nm or 248 nm. 'Notice that the anti-reflection layer 41 reduces the photoresist The reflective notch in the mask 51 can cause the photoresist on the highly reflective copper interconnect 39 to be exposed by the lithography method. The photoresist mask 5 丨 is then used as a cloth pattern as shown in FIG. 5 A portion of the dielectric layer 48 below it, more specifically a portion of the dielectric layer 46 and the etch stop layer 44 The photoresist mask 51 is removed to form an interconnect opening 52 in the dielectric layer 48. The photoresist mask 51 is then removed after the interconnect opening 52 is formed. In FIG. 6, a photoresist mask 53 is then formed in the dielectric. On layer 48, the photoresist mask 53 is formed using electromagnetic radiation having a selected photoresist exposure wavelength, such as: 365 nanometers or 248 micrometers. It should be noted that the antireflection layer 4 is reduced in the photoresist mask 53. Reflective grooves, which can lead to highly reflective copper interconnects -12- This paper is based on fcNS) A4 ^ m (2I0X297 / av #) ---- IT -------- line (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumers Cooperative of the Ministry of Economic Affairs K Printed by A 18495 ; Description of the invention (10) ---- 39 on the photoresist is exposed by the lithography method, and the photoresist mask 53 is then used to form a pattern as shown in FIG. 6-partly below it The "electrical layer", more particularly-a portion of the dielectric layer 42, the anti-reflection layer 41, and the copper barrier are removed to form an exposed portion of the copper interconnect 39-the via opening. This also results in the formation of a double embedded opening 50 in the dielectric layer 48. The double embedded opening 50 includes an interconnecting portion 52 and a through hole portion 54. The photoresist mask 53 is then tied to form a double embedded opening 50. It is removed after being formed in the dielectric layer 48. In FIG. 7, a second conductive barrier layer is then formed in the double-embedded opening 50, and the second conductive barrier layer is in a specific example as -A layer of tantalum nitride. The second conductive barrier layer may instead be-a titanium nitride layer '-a crane nitride layer, a silicon nitride layer, a hafnium layer, a hafnium titanium layer (TiW) 'Or similar' The second conductive barrier layer can be deposited using conventional sputtering or chemical vapor deposition techniques. A third steel layer is then formed to cover the second conductive barrier layer. The third steel layer has a thickness as shown in FIG. 7 that is not sufficient to fill the double embedding opening 50. The three copper layers are deposited using a sputtering deposition process. The third copper layer may alternatively be formed by a chemical vapor deposition process. An electroplating process is then used to form a fourth copper layer to cover the third copper layer. The fourth steel layer has a thickness sufficient to fill the double-embedded opening 50, and is used in the fourth copper layer in a specific example. Including copper (Cu), copper sulfate (CuzSO4), sulfuric acid (h2S04), and a plating solution of gaseous ions (such as those obtained from hydrogen acid (HC1)) is deposited, which is specifically described here. Paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) ------ installation ----- 1T ------ ^ f Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 18 4 9 5 A7 ___ B7 V. Description of the Invention (11) In the example, the current flute is improved near the edges of the semiconductor substrates during the copper bonding process in order to improve it. Improving the consistency of this copper plating, as described in U.S. Patent Application No. 08 / 856,459, is the subject matter of the assignee of this patent application, U.S. Patent Application No. 0δ / 856,459 It is expressly incorporated herein by reference, in the alternative A copper plating layer may use other techniques and other solution applied to form a plated 'Furthermore, the second copper layer 34 may use other techniques such as chemical vapor deposition manner be formed. The components of the fourth copper layer, the third copper layer, and the second conductive barrier layer are then removed to form a copper interconnect 62 within the dual embedded opening 50, where the copper interconnect 62 includes a second conductive barrier layer. The remaining portion 57 of the third copper layer 59 'and the remaining portion 60 of the fourth copper layer 60, in a particular embodiment, wherein the second conductive barrier layer includes titanium, tungsten, or tantalum, The steel interconnect 62 may be formed by a chemical mechanical polishing process using a slurry containing hydroperoxide, ammonium citrate, alumina (alumina), 1, 2, 4-dinitrogen, and deionized water. Formed, as described in US registered patent application number 0S / 954,190, which is assigned to the assignee of this patent application, the subject matter of US patent application number 08 / 954,190 is expressly incorporated in This is taken as a reference 'the copper interconnect 62 may alternatively be formed using conventional etching techniques' such as ion beam polishing, reactive ion beam etching, plasma etching, or a combination of etching and polishing techniques. A copper barrier layer 64 containing one of silicon and nitrogen is then formed on the copper interconnect 62. As described earlier in FIG. 3, if no additional interconnect layer is required, the copper barrier layer 64 then acts as —Final device passive layer with adhesive pad opening (not shown -14-This paper size applies to China National Standard (CNS) A4 (21〇x 297 mm) IIIH III1 — — — —-1 I ί II 1 I ^ !! 111111 > (Please read the notes on the back before filling out this page) A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy , Then the steps described in Figures 3 to 7 are repeated. So it is clear that a metallization process has been provided here in accordance with the present invention, which allows copper interconnects to be reliably manufactured Semiconductor device, although the invention has been described herein and described with reference to specific examples, however, the invention is not limited to the specific examples illustrated, and those skilled in the art will recognize that the present invention can be implemented without departing from the present invention. Spirit of Fan Yuanzhi Make various improvements and changes' Therefore, the present invention intends to cover all changes and improvements falling within the scope of the attached patent application. Component comparison table semiconductor substrate 10 conductor opening 29 interconnect layer 29 copper layer copper layer 34 copper interconnect 39 field isolation region 12 transistor transistor 14 conductive plug 24 source / drainregion source / drain region 16 gate dielectric layer gate dielectric layer 18 gatee ectrode gate electrode 20 conductive barrier layer Layer 30 First copper layer 32 Second copper layer 34 Second portion 34 remaining portion 36,37,38 antireflective layer 41 -15- This paper standard applies to China National Standard (CNS) A4 (210 X 297 mm) J nn I ^^ 1 t ^ i I 1 ^ 1 1 (Please read the notes on the back before filling in this page) A7 4 18495 ～ —— · ——. ___B7 ___ V. Description of the invention ( 13) interlevel dielectric layer 48 dilectric layer dielectric layer 22,28,42,46,48 etch stop laye r Etch stop layer 26,44 photoresist mask 51,53 interconnect opening 52 via opening 54 dual inlaid opening 50

Remaining portion of the second conductive barrier layer 第 二傳導性障蔽層的殘留部份57 Remaining portion of the third copper layer 第三鋼層的殘留 部份59Remaining portion of the second conductive barrier layer 57 Remaining portion of the third conductive layer 59

Remaining portion of the fourth copper layer 第四趣]層的殘 留部份60Remaining portion of the fourth copper layer

Copper barrier layer 銅障蔽層 64 1-----------^裝----I--丨訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 適 一度 尺 張 紙 本 釐一公97 2 X 10 2 /V 格 規 A4 S) N {C 標-Copper barrier layer 64 1 ----------- ^ install ---- I-- 丨 order --------- line (Please read the precautions on the back before filling (This page) Consumption cooperation between employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, Du printed a one-degree ruled paper, one centimeter 97 2 X 10 2 / V, A4 S) N (C standard-

Claims (1)

經濟部中央標準局貝工消費合作社印裝 4 184 9d A 05 3^g a» C8 —----------D8 六、申請專利範圍 l -種用於在一半導體裝置内形成一飼互連結構的方法， 包括以下步驟： 提供一半導體基質； 於半導體基質之上形成一介電層； 佈型該介電層以便在介電層之内形成一開口； 於該半導體基質之上形成一銅層，銅層位於該開口之 内； 研磨該鋼層以便在開口之内形成一銅互連’該銅互連 具有一上表面； 將菽銅互連曝露於一含氫之電漿下以便從銅互連之上 表面移除銅氧化物並形成一潔淨之上表面；以及 於該潔淨上表面上形成一鋼障蔽層，其中該潔淨上表 面在形成銅障蔽層之前不再加以氧化。 2.—種用於在一半導體裝置内形成一銅互連結構的方法， 包括以下步驟： 提供一半導體基質； 於半導體基質之上形成一介電層； 佈型該介電層以便在介電層之内形成„開口； 於遠半導體基質之上形成一銅層’銅層位於該開口之 内； 研磨該銅層以便在開口之内形成一銅互連，該鋼互連 具有一上表面； 從銅互連之上表面移除銅氧化物並形成一潔淨上表面 ;以及 -17- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ¾------ΐτ------,ii (請先閣讀背面之注意事項再填寫本頁) 經濟部十央梯準局員工消費合作社印裝 A18495 B8 ， ___ D8____ 六、申請專利範圍 於該潔淨上表面上形成一銅障蔽層。 3. —種用於在一半導體裝置内形成一鋼互連結構的方法， 包括以下步驟： 提供一半導體基質； 於半導體基質之上形成一介電層； 佈型該介電層以便在介電層之内形成一開口； 於該半導體基質之上形成一銅層，铜層位於該開口之 内； 研磨該鋼層以便在開口之内形成一銅互連，該鋼互連 具有一上表面； 將該銅互連曝露於一含氫及氮之電漿下以便從銅互連 之上表面移除鋼氧化物並形成一潔淨之上表面；以及 於遠潔淨上表面上形成一銅障蔽層，其中該潔淨上表 面在形成銅障蔽層之前不再加以氧化。 4. 一種用於在一半導體裝置内形成一銅互連結構的方法， 包括以下步驟： 提供一半導體基質； 於半導體基質之上形成一介電層； 体型該介電層以便在介電層之内形成一開口； 於该半導體基質之上形成一銅層，銅層位於該開口之 内； 研磨該鋼層以便在開口之内形成一銅互連，該飼互連 具有一上表面； 將該銅互連曝露於一含氫之無矽電漿下以便從銅互連 -18- 本紙張尺度適用中國®家樣準（CNS ) Α4；ί^ ( 210X297公釐） --r--------^------.玎-------線 (請先閲讀背面之注意事項再填寫本頁) ABCD 418495 六、申請專利範圍 之上表面移除銅氧化物並形成一潔淨上表面；以及 於該潔淨上表面上形成一銅陣蔽層，其中曝露釣 的步驟及形成鋼障蔽層的步驟係於相同的室中進行。 5 —種用於在一丰導體裝置内形成—銅互連結構的丁方法 包括以下步驟： 提供一半導體基質； 於半導體基質之上形成一介電層； 佈型該介電層以便在介電層之内形成一開口； 於菘半導體基質之上形成—鋼層，銅層位於該開口之 内； 研磨該銅層以便在開口之内形成一銅互連，該銅互連 具有一上表面； 將該銅互連曝露於一含氫之無矽電漿下以便從銅互連 之上表面移除銅氧化物並形成一潔淨上表面；以及 於該潔淨上表面上形成包含矽及氮之一銅障蔽層，其 中曝露銅互連的步驟及形成銅障蔽層的步驟係於相同的 室中進行。 ¾-- (請先閱讀背面之注意事項再填寫本頁〕 經濟部智慧財產局員工消費合作社印製 -19 - 本紙張又度逋用中圃圃家標隼（CNS > A4洗格（210X297公煃）Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives 4 184 9d A 05 3 ^ ga »C8 —---------- D8 6. Application for Patent Scope l-A type used to form a semiconductor device A method for feeding an interconnect structure includes the following steps: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; fabricating the dielectric layer so as to form an opening in the dielectric layer; on the semiconductor substrate Forming a copper layer, the copper layer is located within the opening; grinding the steel layer to form a copper interconnect within the opening; the copper interconnect has an upper surface; exposing the copper interconnect to a hydrogen-containing plasma Lower to remove copper oxide from the upper surface of the copper interconnect and form a clean upper surface; and to form a steel barrier layer on the clean upper surface, wherein the clean upper surface is no longer oxidized before the copper barrier layer is formed . 2. A method for forming a copper interconnect structure in a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; and fabricating the dielectric layer to form a dielectric layer An opening is formed in the layer; a copper layer is formed on the far semiconductor substrate; the copper layer is located in the opening; the copper layer is ground to form a copper interconnection within the opening, and the steel interconnection has an upper surface; Remove copper oxide from the upper surface of the copper interconnect and form a clean upper surface; and -17- This paper size applies to China National Standard (CNS) A4 (210X297 mm) ¾ ------ ΐτ-- ----, ii (Please read the notes on the back of the cabinet first and then fill out this page) Printed on A18495 B8 by the Consumer Cooperatives of the Shiyang Elevator Bureau of the Ministry of Economic Affairs, ___ D8____ VI. The scope of patent application forms a clean surface. Copper barrier layer 3. A method for forming a steel interconnect structure in a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; and fabricating the dielectric layer so that An opening is formed in the dielectric layer; a copper layer is formed on the semiconductor substrate, and the copper layer is located in the opening; the steel layer is ground to form a copper interconnection within the opening, and the steel interconnection has an upper surface; Surface; exposing the copper interconnect to a plasma containing hydrogen and nitrogen to remove steel oxide from the upper surface of the copper interconnect and forming a clean upper surface; and forming a copper barrier on the far clean upper surface Layer, wherein the clean upper surface is not oxidized before the copper barrier layer is formed. 4. A method for forming a copper interconnect structure in a semiconductor device, comprising the steps of: providing a semiconductor substrate; A dielectric layer is formed on the body; the dielectric layer is shaped so as to form an opening in the dielectric layer; a copper layer is formed on the semiconductor substrate, and the copper layer is located in the opening; the steel layer is ground so as to be in the opening A copper interconnect is formed inside, the feed interconnect has an upper surface; the copper interconnect is exposed to a silicon-free plasma containing hydrogen to interconnect from the copper-18 CN S) Α4; ί ^ (210X297 mm) --r -------- ^ ------. 玎 ------- line (please read the precautions on the back before filling in this Page) ABCD 418495 6. Remove copper oxide on the upper surface of the patent application and form a clean upper surface; and form a copper masking layer on the clean upper surface, in which the step of exposing the fish and the step of forming a steel barrier layer The method is performed in the same chamber. 5—A method for forming a copper interconnect structure in a conductor device includes the following steps: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; The dielectric layer is formed to form an opening within the dielectric layer; a steel layer is formed on the semiconductor substrate, and a copper layer is positioned within the opening; the copper layer is ground to form a copper interconnect within the opening, the The copper interconnect has an upper surface; exposing the copper interconnect to a silicon-free plasma containing hydrogen to remove copper oxide from the upper surface of the copper interconnect and form a clean upper surface; and on the clean upper surface A copper barrier layer containing silicon and nitrogen is formed thereon, in which the steps of the copper interconnect are exposed The steps of forming and forming the copper barrier layer are performed in the same chamber. ¾-- (Please read the notes on the back before filling out this page) Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-19-This paper has been reprinted with the Zhongpupu House Standard (CNS > A4 洗 格 (210X297 Public
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Families Citing this family (147)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6492266B1 (en) * 1998-07-09 2002-12-10 Advanced Micro Devices, Inc. Method of forming reliable capped copper interconnects
JP4014738B2 (en) * 1998-09-15 2007-11-28 株式会社東芝 Manufacturing method of semiconductor wafer
JP2000150647A (en) * 1998-11-11 2000-05-30 Sony Corp Wiring structure and its manufacture
US6355571B1 (en) * 1998-11-17 2002-03-12 Applied Materials, Inc. Method and apparatus for reducing copper oxidation and contamination in a semiconductor device
US7405149B1 (en) * 1998-12-21 2008-07-29 Megica Corporation Post passivation method for semiconductor chip or wafer
US7381642B2 (en) * 2004-09-23 2008-06-03 Megica Corporation Top layers of metal for integrated circuits
JP4554011B2 (en) 1999-08-10 2010-09-29 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device
US6107188A (en) * 1999-08-16 2000-08-22 Taiwan Semiconductor Manufacturing Company Passivation method for copper process
US6423625B1 (en) * 1999-08-30 2002-07-23 Taiwan Semiconductor Manufacturing Company Ltd. Method of improving the bondability between Au wires and Cu bonding pads
US6734110B1 (en) * 1999-10-14 2004-05-11 Taiwan Semiconductor Manufacturing Company Damascene method employing composite etch stop layer
JP3348785B2 (en) 1999-11-25 2002-11-20 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP2001176967A (en) * 1999-12-21 2001-06-29 Nec Corp Semiconductor device and producing method therefor
US6383925B1 (en) * 2000-02-04 2002-05-07 Advanced Micro Devices, Inc. Method of improving adhesion of capping layers to cooper interconnects
US6492267B1 (en) * 2000-02-11 2002-12-10 Micron Technology, Inc. Low temperature nitride used as Cu barrier layer
US6613671B1 (en) * 2000-03-03 2003-09-02 Micron Technology, Inc. Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
US7061111B2 (en) * 2000-04-11 2006-06-13 Micron Technology, Inc. Interconnect structure for use in an integrated circuit
JP3664939B2 (en) * 2000-04-14 2005-06-29 富士通株式会社 CMOS image sensor and manufacturing method thereof
US6287960B1 (en) * 2000-05-08 2001-09-11 Motorola, Inc. Self aligned dual inlaid patterning and etching
US6294460B1 (en) * 2000-05-31 2001-09-25 Advanced Micro Devices, Inc. Semiconductor manufacturing method using a high extinction coefficient dielectric photomask
US6348406B1 (en) * 2000-05-31 2002-02-19 Advanced Micro Devices, Inc. Method for using a low dielectric constant layer as a semiconductor anti-reflective coating
US7122900B2 (en) 2000-06-26 2006-10-17 Renesas Technology Corp. Semiconductor device and method manufacturing the same
US6576550B1 (en) * 2000-06-30 2003-06-10 Infineon, Ag ‘Via first’ dual damascene process for copper metallization
US6596631B1 (en) * 2000-07-26 2003-07-22 Advanced Micro Devices, Inc. Method of forming copper interconnect capping layers with improved interface and adhesion
US6689682B1 (en) * 2000-08-11 2004-02-10 Advanced Micro Devices, Inc. Multilayer anti-reflective coating for semiconductor lithography
JP2002110679A (en) 2000-09-29 2002-04-12 Hitachi Ltd Method for manufacturing semiconductor integrated circuit device
US6348410B1 (en) * 2000-11-02 2002-02-19 Advanced Micro Devices, Inc. Low temperature hillock suppression method in integrated circuit interconnects
US6500754B1 (en) * 2000-11-02 2002-12-31 Advanced Micro Devices, Inc. Anneal hillock suppression method in integrated circuit interconnects
DE10059143B4 (en) * 2000-11-29 2006-12-28 Advanced Micro Devices, Inc., Sunnyvale Surface treatment and cover layer method for producing a copper interface in a semiconductor device
JP2002198370A (en) * 2000-12-26 2002-07-12 Mitsubishi Electric Corp Semiconductor device and its fabrication method
US7172960B2 (en) * 2000-12-27 2007-02-06 Intel Corporation Multi-layer film stack for extinction of substrate reflections during patterning
US6576982B1 (en) * 2001-02-06 2003-06-10 Advanced Micro Devices, Inc. Use of sion for preventing copper contamination of dielectric layer
JP4535629B2 (en) * 2001-02-21 2010-09-01 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US6432822B1 (en) * 2001-05-02 2002-08-13 Advanced Micro Devices, Inc. Method of improving electromigration resistance of capped Cu
US6562416B2 (en) * 2001-05-02 2003-05-13 Advanced Micro Devices, Inc. Method of forming low resistance vias
JP5023413B2 (en) * 2001-05-11 2012-09-12 ソニー株式会社 Semiconductor device and manufacturing method thereof
JP2003017564A (en) * 2001-07-04 2003-01-17 Fujitsu Ltd Semiconductor device and method of manufacturing same
US6429128B1 (en) * 2001-07-12 2002-08-06 Advanced Micro Devices, Inc. Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface
JP2003068848A (en) * 2001-08-29 2003-03-07 Fujitsu Ltd Semiconductor device and its manufacturing method
US6727176B2 (en) * 2001-11-08 2004-04-27 Advanced Micro Devices, Inc. Method of forming reliable Cu interconnects
CN1220258C (en) * 2001-12-27 2005-09-21 松下电器产业株式会社 Forming method for wiring structure
CN1220259C (en) * 2001-12-27 2005-09-21 松下电器产业株式会社 Forming method for wiring structure
CN1198331C (en) * 2001-12-27 2005-04-20 松下电器产业株式会社 Forming method for wiring structure
CN1207773C (en) * 2001-12-27 2005-06-22 松下电器产业株式会社 Forming method of wiring structure
US20030134495A1 (en) * 2002-01-15 2003-07-17 International Business Machines Corporation Integration scheme for advanced BEOL metallization including low-k cap layer and method thereof
US6709971B2 (en) 2002-01-30 2004-03-23 Intel Corporation Interconnect structures in a semiconductor device and processes of formation
US6656840B2 (en) * 2002-04-29 2003-12-02 Applied Materials Inc. Method for forming silicon containing layers on a substrate
US7687917B2 (en) 2002-05-08 2010-03-30 Nec Electronics Corporation Single damascene structure semiconductor device having silicon-diffused metal wiring layer
JP5117755B2 (en) * 2002-05-08 2013-01-16 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2003347299A (en) * 2002-05-24 2003-12-05 Renesas Technology Corp Method for manufacturing semiconductor integrated circuit device
KR100904613B1 (en) * 2002-12-23 2009-06-25 매그나칩 반도체 유한회사 Method of forming a capping layer
US7056826B2 (en) * 2003-01-07 2006-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming copper interconnects
KR100508094B1 (en) * 2003-06-26 2005-08-17 삼성전자주식회사 Semiconductor device with capacitor and method of forming the same
KR100555513B1 (en) * 2003-08-04 2006-03-03 삼성전자주식회사 Metal Interconnection for avoiding void and method for fabricating the same
US7078336B2 (en) * 2003-11-19 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system for fabricating a copper barrier layer with low dielectric constant and leakage current
US7074701B2 (en) * 2003-11-21 2006-07-11 Taiwan Semiconductor Manufacturing Company Method of forming a borderless contact opening featuring a composite tri-layer etch stop material
US7081407B2 (en) 2003-12-16 2006-07-25 Lam Research Corporation Method of preventing damage to porous low-k materials during resist stripping
JP4339152B2 (en) * 2004-03-08 2009-10-07 富士通マイクロエレクトロニクス株式会社 Method for forming wiring structure
US7229911B2 (en) * 2004-04-19 2007-06-12 Applied Materials, Inc. Adhesion improvement for low k dielectrics to conductive materials
US20050233555A1 (en) * 2004-04-19 2005-10-20 Nagarajan Rajagopalan Adhesion improvement for low k dielectrics to conductive materials
KR100632115B1 (en) * 2004-12-29 2006-10-04 동부일렉트로닉스 주식회사 Method for forming the metal interconnection of semiconductor device
JP4941921B2 (en) * 2005-03-14 2012-05-30 株式会社アルバック Selective W-CVD method and Cu multilayer wiring fabrication method
US7192855B2 (en) * 2005-04-15 2007-03-20 Freescale Semiconductor, Inc. PECVD nitride film
JP4535505B2 (en) * 2006-02-10 2010-09-01 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
CN101123210B (en) * 2006-08-10 2013-04-17 中芯国际集成电路制造(上海)有限公司 Making method for metal interconnection layer
TW200826233A (en) * 2006-12-15 2008-06-16 Touch Micro System Tech Method of fabricating metal interconnects and inter-metal dielectric layer thereof
TWI340427B (en) * 2007-02-06 2011-04-11 Touch Micro System Tech Method of fabricating micro mechanical moving member and metal interconnects thereof
US7863196B2 (en) * 2007-05-10 2011-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned dielectric cap
DE102007057686B4 (en) * 2007-11-30 2011-07-28 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG, 01109 A method and semiconductor device having a protective layer for reducing stress relaxation in a dual stress coating technique
JP5135002B2 (en) * 2008-02-28 2013-01-30 ルネサスエレクトロニクス株式会社 Semiconductor device
US20100240220A1 (en) * 2009-03-20 2010-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Process for stripping photoresist and removing dielectric liner
WO2010143609A1 (en) * 2009-06-12 2010-12-16 株式会社アルバック Method for producing electronic device, electronic device, semiconductor device, and transistor
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
CN104241194B (en) * 2013-06-20 2017-10-27 中芯国际集成电路制造(上海)有限公司 Semiconductor interconnection structure and preparation method thereof
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) * 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US11705414B2 (en) * 2017-10-05 2023-07-18 Texas Instruments Incorporated Structure and method for semiconductor packaging
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10424487B2 (en) 2017-10-24 2019-09-24 Applied Materials, Inc. Atomic layer etching processes
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
TWI716818B (en) 2018-02-28 2021-01-21 美商應用材料股份有限公司 Systems and methods to form airgaps
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS596540A (en) 1982-07-05 1984-01-13 Toshiba Corp Manufacture of semiconductor device
JP2544396B2 (en) * 1987-08-25 1996-10-16 株式会社日立製作所 Method for manufacturing semiconductor integrated circuit device
JP2839579B2 (en) * 1989-10-02 1998-12-16 株式会社東芝 Semiconductor device and manufacturing method thereof
US5677111A (en) * 1991-12-20 1997-10-14 Sony Corporation Process for production of micropattern utilizing antireflection film
US5612254A (en) * 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
TW363146B (en) 1992-08-20 1999-07-01 Sony Corp An anti-reflective layer and a method of forming a photoresist pattern
JP3342164B2 (en) 1993-04-16 2002-11-05 三菱電機株式会社 Semiconductor device and method of manufacturing the same
US5378659A (en) 1993-07-06 1995-01-03 Motorola Inc. Method and structure for forming an integrated circuit pattern on a semiconductor substrate
US5447887A (en) 1994-04-01 1995-09-05 Motorola, Inc. Method for capping copper in semiconductor devices
KR100366910B1 (en) * 1994-04-05 2003-03-04 소니 가부시끼 가이샤 Manufacturing method of semiconductor device
US5744376A (en) * 1996-04-08 1998-04-28 Chartered Semiconductor Manufacturing Pte, Ltd Method of manufacturing copper interconnect with top barrier layer
US5893752A (en) * 1997-12-22 1999-04-13 Motorola, Inc. Process for forming a semiconductor device
US5821168A (en) * 1997-07-16 1998-10-13 Motorola, Inc. Process for forming a semiconductor device
US6071813A (en) * 1997-10-20 2000-06-06 Advanced Micro Devices, Inc. Method and system for electrical coupling to copper interconnects

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