TW413907B - Method for manufacturing crown-type capacitor of DRAM cell - Google Patents

Abstract

The present invention discloses a method for manufacturing crown-type capacitor of DRAM cell, on a semiconductor substrate having switching elements. The manufacturing method comprises the steps of: forming an insulation layer on the substrate; forming a contact opening on the insulation layer for connecting to the switching element; forming a first conductive layer on the contact opening for electrically connecting to the switching element; forming a sacrificial layer on the first conductive layer, wherein the material of the sacrificial layer is different from that of the insulation layer; defining the sacrificial layer and the first conductive layer to form a stack structure; forming a conductive spacer on the sidewall of the stack structure; selectively removing the sacrificial layer to form the bottom electrode of the capacitor; forming a dielectric layer on the bottom electrode; and forming the top electrode of the capacitor on the dielectric layer.

Description

413907 * V. Description of the Invention (1) The present invention relates to a method for manufacturing a semiconductor memory element, and more particularly to a method for manufacturing a crown capacitor of a dynamic random access memory (DRAM). Dynamic random access memory is a widely used integrated circuit component, especially in today's information electronics industry. With the evolution of technology ', the common DRAM memory cells on the current production line are mostly composed of a transistor T and a capacitor C, as shown in the circuit diagram in Figure 1. The source of the transistor T is connected to a corresponding bit line (! 51 °) and the pole ((11 & 丨 11) is connected to a bottom electrode of a capacitor C, and the gate The gate is connected to a corresponding word line (ffL) 'an upper electrode (top e 1 ectr 〇dej of the capacitor C is connected to a fixed voltage source, and the lower electrode and the upper electrode are separated by a Dielectric layer. Capacitor C is used to store electronic information. It should have sufficient capacitance to avoid data loss and reduce the frequency of charge refresh. There are two directions to increase the capacitance of capacitor C. One is to reduce the thickness of the dielectric layer. The other is to increase the surface area of the lower electrode. In terms of reducing the thickness of the dielectric layer, the capacitors manufactured today have used extremely thin dielectric layers, but their thickness is not reduced indefinitely. When the thickness of the dielectric layer is less than 50 angstroms, it is very likely that direct carrier tunneling will cause excessive leakage current, which will affect the properties of the element. Therefore, many current research and development efforts are focused on increasing the surface area of the lower electrode. To enhance the capacity of the capacitor. In the conventional less than one million yuan (1MB) of the DRAM manufacturing process, and more generally

413907 V. Description of the invention (2) Use one-degree space capacitor to store data, which is generally called planar_type capacitor. However, planar capacitors need to use a relatively large area to form the lower electrode c in order to provide sufficient capacitance, so they are not suitable for the current process requirements of increasingly integrated DRM devices. Generally, DRAMs with integrated area, such as those with a storage capacity greater than 16M bits, need to use a three-dimensional capacitor structure, such as a trench-type or stack-type capacitor memory element. However, due to money engraved grooves to make capacitors, lattice defects (ineffects) will inevitably be generated on the substrate, which will increase the leakage current and affect the properties of the device. Furthermore, the aspect ratio will increase along the groove. The engraving rate will decrease. Not only does it increase the difficulty of the process, but it also affects the production efficiency. Therefore, the application of the process of the groove type capacitor in the actual production line has its difficulty. The opposite process of the 'stacked capacitor' does not produce the above disadvantages, so many technologies are improved for this type of memory element to achieve the purpose of ensuring a sufficient capacitance when the size of the element is reduced. Among the memory elements of various stacked capacitors, the electrodes have crown-type capacitors that protrude upwards. Since the inner and outer surfaces can provide an effective capacitance area, they are quite suitable for manufacturing highly integrated components, especially It is a memory element larger than 64MB. However, the conventional method for manufacturing a crown capacitor of a dynamic random access memory cell is mainly to deposit an insulating layer on a semiconductor substrate having a switching element, which can provide a flat surface favorable for subsequent processes, and then form an insulating layer on the insulating layer that can be connected to The capacitance of the switching element. But in the formation of the above capacitor etch

Page 5 413907 V. Description of the Invention (3) In the step (3), the flat surface of the insulating layer is usually damaged. In order to improve this problem, an additional shielding layer can be deposited on the above-mentioned insulating layer to ensure that the subsequent process of forming a capacitor will not etch the above-mentioned insulating layer and maintain a flat surface, but this will increase the number of manufacturing steps and affect production efficiency. In view of this, the present invention provides a method for manufacturing a private capacitor of a dynamic random access memory, which is characterized by omitting a conventional shielding layer, but still keeping the flat surface of the insulating layer from being damaged. The above method is also suitable for manufacturing a capacitor on a semiconductor substrate having a switching element, and includes the following steps: forming an insulating layer on the substrate; forming a contact opening in the insulating layer that can communicate with the switching element; and in the contact A first conductive layer is formed on the opening to form an electrical connection with the switching element; a sacrificial layer is formed on the first conductive layer, wherein the material of the sacrificial layer is different from the insulating layer; the sacrificial layer and the first- A conductive layer is formed to form a stacked structure; a conductive spacer is formed on the side wall of the stacked structure; the sacrificial layer is selectively removed to form the capacitor lower electrode; a dielectric layer is formed on the lower electrode; The above capacitor electrode is formed on the dielectric layer. Furthermore, according to the process steps of the crown capacitor provided by the present invention, a dynamic random access memory can be further formed. In order to make the above-mentioned objects and features of the present invention more comprehensible, several preferred embodiments are described below in detail in conjunction with the accompanying drawings, as follows: Brief description of the drawings FIG. 1 is a general dynamic random access memory Schematic diagram of the unit; Figures 2 to 5 are cross-sectional schematic diagrams to illustrate the

4139G7 V. Description of the Invention (4) The manufacturing process of forming a crown capacitor by a good example. DESCRIPTION OF SYMBOLS 10 ~ substrate, 12 ~ field oxide layer, H ~ gate, 22 ~ gate spacer, 24 ~ source and drain region, 26 ~ insulating layer, 30 ~ first conductive layer, 32 ~ sacrificial layer , 34 ~ conductive spacer, 36 ~ lower electrode, 38 dielectric layer, 40 ~ upper electrode embodiment. Refer to FIG. 2 first, which shows the initial steps of the present invention. A semiconductor substrate 10 is provided. Here, a p-type silicon substrate with a lattice orientation of < 100 > is taken as an example. An oxide layer 12 is formed on the substrate by a thermal oxidation process, such as a local oxidation method (LoCos), to define an acUve area that will form a memory cell. Next, a gate oxide layer 14, a complex crystal fragment layer 16, a tungsten oxide layer (WSix) 18, and an oxygen-cutting layer 20 are sequentially deposited on the substrate.The above layers are defined by lithography and anisotropic etching procedures. Pattern, ": an open-pole structure. Then, a lightly-doped or L t region is formed next to the gate structure. For example, using the open-structure structure as a mask, ion implantation, such as a phosphorus doped M source. It is formed by entering the semiconductor substrate 1G. Then, a gate spacer 22 ′ is formed on the interlayer structure and the sidewall, for example, it is completed by a deposition and an anisotropic region, a back, and two insulating layers. Then, a heavily doped source electrode and Drain trace, i, to complete the manufacture of source and drain region 24. For example, using spacer 22 and gate kH as a mask, ion implantation of a higher concentration of an N-type dopant source, such as phosphorous or it semiconductor The substrate 10 is formed. At this point, the complete-transistor element must be deposited on the substrate 10 containing the transistor element to deposit at least one layer, s, to isolate the transistor from the conductive layer formed later, and provide a favorable 413907. Description of the Invention (5) — Flat surface in subsequent processes Make the necessary wires in between. For example, after depositing _____________ on the substrate 10, a planarization process is performed to make the surface of the insulating layer 26 flat, as shown in the figure / figure. The insulating layer 26 may be boron. Phosphosilicate glass or silicon oxide, of which glass filled with stone is more preferred. Tetraethoxysilane (TE0S), 03/02, triethylborate (TEB), and trimethyl Trimethylphosphate (TMP) is the atmospheric pressure chemical vapor deposition (APCVD) deposition of reactants. The planarization technology may be chemical-mechanical polishing. In the conventional technology, 'to ensure The insulating layer 26 is not etched during the subsequent process of removing the sacrificial layer. 'A shielding layer is usually deposited on the insulating layer 26. However, in the manufacturing method of the present invention, because an insulating layer and a sacrificial layer of different materials are used' and The selective etching method for the sacrificial layer is much larger than the selective etching method of the insulating layer to remove the sacrificial layer, so that the step of manufacturing the shielding layer can be omitted. Therefore, according to the method for manufacturing a crown capacitor according to the present invention, After the planarization of the insulating layer is completed, the subsequent electrical manufacturing can be directly performed. After that, the first insulating layer 26 is defined by lithography technology and anisotropic etching process to form a contact opening 28 that exposes the transistor Source and drain regions 24. The etch process can be performed using reactive ion etching (RIE) using carbon fluoride (Cf3) as the main etching reaction gas. A first conductive layer 30 covers the surface of the insulating layer 26 and

413907 V. Description of the invention (6) ΪΪ =: 28 so that subsequent components can form an electrical connection with the source and non-electrode regions. The first conductive layer 3 II ^ ^ ^ ^ ^ LPCVO) For conductive materials, diffusion, ion implantation of arsenic, or ~ 2 or = simultaneous doping method (in sudo doped method). Material 32 of layer 32 is formed with a sacrificial layer 32, where sacrifices are added to ::: The first conductive layer 30 is different from the insulating layer 26. For example, silicon nitride is deposited by PECVD to a thickness between 6000 angstroms and 8000 angstroms to form a sacrificial layer. The facies deposition method has the characteristics of adjusting the tensile stress of the gasified stone and strengthening it to a low temperature. The sacrificial layer 32 is formed. ^ And it is used to deposit the nitrided stone group. Please refer to FIG. 3 for its display. An important step for making the crown of the present invention is performed. First, a photoresist layer (not shown) is formed on the first conductive layer 30. Then the photoresist layer is used to etch the sacrificial layer anisotropically. 32 and the first conductive layer 30 to the insulating layer 26. Next, in the defined sacrificial layer 32 and the first conductive layer 3 The side is formed-conductive spacer 34, * shown in Figure 3. For example, a second conductive layer is conformally deposited on the fixed soil layer 32, the first conductive layer 30 and the insulating layer 26, and then Anisotropically the second conductive layer to the insulating layer 26 can form a conductive spacer 34. The complex second conductive layer can be a polycrystalline silicon layer, and the etching process can be performed using ^ (C12), hydrochloric acid (HC1) or Gasification # (SiC12) is the reaction of etching reaction gas Page 9 413907

Sex ion #etching method, please refer to the sacrificial layer 32, leaving the electrical etching rate under the crown capacitor needs to be large. The sacrificial layer 32 is a nitrided main etching liquid to select fossils, polycrystalline silicon, and so on. The sacrifice of the removal of nitrided stone is carried out.

See Figure 4. The remaining first conductive layer 30 and the conductive spacers 34 are removed by a selective etching process to form the electrodes 36. The selective etching process aligns the sacrificial layer 32 to the first and second conductive layers and the insulating layer. For example, if Shi Xi 'is used, the sacrificial layer 32 may be selectively removed using phosphoric acid at a temperature of about 150 ° C. Due to the thermal phosphoric acid, the etch selectivity for the nitrogen-breaking glass is 10: 0 (H under the flat surface of the bad insulating layer 26, which is used to selectively coat the layer 32. Next, a dielectric layer 38 is formed to Compliantly cover the lower electrode 36 j: Then a third conductive layer is formed on the dielectric layer 38. As the upper electrode, the lower electrode 36 ′ dielectric layer 38 and the upper electrode can be combined to form a crown capacitor of X Ming. As shown in Figure 4. The dielectric layer 38 can be an oxide / silicon nitride / silicon oxide layer (ON0: oxide / nitride / oxide) or nitride = / silicon oxide (N0), an oxide button (Ta2〇 5), silicon oxide or silicon nitride and other insulating layers with high coefficients. Among them, silicon oxide / silicon nitride / silicon oxide (0N〇) or silicon nitride / silicon oxide is preferred. Low-pressure chemical vapor phase can be used. The deposition method is used to deposit a thickness of about 50 angstroms to 60 angstroms. Based on the above process, the surface area of the electrode can also be easily increased to provide a large capacitance. As shown in FIG. Before the dielectric layer 38, a plurality of hemi-spherica grains (hemi-spherica) are formed on the exposed surface of the lower electrode 36 by a conventional procedure. l silicon grain (HSG), or rugged polycrystalline silicon (LPCVD)

Page 10 413907 V. Description of the invention (8) After the po1ys i 1 i con), the crown of the sequential shape memory unit. At the same time, the clinker is not limited to the substance and the method of formation. Although the present invention limits the invention, Within the range, when the range is viewed as the attachment structure 42, a dielectric layered capacitor is formed. Knowing the replacement of this technique in the embodiment, the size has been more familiar with any application, and can be used for various applications, which can effectively increase the surface area of the lower electrode 36. A dynamic random access reporter and the upper electrode can complete a dynamic random access. The reporter should be able to understand that the material materials available in the present invention can be described by various suitable characteristics and the structure space of the present invention is not limited to the actual embodiments. However, it is not intended to be used by those skilled in the art to make changes and decorations without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention shall prevail. ,

Claims (1)

413907 VI. Scope of patent application1. A method for manufacturing a crown capacitor of a dynamic random access memory cell is suitable for manufacturing a capacitor on a semiconductor substrate with a switching element, and the above manufacturing method includes the following steps: forming an insulation on the substrate Forming a contact opening that can communicate with the switching element in the insulating layer; forming a first conductive layer on the contact opening to form an electrical connection with the switching element; forming a contact layer on the first conductive layer Sacrificial layer, wherein the material of the sacrificial layer is different from the insulating layer; defining the sacrificial layer and the first conductive layer; forming a conductive spacer on the sidewall of the sacrificial layer and the first conductive layer; selectively removing the sacrificial layer Layer to form the capacitor lower electrode; forming a dielectric layer on the lower electrode; forming the capacitor upper electrode on the dielectric layer. 2. The manufacturing method according to item 1 of the scope of the patent application, wherein the above-mentioned insulating layer is a borophosphosilicate glass layer having a thickness between 8000 angstroms and 10,000 angstroms. 3. The manufacturing method as described in item 1 of the scope of the patent application, wherein the above-mentioned conductive layer is a polycrystalline silicon layer having a thickness of 1 500 angstroms to 3 palals 0 '< 4. The manufacturing method of item 1 in the above range, wherein Page 12 413907 Six 'patent application scope The conductive layer spacer is polycrystalline silicon, and its thickness is between 50 angstroms and 700 angstroms. 5. —A method for manufacturing a crown capacitor of a dynamic random access memory unit 'is suitable for manufacturing electricity on a semiconductor substrate having a switching element. The above manufacturing method includes the following steps: forming an insulating layer on the substrate; and Forming a contact in the insulating layer that can communicate with the switching element, forming a first conductive layer on the contact opening, thereby forming an electrical connection with the closing element; and forming a silicon nitride on the first conductive layer Layer; defining the first conductive layer and the silicon nitride layer to form a structure; and forming a conductive spacer on a sidewall of the stacked structure; selectively removing the silicon nitride layer to form the capacitor Forming a dielectric layer on the lower electrode; forming the capacitor upper electrode on the dielectric layer. 6. The manufacturing method as described in item 5 of the scope of patent application, wherein the above-mentioned insulating layer is a rotten phosphorous silicon glass layer having a thickness ranging from 8 000 Angstroms to 10,000 Angstroms. "-7. The manufacturing method according to item 5, wherein the conductive layer is a polycrystalline silicon layer having a thickness between 1000 angstroms and 15,000 angstroms. The manufacturing method according to item 5 of the patent application range, wherein Page 13 413907 6. Scope of patent application The conductive layer spacer is polycrystalline silicon, and its thickness is between 500 angstroms and 700 angstroms. 9. The manufacturing method according to item 5 of the scope of the patent application, wherein the silicon nitride is deposited to a thickness between 600 angstroms and 8000 angstroms by a polymer chemical vapor deposition (PECVD) method. 10 · The manufacturing method as described in item 5 of the scope of the patent application, wherein the rabbit selectively removes the above-mentioned gasification with a liquid containing a scaly acid surname ^, U 'A crown of a dynamic random access memory unit The manufacturing method of a capacitor is suitable for manufacturing a capacitor on a semiconductor substrate having a switching element, and the manufacturing method includes the following steps: forming an insulating layer on the substrate; and forming an insulating layer in the insulating layer that can be connected to the switching element. A contact opening; forming a first conductive layer on the contact opening to form an electrical connection with the switch element; forming a gasified stone layer on the first conductive layer by a plasma chemical vapor deposition method; defining the first A conductive layer and the silicon nitride layer to form a stacked structure; a conductive spacer is formed on the sidewall of the stacked structure;.. The silicon nitride layer is selectively removed to form a capacitor under the capacitor; A dielectric layer is formed on the lower electrode, and the capacitor upper electrode is formed on the dielectric layer. 12. The manufacturing method described in item 11 of the scope of patent application, wherein the above Page 14 _- 413907 VI. Scope of patent application The insulating layer is a borophosphosilicate glass layer with a thickness between 8 000 Angstroms and 10,000 Angstroms. 1 3. The manufacturing method as described in item 11 of the scope of patent application, wherein an etching liquid containing phosphoric acid is used to selectively remove the plasma silicon nitride layer. Page 15