TW413842B - Method for improving photoresist residue - Google Patents
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- TW413842B TW413842B TW088101439A TW88101439A TW413842B TW 413842 B TW413842 B TW 413842B TW 088101439 A TW088101439 A TW 088101439A TW 88101439 A TW88101439 A TW 88101439A TW 413842 B TW413842 B TW 413842B
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 title claims description 58
- 239000000463 material Substances 0.000 claims description 50
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 32
- 239000003990 capacitor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 230000002079 cooperative effect Effects 0.000 claims 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- 230000000875 corresponding effect Effects 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 115
- 238000005530 etching Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 238000000059 patterning Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- 229910001413 alkali metal ion Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
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- 238000005034 decoration Methods 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- 229910000679 solder Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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Description
413842 4287twf.doc/006 A7 B7 五、發明説明(/ ) 本發明是有關於一種改善光阻殘留的方法,且特別是 有關於一種改善氮化鈦(T i N)層表面光阻殘留的方法。 在半導體製程中’任何材質層之圖案化的方式均需藉 由光阻材質的使用來達成。光阻是爲一種感光材料,經由 曝光顯影的步驟後,即可以此光阻層當鈾刻罩幕,藉以使 其下方的材質層圖案化。 但蝕刻不同的材質需配合使用不同的光阻材質當蝕 刻罩幕,而蝕刻氧化矽材質層所用的光阻材質會對氮化鈦 材質造成傷害,會造成氮化鈦材質層表面有缺陷產生’而 且即使將光阻淸除後,仍會有部份的光阻材質殘留於氮化 鈦材質層的表面。 因此,本發明提供一種改善光阻殘留的方法,適用於 避免氮化鈦層表面的光阻殘留,包括:於基底上形成絕緣 層,而絕緣層上形成有已圖案化之氮化鈦層,於絕緣層和 氮化鈦層上,形成薄層的介電層,再將介電層上之光'阻層 的圖案轉移至絕緣層,之後再將光阻層剝除。 本發明於氮化鈦層和光阻層之間置入薄層的介電層 做爲氮化鈦層的保護層,以避免光阻材質對氮化鈦層造成 傷害,此介霉層的材質比如是氮化矽層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉一較佳實施例,並配合所附圖式’作詳 細說明如下: 圖式之簡單說明: 第1A圖至第1E圖所示,爲根據本發明一較佳實施例 3 JJ--------裝— V;''. (請先閑讀背面之注意事項再填寫本頁) —訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS > A4规格(210X297公釐) 經濟部中央標準局員工消費合作社印製 413842 4287twf.doc/006 __:_____B7_____ 五、發明説明(之) 之一種改善氮化鈦層表面之光阻殘留的方法,並以指紋辨 認器的半導體製程爲例。 其中,各圖標號與構件名稱之關係如下: 100 :基底 102 :導電層C銲墊) 104、104a :絕緣層 106 :導電層 106a :下電極 108、118、128 :光阻層 116 :開口 110、110a' 112:介電層 實施例 以指紋辨認器(Fingerprint Sensor)的積體電路製程 爲例,當內連線製程完成後,於整個基底結構的上方形成 約手指大小的感測區,約1.5公分見方,在此感測區佈局 約有300行和300列的電容器,而電容器的下電極之材質 較佳的是氮化鈦,而上電極即爲接觸的手指。電容器的作 用係用於感應手指的靜電,因爲指紋的紋路有凹凸之不 同,因此不同的電容器被凹紋和凸紋印壓所感應的電容値 會不同,最後再將此訊號轉換成影像。 傳統在製造指紋辨認器的過程,於內連線製程完成 後,沈積一層已圖案化的氮化鈦層做爲下電極之用,之後 再於氮化鈦層和銲墊之間的氧化矽層形成銲墊開口,以做 爲封裝(Package)製程中拉線的步驟之用。然而,在將氧 4 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先闖讀背面之注意事項再填寫本頁) -裝- 訂 413842 4287lwf.doc/006 A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明(J) 化矽層圖案化的過程中,需於氧化矽層和氮化鈦層上方覆 蓋一層光阻層,然而於此所使用的光阻材質卻會對氮化鈦 層造成傷害會造成氮化鈦材質層表面有缺陷產生,而且光 阻材質會有部份殘留於氮化鈦材質層的表面。如此會造成 電容器的品質不良。 第1A圖至第1E圖所示,爲根據本發明一較佳實施例 之一種改善氮化鈦層表面之光阻殘留的方法,並以指紋辨 認器的半導體製程爲例。 首先請參照第1A圖,提供一基底1〇〇,比如是半導體 矽基底,此基底100已形成有內連線與MOS元件等(未繪 出)。於基底100上形成已圖案化的導電層102,導電層 102是金屬內連線中最上層的導電層,此導電層102係做 爲銲墊之用。其中導電層102的材質比如是鋁、鋁合金、 銅、銅合金或其他類似此性質者。之後於導電層102上形 成絕緣層104,其厚度比如約爲10,000埃至14,000埃, 其材質比如是氧化矽,其形成方法比如是以矽酸四乙酯 (TEOS)爲氣源進行化學氣相沈積製程。接著,於絕緣層 104中形成介層窗開口(未繪示於圖中),做爲連接後續 將形成之電容器的下電極之用。再於絕緣層104上形成一 層導電層106,此導電層106係用於做爲電容器的下電極 之用,其厚度約爲1,800埃至2,200埃,其材質較佳的是 氮化鈦。其中,導電層106更包括塡入介層窗開口中與導 電層102做電性連接:或者先於介層窗開口中塡入導電材 質,以形成導電插塞,再於其上形成導電層106。之後, 5 (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 本纸張尺度適用中國國家標芈(CNS ) A4規格(210 X297公釐) 經濟部中央標準局貝工消費合作社印製 413842 42S7twt.doc/006 A 7 ______B7_ 五、發明説明(Y ) 於導電層102上形成一層已圖案化的光阻層1〇8,此光阻 層108係覆蓋住欲形成電容器的區域。此光阻層丨08之材 質係配合蝕刻氮化鈦導電層102之用,故所使用之光阻材 質不會對氮化鈦導電層102造成傷害。
接著請參照第+1B圖,以此光阻層108爲罩幕,進行 非等向性蝕刻製程,蝕刻導電層106,直至暴露出絕緣層 104止,使導電層106轉爲電容器的下電極l〇6a。利用傳 統的方法剝除光阻層108後,於下電極106a和絕緣層104 的表面形成一薄層的介電層110,其厚度比如約爲80埃至 150埃,此介電層110可約略與整個基底1〇〇結構共形, 此介電層110係用於做爲電容器的部份介電膜層之用,其 材質比如是氮化矽、氧化矽或其他類似此性質者,較佳的 是氮化砂D 由於本發明的特徵之一在於下電極l〇6a形成後,即 覆蓋一薄層的介電層110,此介電層110除了可做爲電容 器的部份介電膜層之用,其主要作用爲保護下電極l〇6a, 避免受到後續製程之光阻材質的污染。 接著請參照第1C圖,於介電層110上覆蓋一已圖案 化的光阻層118,此光阻層118暴露出欲進行拉線的區域’ 此光阻層118係用於做爲蝕刻絕緣層1〇4的蝕刻罩幕之 用。以光阻層11δ爲蝕刻罩幕,依序蝕刻介電層no和絕 緣層104,使其分別轉爲如圖所示之介電層ll〇a和絕緣層 104a,以形成開口 116暴露出導電層102。 由於蝕刻不同的材質需配合使用不同的光阻材質當 6 本紙張尺度適用中國國家標準(CNS ) A4規格(21〇Χ297公釐) (請先閱讀背面之注^一^項再填寫本頁)
製 413842 4287twf.doc/〇〇6 A7 ____—_B7_ 五、發明説明(夂) 蝕刻罩幕,而蝕刻絕緣層104所用的光阻材質會對氮化鈦 下電極106a造成傷害。因此習知直接於氮化鈦下電極上 直接覆蓋光阻材質的做法,會造成氮化鈦下電極表面有缺 陷產生,而光阻材質會有部份殘留於氮化鈦下電極的表 面。故本發明於覆蓋用於定義絕緣層1〇4的光阻層118之 前,先於氮化鈦下電極106a表面覆蓋一薄層的介電層110 做保護層。 接著請參照第1D圖,利利傳統的方法剝除光阻層118 後,於介電層110a上形成一層厚度較厚的介電層,其厚 度比如約爲7,000埃至6800埃,此介電層除了做爲電容 器之部份介電膜層外,亦需做爲整個積體電路的護層,其 材質通常爲密度高、硬度強且介電常數較高的氮化矽,以 保護元件免於遭受到永久的機械性傷害,並可以用來抵擋 外界水氣及鹼金屬離子的穿透,其形成方法比如是化學氣 相沈積法。之後’於此層較厚的介電層上覆蓋一層已圖案 化的光阻層128,將此光阻層128曝光所用的光罩與光阻 層118曝光所用的光罩相同。以此光阻層128爲蝕刻罩 幕,蝕刻此厚度較厚的介電層,使其轉爲如圖所示之介電 層112,以暴露出開口底部的導電層1〇2 ^ 接著請參照第1E圖,利用傳統的方法剝除光阻層U8 後’即可進行後續的封裝製程,然此非關本發明,在此不 多贅述。 本發明的特徵如下: (1)本發明在下電極形成後,即覆蓋一薄層的介電 —I------裝.-- (請先閲讀背面之注意事項再填寫本頁) 訂 4 413842 4287twf'doc/006 A 7 _B7__ 五、發明説明(6) 層,此介電層除了可做爲電容器的部份介電膜層之用,其 主要作用爲保護下電極,避免受到後續製程之光阻材質的 污染。 (2)在定義絕緣層的過程中,若所使用的光阻材質會 對所裸露的氮化鈦材質層造成傷害,則先於氮化鈦材質層 的表面形成一薄層的介電層,用以避免會造成氮化鈦材質 傷害的光阻材質直接其表面。 雖然本發明已以一較佳實施例掲露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍內,當可作各種之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 —\ί-- .‘ C (請先聞讀背面之注^^項再填寫本頁) 、1Τ 經濟部中央標準局貝工消費合作社印製 本紙張尺度適用中國國家操準(CNS ) A4規格(21〇X297公釐)
Claims (1)
- AWCD 810143113842 4287twf.doc/006 六、申請專利範圍 1. 一種改善光阻殘留的方法,且特別適用於避免一 物質層表面的光阻殘留,包括: (請先閱讀背面之注意事項再填寫本頁) 於一基底上形成一絕緣層; 於該絕緣層上形成已圖案化之該物質層; 於該絕緣層和該物質層上,形成一薄層的介電層,用 以保護該物質層; 於該介電層上形成已圖案化的一光阻層; 將該光阻層的圖案轉移至該絕緣層;以及 剝除該光阻層。 2. 如申請專利範圍第1項所述之改善光阻殘留的方 法,其中該絕緣層的材質包括氧化矽。 3. 如申請專利範圍第1項所述之改善光阻殘留的方 法,其中該物質層的材質包括氮化鈦。 4. 如申請專利範圍第3項所述之改善光阻殘留的方 法,其中該介電層的材質包括氮化矽。 5. 如申請專利範圍第4項所述之改善光阻殘留的方 法,其中該介電層約略與該絕緣層和該氮化鈦層共形。 經濟部中央標準局員工消費合作社印製 6. —種指紋辨認器之電容器的製造方法,適用於內 連線製程完成後,該製造方法包括下列步驟: 提供一基底,該基底上形成已圖案化的一第一導電 層,該第一導電層係爲一銲墊; 於該第一導電層上形成一絕緣層; 於該絕緣層上形成一第二導電層; 定義該第二導電層,使形成一電容器之一下電極; 本紙張尺度逋用中國國家揉準(CNS ) A4規格(210X297公鼇) 413842 4287twf,doc/006 A8 B8 C8 D8 申請專利範圍 於該下電極和該絕緣層上,形成一第一介電層; 形成已圖案化的一光阻層於該第一介電層上; 將該光阻層的圖案轉移至該第一介電層和該絕緣 層,以形成一開口暴露出該第一導電層; 剝除該光阻層; 於該第一介電層上形成一第二介電層,該第一介電層 和該第二介電層爲該電容器之一介電膜層;以及 定義該第二介電層,以暴露出對應於該開口之該第一 導電層。 7. 如申請專利範圍第6項所述, 造方法,其中該第二導電層的材質包括氮/ 8. 如申請專利範圍第7項所述之进義 其中該絕緣層的材質包括氧化矽。垮 9. 如申請專利範圍第7項所述之; _容器的製 (請先閲讀背面之注意事項再填寫本頁) -裝· 、1T 第二介電層的材質包相形 10.如申請專利範圍第9項所述 其中該第一介電層約略與該絕緣層和 :.1¾ 與 | % 化鈦層共; 經濟部中央標準局員工消费合作社中I 10 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐)
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TW088101439A TW413842B (en) | 1999-01-30 | 1999-01-30 | Method for improving photoresist residue |
US09/256,566 US6239027B1 (en) | 1999-01-30 | 1999-02-24 | Method using a photoresist residue |
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TW088101439A TW413842B (en) | 1999-01-30 | 1999-01-30 | Method for improving photoresist residue |
US09/256,566 US6239027B1 (en) | 1999-01-30 | 1999-02-24 | Method using a photoresist residue |
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