2919twf.d〇c/006 A7 B7___ 五、發明説明（f ) 本發明是有關於一種積體電路(Integrated Circuits ; ic) 的電容結構與製造方法，且特別是有關於一種利用金屬內 連線製程（metal interconnects)的積體電路電容結構與製造 方法。 請參照第1圖，其繪示習知一種積體電路的電容結構 剖面示意圖。在半導體基底10上設有第一金屬層12，其 材料例如爲鋁，且在第一金屬層12上設有薄的介電層16 與絕緣層14。然後，在絕緣層14中設有儲存開口 15(storage opening)。以及在儲存開口 15中與絕緣層14上設有第二 金屬層18，其材料例如爲鋁。上述第一金屬層12、介電 層16與第二金屬層18共同形成電容19的結構。習知此 種電容結構與目前之0.35/0.25μπι的主流製程不符，且metal routing較爲困難。 請參照第2圖，其繪示習知另一種積體電路的電容結 構剖面示意圖。在半導體基底20上設有第一金屬層22， 其材料例如爲鋁，且在第一金屬層22上依序設有薄的黏 著層24、介電層26與絕緣層28。然後，在絕緣層28中設 有儲存開口 29，以及在儲存開口 29中與絕緣層24上設有 鎢層30與第二金屬層32，其材料例如爲鋁。此處第一金 屬層22、黏著層24、介電層26、鎢層30與第二金屬層32 共同形成電容34的結構。上述鎢層30原本應該覆蓋住儲 存開口 29，但由於儲存開口 29的尺寸太大，且又必須經 過回蝕刻(etch back)的製程，使得鎢層30無法塡滿儲存開 口 29 ’甚至在回蝕刻時還會造成電容底部的損壞。 ______ 3 本紙張尺度適用中國國家標车（CNS ) A4规格（210X297公釐} 裝------訂------嫁 I _ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印裝 29 19twf.doc/〇〇6 Α7 Β7 經濟部中央橾準局貝工消费合作社印繁 五、發明説明（1) 有鑑於此，本發明的目的就是在提供一種積體電路的 電容結構與製造方法，可以使用傳統鎢插塞(W-plug)的方 式來作小於〇·5μιη的製程，且任何的金屬層之間都可以製 作電谷結構，metal routing也不會受到限制。 本發明的另一目的就是在提供一種積體電路的電容結 構與製造方法，可以利用較小的面積達到所需要的電容， 且具有較好的電容特性（包括voltage coefficient以及 temperature coefficient)。 爲達成本發明之目的，提出一種積體電路的電容結構 與製造方法，首先，提供半導體基底，其上已形成有各種 元件結構。然後，在半導體基底上形成第一金屬層，其材 料較佳的是鋁。接著，在第一金屬層上依序形成第一黏著 層與第一介電層。第一黏著層例如爲TiN，第一介電層例 如爲SiON。然後，在第一介電層上依序形成中間金屬層、 第二黏著層與第二介電層。中間金屬層的材料較佳的是 鋁’第二黏著層例如爲ΤιΝ，第二介電層例如爲SiON。接 著’依序定義第二介電層、第二黏著層與中間金屬層的圖 案’使得露出部分第一介電層。此處第一金屬層、第一介 電層與中間金屬層共同形成本發明的電容結構。然後，再 於第一介電層與第二介電層上形成絕緣層。然後，在絕緣 層中形成插塞或金屬介層窗的結構，例如鎢插塞，用以使 第一金屬層或中間金屬層，可以與後續形成之金屬層作電 性連接。接著，在絕緣層上形成第二金屬層，其材料較佳 的是鋁。然後，在第二金屬層上依序形成第三黏著層與第 ____ 4 本紙張尺度適用中國國CNS ) Α4· ( 21〇><297公楚1 ^ 厂裝 訂" (請先閱讀背面之注意事項再填{ί5本頁} 29I9twf.doc/006 A7 29I9twf.doc/006 A7 經濟部中央標準局貝工消費合作社印製 B7 五、發明説明（3) 三介電層。第三黏著層例如爲TiN，第三介電層例如爲 Si〇N。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖繪示習知一種積體電路的電容結構剖面示意 圖； 第2圖繪示習知另一種積體電路的電容結構剖面示意 圖；以及 第3A-3D圖繪示根據本發明之一較佳實施例，一種積 體電路的電容製造流程的剖面示意圖。 圖式之標記說明： 10,20,40 :半導體基底 12,22,42 :第一金屬層 14,28,56 :絕緣層 15,29 :儲存開口（storage opening) 16 :介電層 18,32,58 :第二金屬層 19,34,54 :電容 24,44,50,60 :黏著層 26,46,52,62 :介電層 30 :鎢層 57a，57b :鎢插塞 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 衣 、1τ纪 > I (請先閱讀背面之注意事項再填寫本頁) 29 1 9twf.doc/006 A7 B7_____ 五、發明説明（f) 48 :中間金屬層 實施例 本發明的特徵在於，在一般傳統的金屬內連線結構 中，於低層次金屬層和高層次金屬層之間插入一層中間金 屬層，其與低層次金屬層之間包括介電層的結構，於是形 成本發明的電容結構。此方法可以仍然沿用傳統鎢插塞 (W-plug)的方式來作小於〇.5μιη的製程。且在任何的金屬 層之間都可以製作，metal routing也不會受到限制。此外， 又可以利用較小的面積達到所需要的電容，使得本發明的 電容結構具有較好的電容特性(包括voltage coefficient以及 temperature coefficient)。 請參照第3A-3D圖，其所繪示根據本發明之一較佳實 施例，一種積體電路的電容製造流程的剖面示意圖。首先， 請參照第3A圖，提供半導體基底40，其上已形成有各種 元件結構(未顯示）。然後，在半導體基底40上形成第一金 屬層42，其材料較佳的是鋁。第一金屬層42的形成方式 例如爲濺鍍法。接著，在第一金屬層42上覆蓋第一黏著 層44(glue layer)，並在第一黏著層44上覆蓋第一介電層 46(dielectric layer)。第一黏著層44例如爲TiN，第一介電 層46例如爲SiON。然後，在第一介電層46上依序形成中 間金屬層48、第二黏著層50與第二介電層52。中間金屬 層48的材料較佳的是鋁，且其形成方式例如爲濺鑛法。 第二黏著層50例如爲TiN，第二介電層52例如爲SiON。 接著，請參照第3B圖，以第一介電層46爲終止層， 6 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） I II ^ 裝 訂" (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 291 9twf.doc/006 A7 291 9twf.doc/006 A7 經濟部中央標準局貝工消费合作社印聚 _______B7 五、發明説明（) _ ' 依序纟虫刻疋義第一介電層52、第二黏著層5〇與中間金屬 層48的圖案，露出第一介電層46，餘留的部分爲中間金 屬層48a、第一黏著層5〇a與第二介電層52a。可以看到的 是，上述第〜金屬層42(用以作下電極）、第一介電層46 與中間金屬層48(用以作上電極)共同形成電容54的結構。 然後，再於第一介電層46與第二介電層52a上形成絕緣 層56，例如氧化矽層。 接著，S靑參照第3C圖，在絕緣層56中形成插塞(piUg) 或金屬介層窗(metal Via)的結構，例如鎢插塞57a或鎢插塞 57b。鎢插塞57a形成在第一介電層46上，鎢插塞57b形 成在第一介電層46上。 接著，請參照第3D圖，在絕緣層56上形成第二金屬 層58，其材料較佳的是鋁。第二金屬層58的形成方式例 如爲濺鍍法。然後，在第二金屬層58上覆蓋第三黏著層6〇， 並在第三黏著層60上覆蓋第三介電層62。第三黏著層6〇 例如爲TiN，第三介電層62例如爲SiON。第二金屬層58 藉由鎢插塞57a與第一金屬層42作電性連接，而第二金 屬層58藉由鎢插塞57b與中間金屬層48作電性連接。於 是完成本發明的電容結構54，其係爲位於第二金屬靥％ 與第一金屬層42之金屬內連線結構之間。 綜上所述，本發明所提供積體電路的電容結構與製造 方法，有以下的優點： (1)本發明所提供的電容結構54,其製造方法與金屬 內連線的製程相容 > 可以使用傳統鎢插塞(W-plug)的方式 7 本紙張尺度適用中國國家樣準（A4規格UlOX 2^7公楚) ' 〜 t------IT------^ (請先閱讀背面之注意事項再填寫本頁) 2919twf.doc/006 Λ7 B7___ 五、發明説明（έ) 來作小於〇.5μπι的製程，且在任何的金屬層之間都可以形 成此種電容結構54，metal routing也不會受到限制。 (2)本發明所提供的電容結構54，可以利用較小的面 積達到所需要的電容，其具有較好的電容特性(包括voltage coefficient 以及 temperature coefficient) 〇 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 ---------^------IT------.t (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印繁 本紙張纽適财關 CNS ) A4^"( 210 X 297^f )2919twf.d0c / 006 A7 B7___ 5. Description of the Invention (f) The present invention relates to a capacitor structure and manufacturing method for integrated circuits (IC), and in particular to a process using metal interconnections (Metal interconnects) integrated circuit capacitor structure and manufacturing method. Please refer to FIG. 1, which is a schematic cross-sectional view of a capacitor structure of a conventional integrated circuit. The semiconductor substrate 10 is provided with a first metal layer 12 made of, for example, aluminum, and a thin dielectric layer 16 and an insulating layer 14 are provided on the first metal layer 12. Then, a storage opening 15 is provided in the insulating layer 14. A second metal layer 18 is provided in the storage opening 15 and on the insulating layer 14, and the material is, for example, aluminum. The first metal layer 12, the dielectric layer 16 and the second metal layer 18 together form a capacitor 19 structure. It is known that this type of capacitor structure is inconsistent with the current mainstream process of 0.35 / 0.25 μm, and metal routing is difficult. Please refer to FIG. 2, which is a schematic cross-sectional view of a capacitor structure of another conventional integrated circuit. A first metal layer 22 is provided on the semiconductor substrate 20, and its material is, for example, aluminum. A thin adhesive layer 24, a dielectric layer 26, and an insulating layer 28 are sequentially disposed on the first metal layer 22. Then, a storage opening 29 is provided in the insulating layer 28, and a tungsten layer 30 and a second metal layer 32 are provided in the storage opening 29 and the insulating layer 24, and the material is, for example, aluminum. Here, the first metal layer 22, the adhesive layer 24, the dielectric layer 26, the tungsten layer 30 and the second metal layer 32 together form a structure of a capacitor 34. The above-mentioned tungsten layer 30 should originally cover the storage opening 29, but because the size of the storage opening 29 is too large and must be etched back, the tungsten layer 30 cannot fill the storage opening 29 'or even etch back It can also cause damage to the bottom of the capacitor. ______ 3 This paper size is applicable to China National Standard Car (CNS) A4 specification (210X297mm) Packing -------- Order ------ Marry I _ (Please read the precautions on the back before filling this page) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China 29 19twf.doc / 〇〇6 Α7 Β7 Printed by the Central Laboratories of the Ministry of Economic Affairs of the Shellfish Consumer Cooperatives of the Ministry of Economic Affairs of Japan 5. Description of the Invention A capacitor structure and manufacturing method of an integrated circuit can use a traditional tungsten plug (W-plug) method for a process smaller than 0.5 μm, and an electrical valley structure can be made between any metal layers, and metal routing also There is no limitation. Another object of the present invention is to provide a capacitor structure and manufacturing method of an integrated circuit, which can use a small area to achieve the required capacitance, and has better capacitance characteristics (including voltage coefficient and temperature). In order to achieve the purpose of the present invention, a capacitor structure and a manufacturing method of an integrated circuit are proposed. First, a semiconductor substrate is provided, on which various element structures have been formed. Then A first metal layer is formed on the semiconductor substrate, and the material is preferably aluminum. Then, a first adhesive layer and a first dielectric layer are sequentially formed on the first metal layer. The first adhesive layer is, for example, TiN. A dielectric layer is, for example, SiON. Then, an intermediate metal layer, a second adhesive layer, and a second dielectric layer are sequentially formed on the first dielectric layer. The material of the intermediate metal layer is preferably an aluminum 'second adhesive layer. For example, it is TiN, and the second dielectric layer is, for example, SiON. Then, "the patterns of the second dielectric layer, the second adhesive layer, and the intermediate metal layer are sequentially defined" so that a portion of the first dielectric layer is exposed. Here, the first metal layer The first dielectric layer and the intermediate metal layer together form the capacitor structure of the present invention. Then, an insulating layer is formed on the first dielectric layer and the second dielectric layer. Then, a plug or a metal dielectric is formed in the insulating layer. The structure of the layer window, such as a tungsten plug, is used to enable the first metal layer or the intermediate metal layer to be electrically connected to a subsequently formed metal layer. Then, a second metal layer is formed on the insulating layer, and its material is preferred Is aluminum. Then, on the second metal layer In order to form the third adhesive layer and the ____ 4 This paper size is applicable to China's CNS) Α4 · (21〇 > < 297 Gongchu 1 ^ Factory binding " (Please read the precautions on the back before filling {ί5 Page} 29I9twf.doc / 006 A7 29I9twf.doc / 006 A7 Printed by B7, Shelley Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the invention (3) Three dielectric layers. The third adhesive layer is, for example, TiN, third dielectric The layer is, for example, SiON. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: Brief description: Fig. 1 shows a schematic cross-sectional view of a capacitor structure of a conventional integrated circuit; Fig. 2 shows a cross-sectional schematic view of a capacitor structure of another integrated circuit; and Figs. 3A-3D show a schematic diagram according to the present invention. A preferred embodiment is a schematic cross-sectional view of a capacitor manufacturing process of an integrated circuit. Description of the symbols of the drawings: 10, 20, 40: semiconductor substrates 12, 22, 42: first metal layers 14, 28, 56: insulating layers 15, 29: storage openings 16: dielectric layers 18, 32 , 58: second metal layer 19, 34, 54: capacitor 24, 44, 50, 60: adhesive layer 26, 46, 52, 62: dielectric layer 30: tungsten layer 57a, 57b: tungsten plug 5 paper sizes Applicable to China National Standard (CNS) A4 specification (210X297 mm) Clothing, 1τ Ji > I (Please read the precautions on the back before filling this page) 29 1 9twf.doc / 006 A7 B7_____ V. Description of the invention (f) 48: Embodiment of an intermediate metal layer The present invention is characterized in that, in a general conventional metal interconnect structure, an intermediate metal layer is inserted between a low-level metal layer and a high-level metal layer, and between the low-level metal layer A structure including a dielectric layer thus forms a capacitor structure of the present invention. This method can still use the traditional tungsten plug (W-plug) to make processes smaller than 0.5 μm. It can be fabricated between any metal layers, and metal routing is not restricted. In addition, a smaller area can be used to achieve the required capacitance, so that the capacitor structure of the present invention has better capacitance characteristics (including voltage coefficient and temperature coefficient). Please refer to FIGS. 3A-3D, which are schematic cross-sectional views illustrating a manufacturing process of a capacitor of an integrated circuit according to a preferred embodiment of the present invention. First, referring to FIG. 3A, a semiconductor substrate 40 is provided, on which various element structures (not shown) have been formed. Then, a first metal layer 42 is formed on the semiconductor substrate 40, and its material is preferably aluminum. A method of forming the first metal layer 42 is, for example, a sputtering method. Next, the first metal layer 42 is covered with a first glue layer 44, and the first adhesive layer 44 is covered with a first dielectric layer 46. The first adhesive layer 44 is, for example, TiN, and the first dielectric layer 46 is, for example, SiON. Then, an intermediate metal layer 48, a second adhesive layer 50, and a second dielectric layer 52 are sequentially formed on the first dielectric layer 46. The material of the intermediate metal layer 48 is preferably aluminum, and the formation method thereof is, for example, a sputtering method. The second adhesive layer 50 is, for example, TiN, and the second dielectric layer 52 is, for example, SiON. Next, please refer to Figure 3B, with the first dielectric layer 46 as the termination layer. 6 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) I II ^ Binding " (Please read the note on the back first Please fill in this page again) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative 291 9twf.doc / 006 A7 291 9twf.doc / 006 A7 Printed by the Central Standards Bureau of Ministry of Economic Affairs, Shellfish Consumer Cooperative _______B7 V. Description of Invention () _ 'Patterns of the first dielectric layer 52, the second adhesive layer 50, and the intermediate metal layer 48 are sequentially etched, and the first dielectric layer 46 is exposed. The remaining part is the intermediate metal layer 48a, the first The adhesive layer 50a and the second dielectric layer 52a. It can be seen that the above-mentioned first metal layer 42 (used as the lower electrode), the first dielectric layer 46 and the intermediate metal layer 48 (used as the upper electrode) collectively form a capacitor 54 structure. Then, an insulating layer 56 such as a silicon oxide layer is formed on the first dielectric layer 46 and the second dielectric layer 52a. Next, referring to FIG. 3C, a structure of a plug (piUg) or a metal via (metal via), such as a tungsten plug 57a or a tungsten plug 57b, is formed in the insulating layer 56. A tungsten plug 57a is formed on the first dielectric layer 46, and a tungsten plug 57b is formed on the first dielectric layer 46. Next, referring to FIG. 3D, a second metal layer 58 is formed on the insulating layer 56. The material is preferably aluminum. A method for forming the second metal layer 58 is, for example, a sputtering method. Then, a third adhesive layer 60 is covered on the second metal layer 58, and a third dielectric layer 62 is covered on the third adhesive layer 60. The third adhesive layer 60 is, for example, TiN, and the third dielectric layer 62 is, for example, SiON. The second metal layer 58 is electrically connected to the first metal layer 42 through a tungsten plug 57a, and the second metal layer 58 is electrically connected to the intermediate metal layer 48 through a tungsten plug 57b. The capacitor structure 54 of the present invention is completed, which is located between the second metal 靥% and the metal interconnect structure of the first metal layer 42. In summary, the capacitor structure and manufacturing method of the integrated circuit provided by the present invention have the following advantages: (1) The capacitor structure 54 provided by the present invention, the manufacturing method is compatible with the manufacturing process of the metal interconnections > The traditional tungsten plug (W-plug) can be used. 7 This paper size is applicable to Chinese national standards (A4 specification UlOX 2 ^ 7). '~ T ------ IT ------ ^ ( Please read the precautions on the back before filling in this page) 2919twf.doc / 006 Λ7 B7___ V. Description of the invention (rod) for a process smaller than 0.5 μm, and this capacitor structure can be formed between any metal layers 54, metal routing will not be restricted. (2) The capacitor structure 54 provided by the present invention can use a small area to achieve the required capacitance, which has better capacitance characteristics (including voltage coefficient and temperature coefficient). In summary, although the present invention has been A preferred embodiment is disclosed above, but it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be Subject to the scope of the attached patent application. --------- ^ ------ IT ------. T (Please read the notes on the back before filling this page) Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs Paper New Zealand Financial Gateway CNS) A4 ^ " (210 X 297 ^ f)