TW517344B - Manufacturing method of anti-fuse structure - Google Patents

Manufacturing method of anti-fuse structure Download PDF

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Publication number
TW517344B
TW517344B TW90112759A TW90112759A TW517344B TW 517344 B TW517344 B TW 517344B TW 90112759 A TW90112759 A TW 90112759A TW 90112759 A TW90112759 A TW 90112759A TW 517344 B TW517344 B TW 517344B
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Taiwan
Prior art keywords
dielectric
fuse structure
scope
layer
patent application
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TW90112759A
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Chinese (zh)
Inventor
Tsung-Min Shie
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United Microelectronics Corp
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Abstract

A manufacturing method of anti-fuse structure is disclosed, in which a substrate is provided firstly, and a conductive region is formed on the substrate. Then a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to form the first opening for exposing the conductive region. Then the first conductive layer is filled into the first opening to form a via plug, then a dielectric thin layer is formed on the first dielectric layer and the via plug, and a second dielectric layer is formed on the dielectric thin layer. Then the first dielectric layer is patterned to form a second opening, in which the second opening at least exposes part of the dielectric thin layer on the via plug. Then, a second conductive layer is formed on the second dielectric layer, and the second opening is fully filled.

Description

^_I_ 經齊郎智慧財產局員工消費合作社印製 517344 75〇〇twf·d〇c/0〇6 A7 --- ---B7 發明說明（/ ) 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種反熔絲（Anti-Fuse)結構的製造方法。 反熔絲係爲一種在邏輯電路之閘極陣列(Gate Array)中 用以與每一電晶體連接之元件’意即閘極陣列中之每一電 晶體皆有一反熔絲結構與其連接，其作用爲用以將閘極陣 列進行程式化。反熔絲結構亦可形成於後段製程之金屬內 連線之中，將其與介層插塞連接，以進行閘極陣列之程式 化。 利用反熔絲進行閘極陣列之程式化，係利用施加一高 電壓於一反熔絲結構時，反熔絲結構中之介電層會崩潰， 使此反熔絲呈”開”(〇n)之狀態。反之，在不施加任何電壓 時，反熔絲係成一”關”(〇ff)之狀態。因此，利用反熔絲結 構進行程式化，係利用於每一反熔絲結構施加電壓或不施 加電壓，而分別使其呈”開”或”關”之狀態，以達到閘極陣 列之程式化之目的。 第1圖是習知之形成於金屬內連線之其中一反熔絲結 構之剖面示意圖。 請參照第1圖，在所提供之基底100上已形成有一金 屬內連線層102。之後，在基底100與金屬內連線層102 上形成一第一介電層104。接著，在第一介電層104中形 成一介層插塞（Via Plug)106，並使之與金屬內連線層102 電性連接。之後，在第一介電層104上形成一第二介電層 108，再於第二介電層108中形成一反熔絲結構116，此反 熔絲結構116係由金屬層110-介電層112-金屬層114所組 3 (請先閱讀背面之注意事項再填寫本頁) IT--------· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 517344 7 5 00twf. doc/006 A7 B7 五、發明說明（么） 成之三明治結構。之後，在介電層1〇8上形成一金屬層118 並且在介電層108中形成有介層插塞118a，以使金屬層 與反熔絲結構116之金屬層110電性連接。 當施加一高電壓於反熔絲結構116時’反熔絲結構之 金屬層110與金屬層114之間之介電層112將崩潰，使此 反熔絲結構呈，，開，，之狀態。反之，若未施加電壓於反溶絲 結構116時，反熔絲結構係呈，，關，，之狀態。藉由與反熔絲 結構成開或關之狀態’可達到將閘極陣列程式化之目@ ° 然而習知形成於金屬內連線上之反熔絲結構需在介Μ 插塞之間形成一金屬層-介電層-金屬層結構之反熔絲、糸吉 構，其中反熔絲結構之上層金屬層與反熔絲結構上方之介 層插塞電性連接，而反熔絲結構之下層金屬層與反熔絲結 構下方之介層插塞電性連接。因此，習知之反熔絲結構與 介層插塞係爲兩個分開的元件，如此將無法有效減少其尺 寸與降低其寄生電容。其次，由於習知之反熔絲結構與介 層插塞係爲兩個不同之元件，因此於金屬內連線製程中形 成反熔絲結構之步驟也較爲繁瑣。 因此本發明的目的就是在提供一種反熔絲結構的製造 方法，以減少反熔絲結構所佔用之面積，而降低其寄生電 容。 本發明的另一目的是提供一種反熔絲結構的製造方 法，以使形成反熔絲結構之製程較爲簡化。 一種反熔絲結構的製造方法，此方法係首先提供一基 底，且基底上已形成有一金屬內連線層。接著在基底上形 4 本紙張尺度適用中國國家標準（CNS)AI規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -—裝--------訂--------· 經齊郎智慧財產局員工消費合作社印製 517344 7 5 00twf. doc/00 6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（>) 成一第一介電層，並圖案化第一介電層，以形成一第一開 口，暴露出金屬內連線層，之後在第一開口塡入一第一導 電層，以形成一介層插塞，然後在第一介電層與介層插塞 上形成一介電薄層，並在介電薄層上形成一第二介電層， 接著圖案化第二介電層，以形成一第二開口，其中第二開 口至少暴露出介層插塞上之部分介電薄層，之後在第二開 口中塡入一第二導電層，以形成金屬內連線中之反熔絲結 構。 本發明將反熔絲結構與介層插塞結合，可有效其降低 所佔用之面積，而降低其寄生電容，並有利於提高積極度。 本發明將反熔絲結構與介層插塞結合，較習知於兩介 層插塞之間形成反溶絲結構之方法較爲簡化。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖爲習知之形成於金屬內連線之其中一反熔絲結 構圖。 第2A圖至第2E圖是依照本發明一較佳實施例之反熔 絲結構之製造流程剖面圖。 圖式之標示說明： 100、200 :基底 102 :金屬內連線層 1〇4、204 :第一介電層 5 (請先閱讀背面之注意事項再填寫本頁) 裝 訂--- 秦· 本紙張尺度適用中國國家標準（CNS)A4規格《】0 X 297公釐） 經濟邹智慧財產局員工消費合作社印製 517344 75〇〇twf. doc/006 A7 _ B7 五、發明說明（έ ) 開，，之狀態。反之，若未施加電壓於反熔絲結構時，反熔 絲結構將呈”關”之狀態。因此，利用施加電壓與不施加電 壓於反熔絲結構之作用，可達到將積體電路之閘極陣列程 式化之目的。 本發明將介層插塞元件與反熔絲結構兩者結合成一元 件，較習知方法中反熔絲結構與介層插塞爲分開之兩元件 可大幅減少所佔用之面積，如此一來除了可降低其寄生電 容之外，且有利於提高積體電路之積極度。再者，本發明 利用形成介層插塞之製程時，同時形成反熔絲結構，因此 較習知之方法更爲簡化。 綜合以上所述，本發明具有下列優點： 1 ·本發明將反熔絲結構與介層插塞結合，可有效其降 低所佔用之面積，而降低其寄生電容，並有利於提高積極 度。 2·本發明將反熔絲結構與介層插塞結合，較習知於兩 介層插塞之間形成反熔絲結構之方法較爲簡化。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） --— — — — — I — -II! (請先閱讀背面之注意事項再填寫本頁) 1Τ--------^ _I_ Printed by Jingqilang Intellectual Property Bureau employee consumer cooperative 517344 75〇twf · d〇c / 0〇6 A7 --- --- B7 Description of the invention (/) The present invention relates to a method for manufacturing a semiconductor device , And in particular, relates to a method for manufacturing an anti-fuse structure. An antifuse is a component used in the gate array of a logic circuit to connect to each transistor. This means that each transistor in the gate array has an antifuse structure connected to it. Used to program the gate array. The anti-fuse structure can also be formed in the metal interconnects in the later stages, and it is connected to the interposer plug to program the gate array. The anti-fuse is used to program the gate array. When a high voltage is applied to an anti-fuse structure, the dielectric layer in the anti-fuse structure will collapse, making this anti-fuse "on" (〇n ) 'S status. Conversely, when no voltage is applied, the anti-fuse is in a "OFF" state. Therefore, the use of anti-fuse structure for stylization is to use each anti-fuse structure to apply or not apply voltage, and to make it "on" or "off" respectively, so as to achieve the stylization of the gate array. Purpose. FIG. 1 is a schematic cross-sectional view of a conventional anti-fuse structure formed on a metal interconnect. Referring to FIG. 1, a metal interconnect layer 102 has been formed on the provided substrate 100. After that, a first dielectric layer 104 is formed on the substrate 100 and the metal interconnect layer 102. Next, a via plug 106 is formed in the first dielectric layer 104 and is electrically connected to the metal interconnect layer 102. After that, a second dielectric layer 108 is formed on the first dielectric layer 104, and an anti-fuse structure 116 is formed in the second dielectric layer 108. The anti-fuse structure 116 is formed by the metal layer 110-dielectric Layer 112-Group 3 of Metal Layer 114 (Please read the precautions on the back before filling this page) IT -------- · This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) 517344 7 5 00twf. Doc / 006 A7 B7 5. Description of the invention (?) The sandwich structure. After that, a metal layer 118 is formed on the dielectric layer 108 and a dielectric plug 118a is formed in the dielectric layer 108, so that the metal layer is electrically connected to the metal layer 110 of the anti-fuse structure 116. When a high voltage is applied to the anti-fuse structure 116, the dielectric layer 112 between the metal layer 110 and the metal layer 114 of the anti-fuse structure will collapse, causing the anti-fuse structure to be in the on, on, and in a state. Conversely, when no voltage is applied to the anti-solvent structure 116, the anti-fuse structure is in a state of, off, and. By turning on or off with the anti-fuse structure, the goal of stylizing the gate array can be achieved @ ° However, the anti-fuse structure conventionally formed on the metal interconnects needs to be formed between the M plugs A metal layer-dielectric layer-anti-fuse structure with a metal layer structure, wherein the upper metal layer of the anti-fuse structure is electrically connected to the dielectric plug above the anti-fuse structure, and the anti-fuse structure is The lower metal layer is electrically connected to the dielectric plug under the anti-fuse structure. Therefore, the conventional anti-fuse structure and the interposer plug are two separate components, so it cannot effectively reduce its size and reduce its parasitic capacitance. Secondly, since the conventional anti-fuse structure and the interposer plug are two different components, the steps of forming the anti-fuse structure in the metal interconnection process are also more complicated. It is therefore an object of the present invention to provide a method for manufacturing an anti-fuse structure to reduce the area occupied by the anti-fuse structure and reduce its parasitic capacitance. Another object of the present invention is to provide a method for manufacturing an anti-fuse structure, so as to simplify the process of forming the anti-fuse structure. A method for manufacturing an antifuse structure. This method first provides a substrate, and a metal interconnect layer has been formed on the substrate. Then form 4 paper sizes on the base to apply Chinese National Standard (CNS) AI specifications (210 X 297 mm) (Please read the precautions on the back before filling this page) -------- · Printed by the Employees 'Cooperatives of the Qilang Intellectual Property Bureau 517344 7 5 00twf. Doc / 00 6 A7 B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A first dielectric layer, and patterning the first dielectric layer to form a first opening, exposing the metal interconnect layer, and then inserting a first conductive layer into the first opening to form a dielectric plug, Then, a thin dielectric layer is formed on the first dielectric layer and the dielectric plug, and a second dielectric layer is formed on the dielectric thin layer, and then the second dielectric layer is patterned to form a second opening. The second opening exposes at least a portion of the dielectric thin layer on the dielectric plug, and then a second conductive layer is inserted into the second opening to form an anti-fuse structure in the metal interconnect. The invention combines the anti-fuse structure and the interposer plug, which can effectively reduce the occupied area, reduce its parasitic capacitance, and help improve the enthusiasm. The invention combines the anti-fuse structure and the interposer plug, which is simpler than the conventional method of forming an anti-solubilization structure between the two interposer plugs. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 It is a conventional anti-fuse structure diagram formed on a metal interconnect. 2A to 2E are cross-sectional views of a manufacturing process of an anti-fuse structure according to a preferred embodiment of the present invention. Description of the drawings: 100, 200: Base 102: Metal interconnect layer 104, 204: First dielectric layer 5 (Please read the precautions on the back before filling this page) Binding --- Qin The paper size applies the Chinese National Standard (CNS) A4 specification "] 0 X 297 mm. Printed by the Consumers' Cooperative of the Economic Zou Intellectual Property Bureau. 517344 75〇twf. Doc / 006 A7 _ B7 V. Description of the invention , The state. Conversely, if no voltage is applied to the anti-fuse structure, the anti-fuse structure will be in the "off" state. Therefore, using the effect of applying voltage and not applying voltage on the anti-fuse structure, the gate array of the integrated circuit can be programmed. The invention combines both the interposer plug element and the anti-fuse structure into one element, which can greatly reduce the occupied area compared with the conventional method in which the anti-fuse structure and the interposer plug are separated. In addition to reducing its parasitic capacitance, it is conducive to increasing the enthusiasm of the integrated circuit. Furthermore, the present invention utilizes a process for forming a via plug to simultaneously form an anti-fuse structure, so it is more simplified than conventional methods. To sum up, the present invention has the following advantages: 1. The present invention combines the anti-fuse structure and the interposer plug, which can effectively reduce the area occupied by it, reduce its parasitic capacitance, and help increase the enthusiasm. 2. The present invention combines the anti-fuse structure and the interposer plug, which is simpler than the conventional method of forming an anti-fuse structure between two interposer plugs. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 8 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 meals) --- — — — — I — -II! (Please read the precautions on the back before filling this page) 1Τ ---- ----

Claims (1)

517344 A8 B8 7500twf.doc/006_g|_ 六、申請專利範圍 1. 一種反熔絲結構的製造方法，包括下列步驟： 提供一基底，該基底上已形成有一導電區； 在該基底上形成一第一介電層； 圖案化該第一介電層，以形成一第一開口，並暴露出 目亥導電區·， 在該第一開口塡入一第一導電層，以形成一介層插 塞； ‘ 在該第一介電層與該介層插塞上形成一介電薄層； 在該介電薄層上形成一第二介電層； 圖案化該第二介電層，以形成一第二開口，其中該第 二開口係至少暴露出該介層插塞上之部分該介電薄層；以 及 在該第二介電層上形成一第二導電層，並塡滿該第二 開口。 2. 如申請專利範圍第1項所述之反熔絲結構的製造方 法，其中該介電薄層之材質包括氮化矽。 3. 如申請專利範圍第2項所述之反熔絲結構的製造方 法，其中該介電薄層之厚度爲50埃至200埃左右。 經濟部智慧財產局員工消費合作社印製 -----------·裝--- (請先閱讀背面之注意事項再填寫本頁) 4. 如申請專利範圍第1項所述之反熔絲結構的製造方 法，其中該介電薄層之材質包括非晶矽。 5. 如申請專利範圍第4項所述之反熔絲結構的製造方 法，其中該介電薄層之厚度爲1〇〇埃至200埃左右。 6. 如申請專利範圍第1項所述之反熔絲結構的製造方 法，其中該介電薄層係爲形成該第二開口之一蝕刻終止 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 經濟部智慧財產局員工消費合作社印制衣 517344 A8 B8 7500twf.doc/〇〇6 C8 __D8 夂、申請專利範圍 層。 7·如申請專利範圍第1項所述之反熔絲結構的製造方 法’其中該第一介電層之材質包括氧化矽。 8·如申請專利範圍第1項所述之反熔絲結構的製造方 法’其中該第二介電層之材質包括氧化矽。 9. 如申請專利範圍第1項所述之反熔絲結構的製造方 法’其中該第一導電層之材質係選自多晶砂與金屬其中之 -- 〇 10. 如申請專利範圍第1項所述之反溶絲結構的製造 方法，其中該第二導電層之材質係選自多晶矽與金屬其中 之一。 Π·如申請專利範圍第1項所述之反熔絲結構的製造 方法，其中該導電區包括一金屬內連線層。 12·如申請專利範圍第1項所述之反熔絲結構的製造 方法，其中在該第一開口塡入該第一導電層以形成該介層 插塞之方法包括： 在該第一介電層上形成該第一導電層，並塡滿該第一 開口；以及 以化學機械硏磨法將部分該第一導電層去除，直_該 第一介電層暴露出。 13· —種反熔絲結構的製造方法，包括下列步驟： 提供一基底，該基底上已形成有一導電區； 在該基底上形成一第一介電層； 在該第一介電層中形成一第一介層插塞； 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------· I -----訂---- - I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 517344 A8 B8 7500twf.doc/006__ 六、申請專利範圍 在該第一介電層與該第一介層插塞上形成一介電薄 層； 在該介電薄層上形成一第二介電層； 在該第二介電層中形成一第二介層插塞，其中該第二 介層插塞至少覆蓋該第一介層插塞上之部分該介電薄層。 14. 如申請專利範圍第13項所述之反熔絲結構的製 造方法，其中該介電薄層之材質包括氮化矽。 15. 如申請專利範圍第14項所述之反熔絲結構的製 造方法，其中該介電薄層之厚度爲50埃至200埃。 16. 如申請專利範圍第13項所述之反熔絲結構的製 造方法，其中該介電薄層之材質包括非晶矽。 17. 如申請專利範圍第16項所述之反熔絲結構的製 造方法，其中該介電薄層之厚度爲100埃至200埃。 18. 如申請專利範圍第13項所述之反熔絲結構的製 造方法，其中該第一介電層之材質包括氧化矽。 19. 如申請專利範圍第13項所述之反熔絲結構的製 造方法，其中該第二介電層之材質包括氧化矽。 20. 如申請專利範圍第13項所述之反熔絲結構的製 造方法，其中該第一介層插塞之材質係選自多晶矽與金屬 其中之一。 21. 如申請專利範圍第13項所述之反熔絲結構的製 造方法，其中該第二介層插塞之材質係選自多晶矽與金屬 其中之一。 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------1 --------訂—I—丨— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制衣 517344 A8 B8 7500twf.doc/006_g| 六、申請專利範圍 22. 如申請專利範圍第13項所述之反熔絲結構的製 造方法，其中該導電區包括一金屬內連線層。 23. —種反熔絲結構，配置於一介電層之中，該反熔 絲結構包括： 一第一介層插塞，其位於該介電層中； 一介電薄層，其位於該介電層之中並與該介電層呈一 三明治結構，且該介電薄層覆蓋於該第一介層插塞上；以 及 一第二介層插塞，配置於該第一介層插塞上之部分該 介電薄層上。 24. 如申請專利範圍第23項所述之反熔絲結構，其 中該該介電薄層之材質包括氮化矽。 25. 如申請專利範圍第24項所述之反熔絲結構，其 中該介電薄層之厚度爲50埃至200埃。 26. 如申請專利範圍第23項所述之反熔絲結構，其 中該介電薄層之材質包括非晶矽。 27. 如申請專利範圍第26項所述之反熔絲結構，其 中該介電薄層之厚度爲100埃至200埃。 28. 如申請專利範圍第23項所述之反熔絲結構，其 中該第一介層插塞之材質係選自多晶矽與金屬其中之一。 29. 如申請專利範圍第23項所述之反熔絲結構，其 中該第二介層插塞之材質係選自多晶矽與金屬其中之一。 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂-------- (請先閱讀背面之注意事項再填寫本頁)517344 A8 B8 7500twf.doc / 006_g | _ VI. Application for patent scope 1. A method for manufacturing an anti-fuse structure, comprising the following steps: providing a substrate, a conductive region has been formed on the substrate; forming a first on the substrate A dielectric layer; patterning the first dielectric layer to form a first opening, and exposing a conductive region of the mesh, and inserting a first conductive layer into the first opening to form a dielectric plug; '' Forming a dielectric thin layer on the first dielectric layer and the dielectric plug; forming a second dielectric layer on the dielectric thin layer; patterning the second dielectric layer to form a first Two openings, wherein the second opening exposes at least a portion of the dielectric thin layer on the dielectric plug; and a second conductive layer is formed on the second dielectric layer and fills the second opening. 2. The method for manufacturing an anti-fuse structure as described in item 1 of the scope of patent application, wherein the material of the dielectric thin layer includes silicon nitride. 3. The manufacturing method of the anti-fuse structure according to item 2 of the scope of patent application, wherein the thickness of the dielectric thin layer is about 50 angstroms to 200 angstroms. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ----------- · install --- (Please read the precautions on the back before filling out this page) 4. As described in item 1 of the scope of patent application The manufacturing method of the anti-fuse structure, wherein the material of the dielectric thin layer includes amorphous silicon. 5. The method for manufacturing an anti-fuse structure as described in item 4 of the scope of patent application, wherein the thickness of the dielectric thin layer is about 100 angstroms to 200 angstroms. 6. The method for manufacturing an anti-fuse structure as described in item 1 of the scope of the patent application, wherein the dielectric thin layer is used to form one of the second openings. Etching is terminated. 9 The paper size is applicable to China National Standard (CNS) A4. (210 X 297 mm) Printed clothing by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 517344 A8 B8 7500twf.doc / 〇〇6 C8 __D8 夂, the scope of patent application. Method for manufacturing fuse structure 'wherein the material of the first dielectric layer includes silicon oxide. 8. · Method for manufacturing the anti-fuse structure described in item 1 of the scope of the patent application'wherein the material of the second dielectric layer includes Silicon oxide. 9. The manufacturing method of the anti-fuse structure described in item 1 of the scope of the patent application, wherein the material of the first conductive layer is selected from polycrystalline sand and metal-〇10. As the scope of patent application The manufacturing method of the anti-fusible filament structure according to item 1, wherein the material of the second conductive layer is selected from one of polycrystalline silicon and metal. Π · The manufacturing of the anti-fuse structure according to item 1 of the scope of patent application Method, which The conductive region includes a metal interconnect layer. 12. The method for manufacturing an anti-fuse structure as described in item 1 of the scope of patent application, wherein the first conductive layer is inserted into the first opening to form the interposer. The method of plugging includes: forming the first conductive layer on the first dielectric layer and filling the first opening; and removing a portion of the first conductive layer by a chemical mechanical honing method until the first dielectric layer The electrical layer is exposed. 13 · A method for manufacturing an anti-fuse structure includes the following steps: providing a substrate having a conductive region formed on the substrate; forming a first dielectric layer on the substrate; A first dielectric plug is formed in the dielectric layer; 10 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) ---------- · I ----- Order -----I (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 517344 A8 B8 7500twf.doc / 006__ VI. The scope of patent application is on the first dielectric layer Forming a dielectric thin layer on the first dielectric layer plug; on the dielectric thin layer Forming a second dielectric layer; forming a second dielectric plug in the second dielectric layer, wherein the second dielectric layer plug covers at least a portion of the thin dielectric layer on the first dielectric layer plug. 14. The method of manufacturing an anti-fuse structure as described in item 13 of the scope of patent application, wherein the material of the dielectric thin layer includes silicon nitride. 15. The method of anti-fuse structure as described in item 14 of the scope of patent application The manufacturing method, wherein the thickness of the dielectric thin layer is 50 angstroms to 200 angstroms. 16. The manufacturing method of the anti-fuse structure described in item 13 of the scope of patent application, wherein the material of the dielectric thin layer includes amorphous silicon . 17. The method for manufacturing an anti-fuse structure according to item 16 of the scope of patent application, wherein the thickness of the dielectric thin layer is 100 angstroms to 200 angstroms. 18. The manufacturing method of the anti-fuse structure according to item 13 of the scope of the patent application, wherein the material of the first dielectric layer includes silicon oxide. 19. The method for manufacturing an anti-fuse structure according to item 13 of the scope of the patent application, wherein the material of the second dielectric layer includes silicon oxide. 20. The method for manufacturing an anti-fuse structure according to item 13 of the scope of the patent application, wherein the material of the first interposer plug is selected from one of polycrystalline silicon and metal. 21. The method for manufacturing an anti-fuse structure according to item 13 of the scope of the patent application, wherein the material of the second interposer plug is selected from one of polycrystalline silicon and metal. 11 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ---------- 1 -------- Order—I— 丨 — (Please read the back first Please pay attention to this page and fill in this page again) Printed clothing by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 517344 A8 B8 7500twf.doc / 006_g | The manufacturing method, wherein the conductive region includes a metal interconnect layer. 23. An anti-fuse structure disposed in a dielectric layer, the anti-fuse structure comprising: a first dielectric layer plug located in the dielectric layer; a dielectric thin layer located in the dielectric layer The dielectric layer has a sandwich structure with the dielectric layer, and the dielectric thin layer covers the first dielectric plug; and a second dielectric plug is disposed on the first dielectric plug. A portion of the plug is on the thin dielectric layer. 24. The anti-fuse structure described in item 23 of the scope of patent application, wherein the material of the dielectric thin layer includes silicon nitride. 25. The anti-fuse structure described in item 24 of the scope of patent application, wherein the thickness of the dielectric thin layer is 50 angstroms to 200 angstroms. 26. The anti-fuse structure described in item 23 of the scope of the patent application, wherein the material of the dielectric thin layer includes amorphous silicon. 27. The anti-fuse structure as described in item 26 of the scope of patent application, wherein the thickness of the dielectric thin layer is 100 angstroms to 200 angstroms. 28. The anti-fuse structure described in item 23 of the scope of patent application, wherein the material of the first interposer plug is selected from one of polycrystalline silicon and metal. 29. The anti-fuse structure described in item 23 of the scope of the patent application, wherein the material of the second interposer plug is selected from one of polycrystalline silicon and metal. 12 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----------- installation -------- order -------- ( (Please read the notes on the back before filling out this page)
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI469339B (en) * 2005-03-31 2015-01-11 Freescale Semiconductor Inc Antifuse element and electrically redundant antifuse array for controlled rupture location
TWI662674B (en) * 2015-01-19 2019-06-11 聯華電子股份有限公司 Semiconductor device with anti-fuse circuit and semiconductor device with fused circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI469339B (en) * 2005-03-31 2015-01-11 Freescale Semiconductor Inc Antifuse element and electrically redundant antifuse array for controlled rupture location
TWI662674B (en) * 2015-01-19 2019-06-11 聯華電子股份有限公司 Semiconductor device with anti-fuse circuit and semiconductor device with fused circuit

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