經濟部中央榇準局貝工消費合作社印製 412819_H7 ____ 五、發明説明（1 ) 本發明係有關一種積體電路製程，特別有關於一種 平坦化層之重疊量測（overlay measurement)方法。 在積體電路(ICs)的應用上，導體、半導體及絕緣層 等材料已被廣泛使用，而薄膜沈積（Thin Film Deposition)、微影製程（photolithography)、及钱刻程序 (etching)則為主要之半導體技術。 其中薄膜沈積，即是將上述各材料分層沈積於待製 晶圓（wafer)表面，而微影製程則是複製所欲形成之元件 或電路圖案，並透過蝕刻步驟，將該些圖案轉移至待製 晶圓表面各層以形成半導體元件如電晶體或電容等。 另為了避免各元件或金屬導體因直接接觸而短路， 故必須選擇絕緣層以之隔離，而用來隔離之介電材料一 般稱之為層間介電層。 例如内層介電層（ILD : inter-layer dielectrics) ’ 可 用作電晶體、電容等半導體元件與後續金屬層之隔離D 此外，在深次微米製程中，積體電路積集度（integration) 增加，製作電晶體之基底面積則需不斷減少以提高密 度，因此目前大多採用多層内連線（multi-level interconnects)之立體架構方式，而以内金屬介電層 (IMD: Inter-Metal Dielectrics)來作為隔離各金屬内連線 之介電材料，其上下層内連線之間，則透過接觸窗（contact) 或介層窗（via)之金屬插塞（metal plug)電性連接。 然而，依前述傳統内連線結構，由於形成之半導體 元件或金屬層常因其高低起伏之外觀，而使基底表面具 3 本紙張尺度適用中國國家標率（CNS ) A4规格（2!〇x297.i># ) ----------Λ-----^—:訂i τ-----線 ► - (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 4128,9 Λ1 —____ 五、發明説明（2; ' — 有不同之輪廓（topography)深度，連帶使沈積之層間介電 層亦呈現不平坦表面，因此，在先前技術（pd〇r art)中， 常以回蝕刻或化學機械研磨製程等平坦化步驟來平坦化 該些層間介電層以利後續各層之形成。 傳統金屬内連線結構係如第丨圖所示。依據第1圖， 其包括一矽基底100’其形成有半導體元件如電晶體或 電容’接著再依傳統半導體製程形成一内介電層 (ILD)ll〇，其用來隔離半導體元件’其次依序形成一下 層金屬内連線120如鋁線及一覆蓋下層金屬内連線12〇 及基底100之内金屬介電層（IMD)130。然後定義一介層 窗圖案，經姓刻内金屬介電層13〇，形成一暴露下層金 屬内連線120部份表面的介層窗（via)14〇。 接續’沈積一金屬層’經回蝕刻步驟，形成一填平 介層窗140之金屬插塞160。隨之沈積另一金屬層，定 義金屬内連線之圖案，經姓刻形成一上金屬内連線18〇。 最後，再沈積另一内金屬介電層（IMD)200，並實施 平坦化步驟，如回蝕刻或化學機械研磨法（CMp : ehemieal mechanical polishing)。 此外，目前另發展出一種鑲嵌式内連線結構 (damascene interconnect structure) ’ 其依據製程特性而可 分為單層型（single type)、雙層型（dual type)和自我對準 型（self-aligned type)’以雙層型鑲嵌式内連線結構為例， 如第2、3圖所示。 依據第2圖，和第1圖相同之傳統製程，首先係提 本紙掁尺度逍用中國國家標準（CNS ) Λ4规栝（2IOX2W公#) ----—*--1 f— n I --- . 訂 *1 ^ I . Λ/ (#先閲讀背面之注$項再填窍本頁〕 ____ 經濟部中央標準局貝工消費合作社印製 4128：9 π Η 7 五、發明説明（3) 供一矽基底300,其上形成有半導體元件如電晶體或電 容，接著再依半導體製程形成一内介電層（ILD)310，其 用來隔離半導體元件’其次依序形成一下層金屬内連線 320如鋁線及一覆蓋下層金屬内連線320及基底300之 内金屬介電層（IMD)330。其中，分別定義介層窗圖案和 金屬内連線圖案，並經蝕刻内金屬介電層330，形成一 暴露下層金屬内連線320部份表面的介層窗（Via)383和 内連線溝槽380。 接續，依據第3圖，沈積另一金屬銅層390，以覆 蓋内金屬介電層330，其並填滿内連線溝槽380及介層 窗383，接著回蝕刻或以化學機械研磨製程（CMP : chemical mechanic polishing)平坦化該金屬銅層 390，以 形成一填平介層窗383及内連線溝槽380之鑲嵌式内連 線結構。 然而，在進入極大型積體電路（ULSI)世代後，光學 微影技術（photolithography)對深次微米級（sub-half micrometer)的元件製造十分重要，其中由於尺寸大小 (feature size)之縮減（shrink)及製程之繁複，微影步驟 (photolithography)之解析度（resolution)及重疊準確率 (overlay accuracy)之要求均大為提高，傳統之曝光顯影 方式顯已不符所需。 一般而言，重疊誤差（overlay error)較容易發生在對 準和曝光之步驟，例如在曝光製程中，光罩和晶圓之間 的相對位置誤差，透鏡之失真或放大倍率之誤差，以及 本紙張尺度適用中國國家標準{ CNS ) Λ4規核{ 210X297公犮） ------(---Λ------Γΐτ.—.-----戈 (讀先閱讀背面之注意事項再填寫本頁) 412819 Λ? Η 7 -------一 I--一 一 一 - 五、發明説明（4) 因溫度偏移導致之曝光系統之不穩定均是發生重疊誤差 之主因。此外’光學步進機（optic stepper)如ASML型， 係採投影式曝光法（projection) ’亦即光罩（mask)和晶圓 (wafer)不直接接觸，而是利用投影裝置將光罩上數倍大 之圖案（pattern)，以步進且重複之方式曝光，而將圖案 微縮轉移至晶圓表面，因此’進行對準時，光罩上較大 之圖案尺寸’可方便調整其重叠位置（〇verlay p〇siti〇n), 並得到較高之解析度。 此外，於進行曝光和顯影製程後，一般會另進行— 顯影後重疊量測步驟’以檢驗上下層之偏差程度，其中 由於重疊量測機台之對準方式，主要係利用光學鏡頭如 CCD讀取頭來抓取前後層之影像，如前層為經定義之半 導體層，而後層為光阻層時，即利用光阻層和半導體層 之輪廓深度作為前後層間之影像對比（c〇ntrast)，以進行 重疊量測步驟，然而對以蝕刻或化學機械研磨製程形成 之平坦化層而言’其輪廓不僅平坦，且厚度亦淺，一般 不到5000A，容易形成模糊之對比，因此在光學鏡頭或 影像軟體不夠敏銳的情況下，常常因對焦不易導致抓不 到前層影像，而產生失誤的情形。 有鑑於此，本發明之目的即在於形成一具有步階高 度之平坦化層，以利於顯影後之重疊量測時，改善其影 像對比能力，提高量測之準確度，以為晶片是否重工 (rework)之依據。 為達成上述目的，本發明提供一種重疊量測平坦化 本纸張尺度適用中國國家標隼（CNS ) Λ4現推（210x297,»«:) ----；--一---A----h-;-訂-----嗖 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印« 經濟部中央標率扃員工消费合作社印繁 J； _ ________ 五、發明説明（3 層之方法，包括下列步驟：首先提供一基底，其表面具 有一凹槽’接著形成一不透光層，其順應性覆蓋凹槽及 基底。其次平坦化此不透光層，以在凹槽内留下一具有 步階高度之凹型不透光層，之後另形成一層間介電層， 其順應性覆蓋前述凹型不透光層及基底。隨之定義一光 阻層’其位於層間介電層表面之對應凹型不透光層的既 定位置’最後重疊量測光阻層與凹型不透光層，以檢驗 上下層之偏差。 為讓本發明之上述和其他目的、特徵、和優點能更 明顯易僅，下文特舉一較佳實施例，並配合所附圖式， 作詳細說明如下： 圖式之簡單說明·· 第1圖係為先前技術中’傳統形成金屬内連線結構 之半導體製程剖面圖。 第2至3圖係為先前技術中，傳統形成鑲嵌式金屬 内連線結構之半導體製程剖面圖。 第4A圖係為先前技術中，傳統鑲嵌式金屬内連線 結構中，上下層間之重疊量測步驟剖面圖。Printed by Shellfish Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs 412819_H7 ____ V. Description of the Invention (1) The present invention relates to an integrated circuit manufacturing process, and in particular to an overlay measurement method for a planarization layer. In the application of integrated circuits (ICs), materials such as conductors, semiconductors and insulation layers have been widely used, while thin film deposition, photolithography, and etching are the main Semiconductor technology. The thin film deposition is to deposit the above materials on the wafer surface in layers, and the lithography process is to copy the desired element or circuit pattern, and then transfer these patterns to the substrate through an etching step. Layers on the surface of the wafer to be formed to form semiconductor elements such as transistors or capacitors. In addition, in order to avoid short circuit of each component or metal conductor due to direct contact, an insulating layer must be selected for isolation. The dielectric material used for isolation is generally called an interlayer dielectric layer. For example, inter-layer dielectrics (ILD: inter-layer dielectrics) 'can be used to isolate semiconductor elements such as transistors and capacitors from subsequent metal layers. In addition, in deep sub-micron processes, the integration of integrated circuits has increased. The area of the substrate for the transistor needs to be continuously reduced to improve the density. Currently, most of the three-dimensional structure of multi-level interconnects is used, and IMD: Inter-Metal Dielectrics The dielectric material that isolates each metal interconnect is electrically connected between the upper and lower interconnects through a metal plug of a contact or via. However, according to the aforementioned conventional interconnect structure, the formed semiconductor element or metal layer often has a fluctuating appearance, so that the surface of the substrate has 3 paper standards that are applicable to the Chinese National Standard (CNS) A4 specification (2.0 × 297). .i >#) ---------- Λ ----- ^ —: Order i τ ----- line ►-(Please read the notes on the back before filling this page) Ministry of Economy Printed by the Central Standards Bureau Shellfish Consumer Cooperative 4128,9 Λ1 —____ V. Description of the invention (2; '— There are different topography depths, and the deposited interlayer dielectric layer also presents an uneven surface. Therefore, in In the prior art, planarizing steps such as etch-back or chemical mechanical polishing processes are often used to planarize the interlayer dielectric layers to facilitate the formation of subsequent layers. The traditional metal interconnect structure is shown in Figure 丨According to the first figure, it includes a silicon substrate 100 'which is formed with a semiconductor element such as a transistor or a capacitor', and then an internal dielectric layer (ILD) 110 is formed according to a conventional semiconductor process, which is used to isolate the semiconductor element. 'Secondly form the next layer of metal interconnects 120 such as aluminum wire and a cover Cover the lower metal interconnects 120 and the inner metal dielectric layer (IMD) 130 of the substrate 100. Then define an interlayer window pattern and engraved the inner metal dielectric layer 13 to form an exposed lower metal interconnect 120. The surface of the interlayer window (via) is 14. The continuation of 'depositing a metal layer' is followed by an etch-back step to form a metal plug 160 filling the interlayer window 140. Then another metal layer is deposited to define the metal interconnection The pattern of the lines is engraved to form an upper metal interconnect 18. Finally, another internal metal dielectric layer (IMD) 200 is deposited and a planarization step such as etch back or chemical mechanical polishing (CMp: ehemieal mechanical polishing). In addition, a damascene interconnect structure has been developed. It can be divided into single type, dual type and self-alignment according to the process characteristics. "Self-aligned type" uses a double-layered mosaic interconnect structure as an example, as shown in Figures 2 and 3. According to Figure 2, the same traditional process as Figure 1, first of all, the paper is drawn Standard Chinese Standards (CNS) Λ4 栝 (2IOX2W 公 #) ----— *-1 f— n I ---. Order * 1 ^ I. Λ / (#Read the note on the back of the page before filling in this page] ____ Economy Printed by the Central Bureau of Standards, Shellfish Consumer Cooperative, 4128: 9 π Η 7 V. Description of the Invention (3) A silicon substrate 300 is formed on which a semiconductor element such as a transistor or a capacitor is formed, and then an intermediary is formed according to the semiconductor process. Electrical layer (ILD) 310, which is used to isolate semiconductor elements. Secondly, a lower metal interconnect 320 such as an aluminum wire and an inner metal dielectric layer (IMD) 330 covering the lower metal interconnect 320 and the substrate 300 are sequentially formed. . Among them, the interlayer window pattern and the metal interconnect pattern are defined, and the inner metal dielectric layer 330 is etched to form a via window (Via) 383 and an interconnect trench that expose a portion of the surface of the lower metal interconnect 320. Slot 380. Next, according to FIG. 3, another metal copper layer 390 is deposited to cover the inner metal dielectric layer 330, which fills the interconnect trenches 380 and the interlayer windows 383, and is then etched back or chemical mechanically polished ( CMP (chemical mechanic polishing) planarizes the metallic copper layer 390 to form a mosaic interconnect structure that fills the interlayer window 383 and interconnect trenches 380. However, after entering the ultra large integrated circuit (ULSI) generation, photolithography is very important for the manufacture of sub-half micrometer devices. Among them, due to the reduction in feature size ( Shrink) and the complexity of the manufacturing process, the resolution and overlay accuracy requirements of the photolithography step have been greatly improved, and the traditional exposure and development methods have obviously not met the requirements. Generally speaking, overlay errors are more likely to occur during the alignment and exposure steps. For example, during the exposure process, the relative position error between the mask and the wafer, the lens distortion or magnification error, and the error Paper size applies Chinese national standard {CNS) Λ4 regulation {210X297 public 犮) ------ (--- Λ ------ Γΐτ .—.----- Ge (Read the first on the back Note for this page, please fill in this page again) 412819 Λ? ---- 7 ------- One I--One One One One-V. Explanation of the invention (4) The instability of the exposure system due to temperature deviation is caused by overlapping errors The main reason. In addition, 'optic stepper (ASML type, projection projection method), that is, the mask and wafer are not in direct contact, but the projection device is used to The pattern on the mask is several times larger and exposed in a stepwise and repetitive manner, and the pattern is transferred to the wafer surface. Therefore, 'the larger pattern size on the mask can be easily adjusted during alignment' Overlap position (〇verlay p〇siti〇n), and get a higher resolution. In addition, the exposure After the light and development process, it is generally performed separately-the overlap measurement step after development 'to check the degree of deviation of the upper and lower layers. Among them, due to the alignment of the overlap measurement machine, optical lenses such as CCD reading heads are mainly used to grasp Take the images of the front and back layers. If the front layer is a defined semiconductor layer and the back layer is a photoresist layer, the contour depth of the photoresist layer and the semiconductor layer is used as the contrast between the front and back layers (contrast) to overlap. The measurement step, but for the planarization layer formed by the etching or chemical mechanical polishing process, its contour is not only flat, but also shallow in thickness, generally less than 5000A, and it is easy to form blurred contrast, so it is not enough in optical lenses or imaging software. In the case of sharpness, it is often difficult to focus because the front layer image cannot be captured and errors occur. In view of this, the object of the present invention is to form a flattening layer with a step height to facilitate overlap after development. When measuring, improve its image contrast ability and increase the accuracy of the measurement, based on whether the chip is reworked. In order to achieve the above purpose, The invention provides an overlay measurement for flattening the paper scale applicable to the Chinese National Standard (CNS) Λ4 now (210x297, »« :) ----;-一 --- A ---- h-;- Order ----- 嗖 (Please read the notes on the back before filling out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Printed Consumers Cooperatives «Central Standards of the Ministry of Economics 扃 Employees' Cooperatives Printed by Fan J; _ ________ 5. Description (The three-layer method includes the following steps. First, a substrate is provided with a groove on its surface, and then an opaque layer is formed, and its compliance covers the groove and the substrate. Secondly, the opaque layer is planarized to leave a concave opaque layer having a step height in the groove, and then an interlayer dielectric layer is formed, and its compliance covers the aforementioned concave opaque layer and substrate. Then, a photoresist layer is defined, which is located at the predetermined position of the corresponding concave opaque layer on the surface of the interlayer dielectric layer. Finally, the photoresist layer and the concave opaque layer are overlapped and measured to check the deviation of the upper and lower layers. In order to make the above and other objects, features, and advantages of the present invention more obvious and simple, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings. 1 The figure is a cross-sectional view of a semiconductor process for forming a conventional metal interconnect structure in the prior art. Figures 2 to 3 are cross-sectional views of a conventional semiconductor process for forming a damascene metal interconnect structure in the prior art. FIG. 4A is a cross-sectional view of a measurement step of overlap between upper and lower layers in a conventional inlaid metal interconnect structure in the prior art.
第4B圖係為先前技術中，傳統鑲嵌式金屬内連線 結構中，上下層間之重疊量測步驟上視圖Q 第4C圖係為先刚技術中，傳統鑲歲式金屬内連線 結構中’上下層間之重疊量測影像示意圖。 第5A至5D圖係顯示本發明之第一實施例中於 鑲嵌式金屬内連線結構形成具有步階高度之平坦化層， 本紙浪尺度適用中國國家標準（CNS ) Λ4規輅（2】0\ 297公对. ---------Λ----^--訂------線 ···- {請先閱讀背面之注意事項再填寫本頁) 412819 Λ7 五 ~ — "： ----------------' 以對上下層進行重疊量測步驟之剖面圖。 '第5E圖係顯示本發明之第一實施例中，於鑲嵌式 金屬内連線結構形成具有步階高度之平坦化層，以對上 下層進行重疊量測步驟之上視圖。 第5F圖係顯示本發明之第一實施例中，於鑲嵌式 金屬内連線結構形成具有步階高度之平坦化層，對上下 層進行重疊量測之影像示意圖。 第6A圖係為先前技術中，傳統環狀鑲嵌式金屬内 連線結構中，上下層間之重疊量測步驟剖面圖。 第6B圖係為先前技術中，傳統環狀鑲嵌式金屬内 連線結構中，上下層間之重疊量測步驟上視圖。 第6C圖係為先前技術中，傳統環狀鑲嵌式金屬内 連線結構中，上下層間之重疊量測影像示意圖。 第7A至7D圖係顯示本發明之第二實施例中，於 環狀鑲嵌式金屬内連線結構形成具有步階高度之平坦化 層’以對上下層進行重疊量測步驟之剖面圖。 經濟部中央標隼局員工消費合作社印製 第7E圖係顯示本發明之第二實施例中，於環狀镶 嵌式金屬内連線結構形成具有步階高度之平坦化層，以 對上下層進行重疊量測步驟之上視圖。 第7F圖係顯不本發明之第二實施例中，於環狀鎮 嵌式金屬内連線結構形成具有步階高度之平坦化層，對 上下層進行重疊量測之影像示意圖。 第8A圖係顯示本發明之第三實施例中，於環狀鎮 叙式金屬内連線結構形成具有步階高度之平坦化層，以 本紙伖尺度逑用中國國家標準（CNS ) Λ4说格（2丨Ox2SH'>># ) 經濟部中央標準局貝工消費合作社印策 412819 Λ 7 —____ΗΊFigure 4B shows the measurement steps for the overlap between the upper and lower layers in the conventional inlay metal interconnect structure in the prior art. Figure 4C shows the traditional inlay metal interconnect structure in the prior technology. Schematic diagram of overlapping measurement images between upper and lower layers. Figures 5A to 5D show that in the first embodiment of the present invention, a flattened layer having step height is formed on a mosaic metal interconnect structure. The paper scale is applicable to the Chinese National Standard (CNS) Λ4 Regulations (2) 0 \ 297 公 对. --------- Λ ---- ^-Order ------ line ···-(Please read the precautions on the back before filling this page) 412819 Λ7 5 ~ — &Quot;: ---------------- 'for a cross-sectional view of the overlapping measurement steps for the upper and lower layers. 'Figure 5E is a top view of a first embodiment of the present invention in which a flattening layer having a step height is formed on a damascene metal interconnect structure to perform an overlay measurement step on upper and lower layers. Fig. 5F is a schematic diagram showing a first embodiment of the present invention in which a flattened layer having a step height is formed on a mosaic metal interconnect structure, and the upper and lower layers are overlapped and measured. FIG. 6A is a cross-sectional view of a step of measuring the overlap between the upper and lower layers in the conventional ring-shaped mosaic metal interconnect structure in the prior art. Fig. 6B is a top view of the step of measuring the overlap between the upper and lower layers in the conventional annular mosaic metal interconnect structure in the prior art. Fig. 6C is a schematic diagram of the overlapping measurement image between the upper and lower layers in the conventional annular mosaic metal interconnect structure in the prior art. Figures 7A to 7D are cross-sectional views showing the step of forming a flattened layer having step heights on a ring-shaped mosaic metal interconnect structure in a second embodiment of the present invention to perform an overlay measurement step on upper and lower layers. Figure 7E printed by the Employees' Cooperatives of the Central Bureau of Standards of the Ministry of Economics shows that in the second embodiment of the present invention, a flattened layer with step height is formed in a ring-shaped inlaid metal interconnect structure to perform upper and lower layers. Top view of overlapping measurement steps. FIG. 7F is a schematic diagram showing a second embodiment of the present invention, forming a planarized layer having a step height on a ring-shaped embedded metal interconnect structure, and performing an overlay measurement on the upper and lower layers. FIG. 8A shows a third embodiment of the present invention, a planarization layer having step height is formed on a ring-shaped metal interconnect structure, and the Chinese National Standard (CNS) Λ4 is used at the paper scale. (2 丨 Ox2SH '> >#) Impression 412819 Λ 7 —____ ΗΊ
,. ι »··-." 一· · ' . I I , , I 五 '發明説明（7 ) 對上下層進行重疊量測步驟之剖面圖。 第8B圖係顯示本發明之第三實施例中，於環狀鑲 散式金屬内連線結構形成具有步階高度之平坦化層，以 對上下層進行重疊量測步驟之上視圖。 第8C圖係顯示本發明之第三實施例中，於環狀鑲 嵌式金屬内連線結構形成具有步階高度之平坦化層，對 上下層進行重疊量測之影像示意圖。 符號說明 100〜基底；110〜内介電質層；120〜下層金屬内連線； 130〜内金屬介電層；14〇〜介層窗；10〇〜金屬插塞；18〇〜 上金屬内連線；200〜層間介電層；300〜基底；31〇〜内介 電質層；320〜下層金屬内連線；33〇〜層間介電層；38〇〜 内連線溝槽；3 83〜介層窗；390〜上金屬内連線；4〇〇〜基 底；420〜下層金屬内連線；440〜層間介電層；460〜光阻 層，5〇0〜基底，51〇〜金屬層；52〇〜下層金屬内連線；Mo〜 光阻層；540〜層間介電層；560〜光阻層；580〜内連線溝 槽；600〜基底；620a、62〇b〜環狀下層金屬内連線；64〇〜 層間介電層；660〜光阻層；700〜基底；710〜金屬層；720〜 環狀下層金屬内連線；740〜層間介電層；760〜光阻層； 780〜内連線溝槽；800〜基底；820a、820b〜環狀下層金 屬内連線；840〜層間介電層；860〜光阻層。 實施例 請參閱第4A至4C圖，其為先前技術中，傳統鑲 嵌式金屬内連線結構中，上下層間之重叠量測步驟。 本紙張尺度適用中國國家標準（CNS ) Λ4规格（2IOX 297公劝） ---------農------Γ訂-----線 {諳先閱讀背面之注意"項再填寫本頁〕 經濟部中央標隼局員工消費合作社印製 412819 Λ， ιυ 五、發明説明（8 ) 首先依據第4Α圖，係為如第3圖之傳統鑲嵌式金 屬内連線結構之部分剖面圖。其包括一矽基底400，其 具有下層金屬内連線或半導體元件如電晶體或電容，並 利用一内介電層（ILD)(未顯示）予以隔離，另於基底400 表面則形成一介層窗（via)(未顯示）或内連線溝槽480。經 平坦化之金屬層420如鋁或銅層，則填滿内連線溝槽 480，以形成一填平介層窗及内連線溝槽480之鑲嵌式内 連線結構。而平坦化内金屬介電層（IMD)440亦覆蓋平坦 化金屬層420及基底，其次，透過曝光微影製程，定義 一圖案化之光阻層460，其位於層間介電層440表面對 應金屬層420之既定位置，一般係用以界定另一層金屬 内連線或介層窗之範圍，其上視圖則如第4B圖所示， 包括下層之金屬層420及上層之光阻層460。 請參閱第4C圖，於完成上述結構後，尚需進行顯 影後之重疊量測，即重疊量測光阻層460與金屬層420， 以進行上下層之對準步驟，然而，由於重疊量測機台之 對準方式，主要係利用光學鏡頭如CCD讀取頭來抓取上 下層之影像，而光阻層460 —般均有相當之厚度，因此 大致並無問題，但對以回蝕刻或化學機械研磨製程形成 之平坦化金屬層420而言，其輪廓不僅平坦，且厚度亦 淺，一般不到5000A，其影像對比並不明顯，加以對準 點僅有A1、A2兩處，因此在光學鏡頭或影像軟體不夠 敏銳的情況下，常常因對焦不易導致抓不到下層金屬層 420之影像（虛線所示），而產生失誤的情形。 Ϊ0 本紙張尺度適用中國國家標準（CNS ) Λ4規柊（210X297公焚） ϋ I nt _ n » n _ m __ I--- I Γ---- I ; ----n (請先閱讀背面之注意事項再填寫本頁) Λ? 412819 五'發明説明（9) 反觀，請參閱第5A至5D圖，其顯示本發明之第 一實施例。其於鑲嵌式金屬内連線結構形成具有步階高 度之平坦化層’以對上下層進行重疊量測步驟。 首先依據第5A圖’係提供一石夕基底5〇〇，其形成 有半導體元件如電晶體或電容及下層金屬内連線，接著 再依半導體製程形成一内介電層（ILD)(未顯示），其用來 隔離半導體元件或下層金屬内連線，其次再依鑲嵌式金 屬内連線結構製程’分別定義介層窗圖案和金屬内連線 圖案’並經钮刻步驟，於基底500表面形成一介層窗 (via)(未顯示）及内連線溝槽580，為使後續平坦化層具有 足夠之步階高度’可蚀刻内連線溝槽580之深度約為 20KA。 依序’請參閱第5B圖，順應性沈積一不透光層如 複晶矽或金屬層510以覆蓋基底，在此以金屬層為例， 且其無法填滿内連線溝槽580。 接著請參閱第5C圖，以蝕刻或化學機械研磨製程 (CMP : chemical mechanic polishiig)平坦化該金屬層 510’以留下一具有步階高度之凹型金屬層52〇。 最後請參閱第5D圖，另形成内金屬介電層 (IMD)540，並實施平坦化步驟，如蝕刻或化學機械研磨 法（CMP : chemical mechanical polishing)，其中，當内連 線溝槽580(如第5A圖所示）具有相當之寬度時，凹型金 屬層520之圖案會使後續沈積之内金屬介電層（imd)540 具有遞延性，而形成一局部凹陷之圖案。 本纸張尺度適用中國國家標隼{ CNS ) Λ4現格（210X29?公订） ------_---A------r 訂 I.-----嗥 (請先閱讀背面之注意事項再填寫本頁) 經濟部中夹標隼局貝工消費合作社印製 經濟部中央標準局員工消费合作社印製 412819 at -- —_—_ — 五、發明説明（I〇) …… —一'' 其次再透過曝光微影製程，定義一圖案化之光阻層 560,其位於層間介電層54〇表面對應凹型金屬層5加之 既定位置，一般係用以界定另一層金屬内連線或介層窗 之範圍，其上視圖則如第5Ε圖所示，包括下層之凹型 金屬層520及上層之光阻層56〇。 請參閱第5F圖，於完成上述結構後，尚需進行顯 影後之重疊量測，即重疊量測光阻層56〇與凹型金屬層 520，以檢驗上下層之偏差，其中，由於本實施例之凹型 金屬層520具有20ΚΑ之步階高度，加以内金屬介電層 (IMD)540形成之局部凹陷圖案，均形成敏銳之影像對 比，明顯有利於重疊量測機台之光學鏡頭抓取上下層之 影像，此外對準點加倍，包括A1、A2、A3 ' A4四處， 更提昇光學鏡頭抓住上下層，亦即凹型金屬層52〇和光 阻層560影像之機率。 請參閱第6A至6C圖，其為另一種先前技術中’ 傳統鑲嵌式金屬内連線結構，其上下層間之重疊量測步 驟。 首先依據第6A圖，係為如第3圖之傳統鑲嵌式金 屬内連線結構之部分剖面圖。其包括一矽基底6〇〇，其 形成有下層金屬内連線或半導體元件如電晶體或電容’ 並有一内介電層（ILD)(未顯示）與之隔離，於基底6〇〇表 面則形成一介層窗（via)(未顯示）或環狀内連線溝槽68〇。 環狀平坦化金屬層620,則填滿環狀内連線溝槽68〇 ’以 形成一填平介層窗及環狀内連線溝槽68〇之鑲嵌式内連 12 本紙張尺度適用中國國家標準（CNS ) Λ4現格（210X297公释） ：--.---政------r訂-------嗜 (讀先閱讀背面之注意事項再填{tip本頁) 經满部中夾標率局員工消費合作社印製 412819 五、發明説明（11) 線結構。而平坦化内金屬介電層（IMD)640亦覆蓋環狀平 坦化金屬層620及基底，其次，透過曝光微影製程，定 義一圖案化之光阻層660,其位於層間介電層64〇表面 對應金屬層620之既定位置，一般係用以界定另一層金 屬内連線或介層窗之範圍，其上視圖則如第6B圖所示， 包括下層之環狀金屬層620及上層之光阻層660。 請參閱第6C圖，於完成上述結構後，尚需進行顯 影後之重疊量測，即重疊量測光阻層66〇與金屬層62〇， 以檢驗上下層之偏差，然而，同第4入至4(：圖所示，由 於對以蝕刻或化學機械研磨製程形成之環狀平坦化金屬 層620而言，其輪廓不僅平坦，且厚度亦淺，一般不到 5000A，其對比並不明顯，因此在光學鏡頭或影像軟體 不夠敏銳的情況下，常常因對焦不易導致抓不到下層環 狀金屬層620之影像（虛線所示），而產生失誤的情形。 反觀，請參閱第7A至7D圖，其顯示本發明之第 二實施例。其於鑲嵌式金屬内連線結構形成具有步階高 度之凹型不透光層720,以對上下層進行重疊量測步驟。 首先依據第7A圖，係為一鑲嵌式金屬内連 之製程部分剖面圖。其提供一矽基底7〇〇 ’形成有下°層 金屬内連線或半導體元件如半導體元件如電晶體或電 容’接著再依半導體製程形成-內介電層（iLD)(未顯示） 與之隔離，其次再依鑲嵌式金屬内連線結構製程，分別 定義介層窗圖案和金屬内連線圖案，並_刻步驟於 基底700表面形成一介層窗（via)(未顯示）及環狀内連線 13 本紙張尺度適用中國國家標準（CNS ) Λ4現枯（210X297次p ----_---袭------：-訂一：-----噃 (請先閱讀背而之注意事項再填寫本頁〕 412819 五、發明説明（I2) 溝槽780，而為使後續平坦化層具有足夠之步階高度， 可蝕刻内連線溝槽780之深度約為20KA，因此在溝槽 寬度相對較小之情形下，可使内連線溝槽780之寬度大 於後續所欲沈積環狀金屬内連線之厚度兩倍，以避免沈 積之金屬層封住溝槽780。 依序，請參閱第7B圖，順應性沈積一不透光層如 複晶矽或金屬層710以覆蓋基底，其中由於内連線溝槽 780之寬度大於環狀金屬層之約兩倍厚度，故形成凹型 開口 790。 接著請參閱第7C圖，以蝕刻或化學機械研磨製程 (CMP: chemical mechanic polishing)平坦化該環狀金屬 層710，以形成一具有步階高度之凹型環狀金屬層720。 最後請參閱第7D圖，另形成内金屬介電層 (IMD)740，並實施平坦化步驟，如蝕刻或化學機械研磨 法（CMP : chemical mechanical polishing)。 經濟部中央標準局員工消費合作社印繁 (請先閱讀背面之注意事項再填寫本頁) 其次再透過曝光微影製程，定義一圖案化之光阻層 760’其位於層間介電層740表面對應凹型環狀金屬層720 之既定位置，一般係用以界定另一層金屬内連線或介層 窗之範圍，其上視圖則如第7E圖所示，包括下層之凹 型環狀金屬層720及上層之光阻層760。 請參閱第7F圖，於完成上述結構後，尚需進行顯 影後重疊量測步驟，即重疊量測光阻層760與凹型環狀 金屬層720，以檢驗上下層之偏差，其中，由於本實施 例之凹型環狀金屬層720具有20KA之步階高度，形成 本紙張尺度適用中國國家標芈（CNS ) Λ4規格（210X297公銲） 經濟部中央標隼局員工消费合作社印製 412819 A -· Η 7 五、發明説明（13) 敏銳之影像對比，明顯有利於重疊量測機台之光學鏡頭 抓取上下層之影像，此外對準點加倍，包括B1〜B8等八 處，更提昇光學鏡頭抓住上下層，亦即凹型環狀平坦化 金屬層720和光阻層760影像之機率。 另請參閱第8A至8C圖，其顯示本發明之第三實 施例。其於鑲嵌式金屬内連線結構形成具有步階高度之 凹型環狀不透光層820，以對上下層進行重疊量測步驟。 依據第8A圖，其對應第7D圖，包括一矽基底800， 於基底800表面形成一暴露下層金屬内連線部份表面的 環狀内連線溝槽880,為使後續平坦化層具有足夠之步 階高度，可蝕刻内連線溝槽880之深度約為20KA，接 著順應性沈積一不透光層如複晶矽或金屬層710以覆蓋 基底及内連線溝槽880，在此以金屬層為例，並以蝕刻 或化學機械研磨製程（CMP : chemical mechanic polishing) 平坦化該環狀金屬層，以形成一具有步階高度之凹型環 狀金屬層820。最後，形成内金屬介電層（IMD)840，並 實施平坦化步驟，如蝕刻或化學機械研磨法（CMP : chemical mechanical polishing)。再利用曝光微影製程定 義一圖案化之光阻層860，其位於層間介電層840表面 對應凹型環狀金屬層820之既定位置，其上視圖則如第 8B圖所示，包括下層之凹型環狀金屬層820及上層之光 阻層860。 當内連線溝槽880具有相當之寬度時，如其寬度大 於内金屬介電層840之兩倍厚度，凹型環狀金屬層820 15 本紙張尺度適用中國國家標準（CNS ) Λ4規梠（2H)X297公好） ---------Λ-------IT—------'t (#先閲讀背面之注意事項再填寫本頁) 412819 a，,. ι »··-. " 一 ·· '. I I,, I Five' Inventive Note (7) A cross-sectional view of an overlapping measurement step for upper and lower layers. FIG. 8B is a top view of a third embodiment of the present invention in which a planarization layer having a step height is formed on a ring-shaped embedded metal interconnect structure to perform an overlay measurement step on upper and lower layers. FIG. 8C is a schematic diagram showing a third embodiment of the present invention, forming a flattened layer having a step height on a ring-shaped embedded metal interconnect structure, and performing overlapping measurement on the upper and lower layers. Explanation of symbols 100 ~ substrate; 110 ~ inner dielectric layer; 120 ~ lower metal interconnect; 130 ~ inner metal dielectric layer; 14 ~ interlayer window; 100 ~ metal plug; 18 ~ upper metal Wiring; 200 ~ interlayer dielectric layer; 300 ~ substrate; 31〇 ~ inner dielectric layer; 320 ~ lower metal interconnect; 33 ~~ interlayer dielectric layer; 38 ~~ interconnect trench; 3 83 ~ Interlayer window; 390 ~ upper metal interconnect; 400 ~ substrate; 420 ~ lower metal interconnect; 440 ~ interlayer dielectric layer; 460 ~ photoresist layer, 5000 ~ substrate, 51 ~ metal Layer; 52 ° to lower metal interconnect; Mo ~ photoresist layer; 540 ~ interlayer dielectric layer; 560 ~ photoresist layer; 580 ~ interconnect line trench; 600 ~ substrate; 620a, 62〇b ~ ring Lower metal interconnects; 64 to interlayer dielectric layers; 660 to photoresist layers; 700 to substrates; 710 to metal layers; 720 to annular lower metal interconnects; 740 to interlayer dielectric layers; 760 to photoresist Layer; 780 ~ interconnect trench; 800 ~ substrate; 820a, 820b ~ ring-shaped lower metal interconnect; 840 ~ interlayer dielectric layer; 860 ~ photoresist layer. Embodiments Please refer to FIGS. 4A to 4C, which are steps for measuring the overlap between upper and lower layers in a conventional embedded metal interconnection structure in the prior art. This paper size applies the Chinese National Standard (CNS) Λ4 specification (2IOX 297). --------- Agriculture ------ Γ Order ----- Line {谙 Read the note on the back first " Fill in this page again] Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 412819 Λ, ιυ V. Description of the invention (8) First, according to Figure 4A, it is a traditional inlaid metal interconnect structure as shown in Figure 3. Partial sectional view. It includes a silicon substrate 400, which has underlying metal interconnects or semiconductor components such as transistors or capacitors, and is isolated by an internal dielectric layer (ILD) (not shown), and a dielectric window is formed on the surface of the substrate 400. (Via) (not shown) or interconnect groove 480. The planarized metal layer 420, such as aluminum or copper layer, fills the interconnect trenches 480 to form a mosaic interconnect structure that fills the interlayer window and interconnect trenches 480. The planarized inner metal dielectric layer (IMD) 440 also covers the planarized metal layer 420 and the substrate. Secondly, a patterned photoresist layer 460 is defined through an exposure lithography process, which is located on the surface of the interlayer dielectric layer 440 corresponding to the metal The predetermined position of the layer 420 is generally used to define the scope of another layer of metal interconnects or interlayer windows. The top view thereof is shown in FIG. 4B and includes the lower metal layer 420 and the upper photoresist layer 460. Please refer to FIG. 4C. After the above structure is completed, overlap measurement after development is needed, that is, the photoresist layer 460 and the metal layer 420 are overlapped to measure the alignment steps of the upper and lower layers. However, due to the overlap measurement, The alignment method of the machine mainly uses an optical lens such as a CCD reading head to capture the upper and lower layers of the image, and the photoresist layer 460 is generally of considerable thickness, so there is generally no problem. For the planarized metal layer 420 formed by the chemical mechanical polishing process, its outline is not only flat, but also shallow in thickness, generally less than 5000A. Its image contrast is not obvious. The alignment points are only A1 and A2. When the lens or imaging software is not sharp enough, the image of the lower metal layer 420 (shown by the dotted line) cannot be captured due to the difficulty of focusing, which leads to errors. Ϊ0 This paper size applies the Chinese National Standard (CNS) Λ4 Regulation (210X297 public incineration) ϋ I nt _ n »n _ m __ I --- I Γ ---- I; ---- n (Please read first Note on the back, please fill out this page again) Λ? 412819 Five 'invention description (9) In contrast, please refer to Figures 5A to 5D, which shows the first embodiment of the present invention. It forms a flattening layer 'with step height on the mosaic metal interconnect structure to perform overlapping measurement steps on the upper and lower layers. First, according to Figure 5A, a lithography substrate 500 is provided, which is formed with semiconductor elements such as transistors or capacitors and underlying metal interconnects, and then an internal dielectric layer (ILD) is formed according to the semiconductor process (not shown). , Which is used to isolate semiconductor elements or underlying metal interconnects, and then according to the mosaic metal interconnect structure process 'define the interlayer window pattern and the metal interconnect pattern' and form a button on the surface of the substrate 500 A via (not shown) and interconnecting trenches 580 have a sufficient step height for subsequent planarization layers. The depth of the etchable interconnecting trenches 580 is about 20KA. In sequence, please refer to FIG. 5B. An opaque layer such as polycrystalline silicon or metal layer 510 is compliantly deposited to cover the substrate. Here, a metal layer is used as an example, and it cannot fill the interconnect trench 580. Referring to FIG. 5C, the metal layer 510 'is planarized by an etching or chemical mechanical polishing process (CMP: chemical mechanic polishiig) to leave a concave metal layer 52 with a step height. Finally, referring to FIG. 5D, an inner metal dielectric layer (IMD) 540 is further formed, and a planarization step such as etching or chemical mechanical polishing (CMP) is performed. When the interconnect line trench 580 ( As shown in FIG. 5A) when the width is considerable, the pattern of the concave metal layer 520 will make the subsequently deposited inner metal dielectric layer (imd) 540 have a ductility and form a pattern of local depressions. This paper size applies to the Chinese national standard 国家 {CNS) Λ4 now (210X29? Public order) ------_--- A ------ r order I .----- 嗥 (please (Please read the notes on the back before filling in this page) Printed by the Ministry of Economic Affairs of the Ministry of Economic Affairs, printed by the Shellfish Consumer Cooperative, printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperative, 412819 at-—___ — )… — One ”Secondly, through the exposure lithography process, a patterned photoresist layer 560 is defined, which is located on the surface of the interlayer dielectric layer 54 corresponding to the concave metal layer 5 plus a predetermined position, which is generally used to define another layer The range of the metal interconnects or interlayer windows, as shown in Figure 5E, includes the lower concave metal layer 520 and the upper photoresist layer 56. Please refer to FIG. 5F. After the above structure is completed, overlap measurement after development needs to be performed, that is, overlap measurement of the photoresist layer 56 and the concave metal layer 520 to check the deviation of the upper and lower layers. The concave metal layer 520 has a step height of 20KA, and the local depression pattern formed by the inner metal dielectric layer (IMD) 540 forms a sharp image contrast, which is obviously conducive to overlapping the upper and lower layers of the optical lens of the measuring machine. In addition, the alignment points are doubled, including A1, A2, A3 and A4. It also increases the probability that the optical lens can grasp the upper and lower layers, that is, the concave metal layer 52 and the photoresist layer 560. Please refer to Figs. 6A to 6C, which are steps for measuring the overlap between upper and lower layers of the conventional inlaid metal interconnect structure in another prior art. Firstly, according to FIG. 6A, it is a partial cross-sectional view of the conventional mosaic metal interconnection structure as shown in FIG. It includes a silicon substrate 600, which is formed with underlying metal interconnects or semiconductor elements such as transistors or capacitors, and is separated from it by an internal dielectric layer (ILD) (not shown). On the surface of the substrate 600, A via (not shown) or annular interconnecting trench 68 is formed. The ring-shaped flattened metal layer 620 fills the ring-shaped interconnecting groove 68 ° 'to form a mosaic interconnecting which fills the interlayer window and the ring-shaped interconnecting groove 68 °. This paper size is applicable to China National Standards (CNS) Λ4 is now available (210X297 public release): --.--- Political ------ r Order ------- Addicted (Read the precautions on the back and fill in the {tip 本Page) Printed by the Consumers' Cooperative of the Bureau of Standards and Clips of the People's Republic of China 412819 V. Description of the invention (11) Line structure. The planarized inner metal dielectric layer (IMD) 640 also covers the annular planarized metal layer 620 and the substrate. Secondly, through a photolithography process, a patterned photoresist layer 660 is defined, which is located at the interlayer dielectric layer 64. The predetermined position of the surface corresponding to the metal layer 620 is generally used to define the scope of another layer of metal interconnects or interstitial windows. The top view is as shown in Figure 6B, which includes the ring metal layer 620 in the lower layer and the light in the upper layer.阻 层 660。 Resistance layer 660. Please refer to Figure 6C. After the above structure is completed, overlap measurement after development is needed, that is, overlap measurement of the photoresist layer 66 and the metal layer 62 to check the deviation of the upper and lower layers. To 4 (: As shown in the figure, for the ring-shaped flattened metal layer 620 formed by the etching or chemical mechanical polishing process, its outline is not only flat, but also its thickness is shallow, generally less than 5000A, and its contrast is not obvious. Therefore, when the optical lens or imaging software is not sharp enough, it is often difficult to focus the image of the lower ring metal layer 620 (shown by the dotted line), and errors occur. In contrast, please refer to Figures 7A to 7D , Which shows a second embodiment of the present invention. It forms a concave opaque layer 720 with step height on the inlaid metal interconnect structure to perform an overlay measurement step on the upper and lower layers. First, according to FIG. 7A, It is a partial cross-sectional view of a manufacturing process of a mosaic metal interconnect. It provides a silicon substrate 7000 'formed with a lower metal interconnect or a semiconductor element such as a semiconductor element such as a transistor or a capacitor. Process Formation-ILD (not shown) is isolated from it, followed by the inlay metal interconnect structure process to define the interlayer window pattern and metal interconnect pattern, and engraving steps on the substrate 700 A via (not shown) and a ring-shaped interconnecting line are formed on the surface. 13 This paper size is applicable to the Chinese National Standard (CNS). Λ4 is now dead (210X297 times p ----_--- attack ----- -:-Order one: ----- 噃 (Please read the precautions before filling this page first) 412819 V. Description of the Invention (I2) The groove 780, so that the subsequent planarization layer has sufficient steps Height, the depth of the etchable interconnect trenches 780 is about 20KA, so the width of the interconnect trenches 780 can be made larger than that of the annular metal interconnects to be deposited in the case where the trench width is relatively small. The thickness is twice to avoid the deposited metal layer from sealing the trench 780. In sequence, please refer to FIG. 7B, and compliantly deposit an opaque layer such as polycrystalline silicon or metal layer 710 to cover the substrate. The width of the trench 780 is greater than about twice the thickness of the annular metal layer, so a recessed opening 790 is formed. FIG. 7C, the ring-shaped metal layer 710 is planarized by etching or chemical mechanic polishing (CMP) to form a concave ring-shaped metal layer 720 having a step height. Finally, please refer to FIG. 7D and form another Inner metal dielectric layer (IMD) 740, and implement planarization steps, such as etching or chemical mechanical polishing (CMP: chemical mechanical polishing). Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, printed by the consumer cooperative (please read the precautions on the back first) (Fill in this page) Then, through the exposure lithography process, a patterned photoresist layer 760 'is defined. It is located at a predetermined position on the surface of the interlayer dielectric layer 740 corresponding to the concave annular metal layer 720, and is generally used to define another layer of metal. The area of the connection or interlayer window is shown in FIG. 7E in the upper view, and includes a concave ring-shaped metal layer 720 on the lower layer and a photoresist layer 760 on the upper layer. Please refer to FIG. 7F. After the above structure is completed, a post-development overlap measurement step is required, that is, the photoresist layer 760 and the concave ring metal layer 720 are overlapped to measure the deviation of the upper and lower layers. For example, the concave annular metal layer 720 has a step height of 20KA, which forms the standard of this paper. It is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 male welding). Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 7 V. Description of the invention (13) The sharp image contrast is obviously conducive to overlapping the upper and lower layers of the optical lens of the measuring machine to capture the upper and lower layers of the image. In addition, the alignment points are doubled, including B1 ~ B8, etc. The probability of images of the upper and lower layers, that is, the concave annular planarized metal layer 720 and the photoresist layer 760. See also FIGS. 8A to 8C, which show a third embodiment of the present invention. It forms a concave ring-shaped opaque layer 820 with step height on the inlaid metal interconnect structure to perform overlapping measurement steps on the upper and lower layers. According to FIG. 8A, which corresponds to FIG. 7D, it includes a silicon substrate 800, and a ring-shaped interconnect line trench 880 is formed on the surface of the substrate 800 to expose the surface of the underlying metal interconnect portion. Step height, the depth of the etchable interconnect trenches 880 is about 20KA, and then an opaque layer such as polycrystalline silicon or metal layer 710 is compliantly deposited to cover the substrate and interconnect trenches 880. Here, The metal layer is taken as an example, and the ring-shaped metal layer is planarized by an etching or chemical mechanical polishing (CMP) process to form a concave ring-shaped metal layer 820 having a step height. Finally, an inner metal dielectric layer (IMD) 840 is formed, and a planarization step such as etching or chemical mechanical polishing (CMP) is performed. Then, a patterned photoresist layer 860 is defined by the exposure lithography process, which is located at a predetermined position on the surface of the interlayer dielectric layer 840 corresponding to the concave ring-shaped metal layer 820. Its top view is shown in FIG. 8B, including the concave type of the lower layer. The annular metal layer 820 and the upper photoresist layer 860. When the interconnect line trench 880 has a considerable width, if its width is greater than twice the thickness of the inner metal dielectric layer 840, the concave annular metal layer 820 15 This paper is applicable to the Chinese National Standard (CNS) Λ4 Regulations (2H) X297 is good) --------- Λ ------- IT -------- 't (#Read the precautions on the back before filling this page) 412819 a,
__IP 五、發明説明（14) 之圖案會使後續沈積之内金屬介電層（IMD)840具有遞延 性，而形成一局部凹陷之圖案。 因此，清參閱第8C圖，在進行重叠量測之對準步 驟時，由於本實施例之凹型環狀金屬層82〇具有2〇κ人 之步階高度，加以内金屬介電層（IMD)84〇形成之局部凹 陷圖案，形成敏銳之影像對比，明顯有利於重疊量測機 台之光學鏡頭抓取上下層之影像，此外對準點加倍，包 括B1〜B8等八處，更提昇光學鏡頭抓住上下層，亦即凹 型環狀平坦化金屬層820和光阻層860影像之機率。 本發明中應用之物質材料，並不限於實施例所引述 者’其能由各種具恰當特性之物質和形成方法所置換， 且本發明之結構空間亦不限於實施例引用之尺寸大小， 例如上述實施例，雖以多層内連線結構為例，然而，在 任何經平坦化之不透光層均有其適用，例如動態隨機存 取記憶體之複晶矽層或氮化矽層等。 經濟部中失標準局貝工消费合作社印裝 雖然本發明已以一較佳實施例揭露如下，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明 之精神和範圍内，當可做些許之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。 本紙張尺度適用中國固家榡準（CNS)以現柏（2ΙΟχ297 ί>^ )__IP V. Description of the Invention (14) The pattern of the invention (14) will make the subsequently deposited inner metal dielectric layer (IMD) 840 have a ductility and form a partially recessed pattern. Therefore, referring to FIG. 8C, when performing the alignment step of the overlap measurement, since the concave annular metal layer 820 of this embodiment has a step height of 20 κ, an internal metal dielectric layer (IMD) is added. The local depression pattern formed by 84 ° forms a sharp image contrast, which is obviously conducive to overlapping the optical lens of the measuring machine to capture the upper and lower layers of the image. In addition, the alignment points are doubled, including eight places such as B1 ~ B8, which improves the optical lens capture The probability of capturing the upper and lower layers, that is, the concave ring-shaped flattened metal layer 820 and the photoresist layer 860. The material materials used in the present invention are not limited to those cited in the examples, which can be replaced by various materials and forming methods with appropriate characteristics, and the structural space of the present invention is not limited to the dimensions cited in the examples, such as the above. In the embodiment, although a multilayer interconnection structure is taken as an example, it can be applied to any planarized opaque layer, such as a polycrystalline silicon layer or a silicon nitride layer of a dynamic random access memory. Printed by Shelley Consumers Cooperative of the Bureau of Loss of Standards of the Ministry of Economic Affairs Although the present invention has been disclosed as a preferred embodiment as follows, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention As some changes and retouching can be done, the scope of protection of the present invention shall be determined by the scope of the attached patent application. This paper size is applicable to China Gujiazheng Standard (CNS) to Xianbai (2ΙΟχ297 ί > ^)