TW408425B - Shallow trench isolation process - Google Patents

Abstract

A kind of shallow trench isolation process is practiced on the semiconductor substrate (such as silicon substrate). In this kind of process, firstly, utilizing the traditional method to form a shallow trench isolation (silicon dioxide) on the semiconductor substrate, the portion next to the substrate of the semiconductor is slightly depressed. Then, using HF as the etching solution to proceed etching toward the pre-formed shallow trench isolation in order to enlarge the pre-formed depressed portion. Then, utilize the cap layer (silicon nitride) to fill up the above-mentioned depressed portion, to make the phenomena of encroachment of the depressed portion to acquire the pre-formed cap layer isolation. Besides, the gate patterning step could be performed before enlarging the depressed portion in the etching shallow trench isolation, the sidewall of the gate could be formed at the same time.

Description

_408485___ V. Description of the invention (1) The present invention relates to an isolation process, and in particular to a shallow trench isolation process (STI process), which can 'finish narrower boundary contacts without adding process steps' Border-less contact process, and effectively avoid metal intrusion between semiconductor substrate and shallow trench isolation (Encroachment). Please refer to Figures 1A to 1D. This is the flow chart of the conventional shallow trench isolation process. First, as shown in FIG. 1A, a semiconductor substrate 10 (such as a silicon substrate) is provided, and an oxide layer 12 is formed on a surface thereof by a thermal oxidation method. Next, as shown in FIG. 1β, the semiconductor substrate 10 and the oxide layer 12 are dry-etched to define an isolation trench 14 to be isolated. Then, as shown in FIG. Ic, another oxide layer 16 is chemically vapor-deposited to cover the semiconductor substrate 10 and the isolation trench 12 formed by etching. Finally, as shown in FIG. D, the oxide layer 16 is etched back by chemical mechanical polishing to expose the surface of the semiconductor substrate 10, thereby completing the entire shallow trench isolation process. In this example, due to the limitation of the covering ability, the portion of the semiconductor substrate 20 at the junction with the shallow trench isolation 16 is slightly recessed, as shown in the figure. In addition, since the definition step of dry etching will cause interstitial defects at the junction between the isolation trench 14 and the semiconductor substrate 10 (especially at the sidewall of the isolation trench 4), when the source / drain region (see the figure) During the ion implantation and metal silicide process on the surface, the metal silicide (such as CoS ”deposited on the source / drain surface will invade along the semiconductor substrate 10 and the shallow trench isolation 16 interface. In addition, since the shallow trench isolation 16 side may invade the metal, when the metal connection is made, the contact window and contact plug to connect the source / drain region must also be connected to the shallow trench. 16 Guaranteed

1. · B. Page 4 V. Description of the invention (2) Maintain proper spacing. In view of this separation process, V is an acceptable phenomenon. V The present invention can achieve a more polar contact window without affecting the original v The present invention can reduce the normal movement of the entire circuitv The present invention can be deposited on the semiconductor to complete the gate sidewall in order to achieve the above process First, the conductor substrate is adjacent to the etching solution, and the depression is selected. In this shallow success. Shallow trenches are used to avoid the need of the present invention to avoid semiconducting, another purpose, narrow boundary contact and normal contact plug circuits, and another purpose of body circuits. A further purpose is to form the transistor gate substrate and the shallow channel. The other purpose is to erode the performance of the neodymium in the semiconductor part. The main purpose is to provide a metal trench between the shallow trench foundation and the shallow trench isolation. It is to provide a shallow trench isolation process. The contact process is that the source / drain to be connected can partially contact the shallow trench isolation, and action. Is to provide a shallow trench isolation process, the required chip area, without affecting the original is to provide a shallow trench isolation process, after the nitrided (or other isolation materials) nitride gap between the enlarged recesses, At the same time, the present invention provides a shallow trench isolation formed on a shallow trench isolation substrate, which is separated from a semi-depression; and then, 'the shallow trench isolation using hydrofluoric acid (HF) is used to expand the previously formed shielding layer, In the trench isolation process to avoid metal intrusion, the semiconductor substrate can be made of silicon and can be made of silicon dioxide. Formation of shallow trench isolation in this shallow trench isolation process

~~ -4684 ^ 5 ---- V. Description of the invention (3) In the step release system, an isolation window is first etched on the semiconductor substrate; then, a dielectric layer (such as silicon dioxide) is deposited to cover the previous one. The isolation window is formed, and the dielectric layer is etched back to expose the surface of the semiconductor substrate. Furthermore, in this shallow trench isolation process, the selective etch step of shallow trench isolation can use hydrofluoric acid (HF) as an etching solution. The shielding layer (silicon nitride) can shield the intrusion of metal in the recessed part. In addition, the present invention also provides a shallow trench isolation process. First, a shallow trench isolation is formed on a semiconductor substrate, and a portion adjacent to the semiconductor substrate is slightly recessed. Then, a gate is defined on the semiconductor substrate; then, reused Hydrofluoric acid (HF) is an etching solution that selectively etches shallow trench isolation to expand the previously formed depressions and form a shielding layer in the depressions to avoid metal intrusion. In this trench isolation process, the step of defining the gate is to first deposit a gate oxide layer (such as silicon dioxide) and a dielectric layer on the semiconductor substrate; and then 're-etch the defined dielectric layer to expose the gate to be formed. Then, a conductive layer (such as a compound crystal; s) is deposited to fill the area, and the dielectric layer is removed to obtain the desired gate electrode. In order to make the above and other objects, features, and advantages of the present invention more comprehensible ', a preferred embodiment is given below, and in conjunction with the accompanying drawings, a detailed description is as follows:

Figures 1A to 1D are flowcharts of a conventional shallow trench process; Figures 2A to 2F are flowcharts of a shallow trench process according to an embodiment of the present invention; and

_____ 408425 V. Description of the invention (4) Figures 3A to 3H are flow charts of a shallow trench process according to another embodiment of the present invention. Carry out you | To solve the above problem, the present invention uses hydrofluoric acid etching to expand the recessed portion of the semiconductor substrate and the shallow trench isolation interface, and deposit silicon nitride to fill the recessed portion, thereby enhancing the isolation effect between the two and Avoid leakage current and malfunction due to metal intrusion between the two. Please refer to Figs. 2A-2F ', which is a flowchart of a shallow trench manufacturing process according to an embodiment of the present invention. As shown in FIG. 2A, a semiconductor substrate 20 (such as a broken substrate) is first provided, and its surface is covered with an oxide layer 22 (such as a silicon dioxide layer) by a thermal oxidation method. However, as shown in FIG. 2B, the dry etching oxide layer 22 and the semiconductor substrate 20 are used to obtain an isolation window 24 for forming shallow trench isolation. In k = steps, the process of dry type remaining can be any conventional technique. After I1 ', as shown in FIG. 2C, a dielectric layer 26 (such as a silicon dioxide layer) is deposited to cover the oxide layer 22 and the isolation window 24. In addition, the deposition layer 22 is etched back to expose the surface of the semiconductor substrate 2G, thereby forming shallow trenches' as shown in FIG. 2D. In this step, the deposition is too light and can be performed by any of the conventional techniques. 26 relay limit, the semiconductor substrate 20 is isolated from the shallow trench. The P-point is slightly recessed 'as shown in Figure 2 & For example, the contact process in the field of knowledge is difficult: it is an invasion phenomenon, and the narrower side is achieved. Therefore, the present invention hopes to fill a shielding material between the semiconductor substrate 20 and the shallow trench isolation 26.

Page 7 —-40 ^ 4½ V. Description of the invention (5) However, it is difficult to perform the filling operation of the shielding material because 'the range of the recessed portion 28a is small'. Therefore, the present invention is further selectively etched to expand the range of the recessed portion 28a to the recessed portion 28b shown in FIG. 2E. In this step, the selective etching step may be isotropic wet etching, which uses hydrofluoric acid (HF) as the coin etching solution. In this way, a shielding material (such as silicon nitride) can be deposited, thereby filling the enlarged recessed portion 28b ', and thereby strengthening the metal intrusion between the semiconductor substrate 20 and the shallow trench isolation 26 and the leakage current phenomenon, such as The filling material 30 shown in FIG. 2F. In addition, 'the insulation effect of the shallow trench isolation 26 can be improved', the contact process with a narrower boundary is also completed, that is, the contact window and contact plug of the source / drain region (not shown) to be connected may be partially Cover the shallow trench isolation 26 without affecting the normal operation of the original circuit. In addition, please refer to FIGS. 3A to 3H, which is a flowchart of a shallow Zhugou process according to another embodiment of the present invention. In this example, the formation of the transistor gate wall side and the filling of the shallow trench isolation side shielding material are performed in the same step. As shown in FIG. 3A, a semiconductor substrate 40 (such as a silicon substrate) is first provided, and its surface is covered with an oxide layer 42 (such as a silicon dioxide layer) by a thermal oxidation method. Then, as shown in FIG. 3B, in the process of forming shallow trench isolations 42a and 42b, the formation steps of trench isolations 42a and 42b can be restated. In addition, the semiconductor substrate 40 is also slightly recessed, as shown in FIG. 3B. The position of the transistor is conventionally determined on the substrate 40. The shallow trenches are the same as in the previous embodiment, so they are no longer separated from the shallow trenches by the recesses 44a, 44b shown at the junctions 42a, 42b.

___ 4 ^ 8425 ------- V. Description of the invention (6) After the trench isolation 42a, 42b is formed, a gate electrode 52 is formed on the semiconductor substrate 40. The steps for forming the gate electrode 52 are as follows. First, a gate oxide layer 46 (such as a di-emulsion layer) and a dielectric layer such as a photoresist layer are sequentially deposited on the semiconductor substrate 40, as shown in FIG. 3C. Then, the dielectric layer 48 is engraved to obtain a window 50 for forming a gate, as shown in FIG. 3D. A conductive material 52 (such as polycrystalline silicon) is filled into the window 50, as shown in FIG. 3E. Next, after removing the dielectric layer 48 and the gate oxide layer 46 which are not covered with the conductive material, 'the desired gate electrode $ 2 is obtained, as shown in Fig. 3 jp. The trench isolations 42 a and 42 b ′ extend the range of the recesses 44 a and 44 b to the recesses 44 a and 44 b shown in FIG. 3G. In this step, the selective etching step may be isotropic wet etching, which uses hydrofluoric acid (HF) as an etching solution. In this way, a 'shielding material (such as silicon nitride) can be deposited to fill in the enlarged depressions 44a, 44b' and the side wall 56 forming the gate electrode 52, as shown in Fig. 3H. In this embodiment, either the deposition or etching steps can be performed using conventional techniques. In summary, the shallow trench isolation process of the present invention can avoid the metal intrusion phenomenon between the semiconductor substrate and the shallow trench isolation, and achieve a narrower boundary, the contact process, that is, the contact of the source / drain region to be connected The window and the contact plug can be partially contacted with the shallow trench isolation without affecting the normal operation of the original power.

V. Description of the invention (7) The wafer area of the present invention. In addition, after the electrode, the nitrided trench is separated and expanded between the substrate and the shallow trench. Although the present invention limits the scope of the present invention, and within the scope, the attached application The shallow trench isolation process can also reduce the overall circuit requirements without affecting the normal operation of the original circuit. The invented shallow trench isolation process can be used to define transistor gate silicon (or other isolation materials) deposited on the semiconductor substrate and shallow depressions, and at the same time complete the shielding between the gate sidewalls and the semiconductor isolation. The Ming has disclosed the above with a preferred embodiment, but it is not intended to be used by any person skilled in the art. Changes and retouching can be made without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention shall be defined by the patent scope.

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Claims (1)

40842 & 6. Application for patent scope 1. A shallow trench isolation process, comprising: providing a semiconductor substrate; forming a shallow trench isolation from the semiconductor substrate, the surface of the semiconductor substrate is slightly recessed at a portion adjacent to the shallow trench isolation; Selectively etching the shallow trench isolation to enlarge the recessed portion; and forming a shielding layer to fill the recessed portion. 2. The shallow trench isolation process described in item 1 of the scope of patent application, wherein the semiconductor substrate is composed of a semiconductor substrate. 3. The shallow trench isolation process described in item 1 of the scope of patent application, wherein the shallow trench isolation is composed of silicon dioxide. 4. The shallow trench isolation process described in item 1 of the scope of the patent application, wherein the formation steps of the shallow trench isolation are: etching an isolation window on the semiconductor substrate; depositing a dielectric layer to cover the An isolation window; and etching back the dielectric layer to expose the surface of the semiconductor substrate. 5. The shallow trench isolation process described in item 1 of the scope of patent application, wherein the selective etching step of the shallow trench isolation uses hydrofluoric acid (HF) as an etching solution. 6. The shallow trench isolation process as described in item 1 of the patent application scope, wherein the shielding layer is used to shield the surface of the semiconductor substrate from metal intrusion in a recessed portion adjacent to the shallow trench isolation. 7. The shallow trench isolation process as described in item 6 of the scope of patent application, wherein the shielding layer is composed of a nitride stone. 8. — A shallow trench isolation process, including: Page 11 40842 ^ 6. The scope of the patent application provides a semiconductor substrate; a shallow trench is isolated from the semiconductor substrate, and the wide surface of the semiconductor substrate is slightly recessed at a portion adjacent to the shallow trench isolation; _ defines a gate electrode for the semiconductor On the substrate; selectively etching the shallow trench isolation to enlarge the depression; and forming a shielding layer to fill the four depressions. 9. In the shallow trench isolation system described in item 8 of the patent application scope, the semiconductor substrate is composed of Shi Xi. 10. In the shallow trench isolation system described in item 8 of the patent application, the shallow trench isolation is composed of dioxide. 8. In the shallow trench isolation process described in item 8 of the scope of the patent application, in which the shallow trench isolation is formed by: etching an isolation window on the semiconductor substrate; depositing a dielectric layer to cover the An isolation window; and truncating the dielectric layer to expose the surface of the semiconductor substrate. 12. According to the shallow trench isolation process described in item 8 of the scope of the patent application, the gate is defined by: depositing a gate oxide layer on the semiconductor substrate; depositing a dielectric layer on the gate oxide layer Up; defining the dielectric layer to expose the area where the gate is to be formed; depositing a conductive layer to fill the area; and removing the dielectric layer to obtain the gate. 1 3. The shallow trench isolation process as described in item 12 of the scope of patent application, 4Q8425 6. Scope of patent application, wherein the dielectric layer is composed of a photoresist layer. 1 4. The shallow trench isolation process according to item 6 of the scope of patent application, wherein the conductive layer is composed of polycrystalline silicon. 1 5. The shallow trench isolation process as described in item 8 of the scope of patent application, wherein the selective etching step of the shallow trench isolation uses hydrofluoric acid (H F) as an etching solution. 16. The shallow trench isolation process according to item 8 of the scope of the patent application, wherein the shielding layer is used to shield the surface of the semiconductor substrate from metal intrusion in a recessed portion adjacent to the shallow trench isolation. 1 7. The shallow trench isolation process according to item 8 of the scope of the patent application, wherein the shielding layer is composed of a nitride stone. Page 13