TW398074B - Mask ROM with low mask number and its manufacturing - Google Patents

Abstract

This invention aims to perform a whole-region ion doping in the PMOS region, NMOS region, and NMOS memory cell region. A gate structure in the substrate is then formed. A large angle of the second ion doping is also performed to form p type punchthrough resistant region in the substrate. A third ion doping and impurities doping transfer the p type LDD region of the NMOS region and the p type punchthrough resistant region to n type LDD region. The sidewall spacer is then formed on the gate structure. A fourth ion doping will assist the formation of the drain region and the source region in the NMOS region and NMOS memory cell region. The next step is to form the drain and source regions in the PMOS region. Finally, a high-temperature annealing procedure in N2, O2 and N2O environments activates the ions and forms the shallow junction facet.

Description

A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention () The invention of the invention: This invention is related to a semiconductor process, especially a memory element. mask read only memory; mask ROM) process. Background of the Invention: As new application fields and the future drive the continuous development of memory elements, a large number of memory elements are required in the computer and communication related industries. For example, the interface of computers will develop in the area of audio and video control in the future. The above control interface will require a large number of Memory element. In order to obtain a high-performance integrated circuit and increase the package density of the wafers', in the ultra-large integrated circuit (ULSI) technology, the size of semiconductor elements has been continuously reduced. Generally (the mask read-only memory has two different threshold voltages in the memory element array. The first kind of element is brought into the -active. Area, and the ™ element has different starting voltages. 1 It is formed in another active region. For example, the first element is a general element and has a starting voltage vti, and the second element has a starting voltage vt2, where the starting voltage VU and the starting voltage described above Vt2 is different. Therefore, a photomask is needed for ion implantation to achieve different starting voltages during the second process. This method involves adding a high dose of butterfly ions to the transistor to improve 'Starting voltage' is generally called threshold voltage programming ° This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back page first) • Installation, 1T1 I-V. Description of the invention (A7 B7 In the traditional process, the above-mentioned different starting voltages can be achieved without the additional number of masks. Please refer to US Patent No. 5,506,438 proposed by Hsue. The process can reach different starting voltages. They are field oxide programming and through hole programming. The above-mentioned various programming methods are implanted at different stages during the manufacturing process. Details The mechanism can be found in semiconductor devices, Chapter 10, page 507-5 12 "Author by Betty Prince, published by John Wiley. Field oxidation programming uses different gate oxide thicknesses to achieve different starting voltages during production The third type of through-hole programming is to selectively open contact holes in contact with the memory cell to achieve different starting voltages. The traditional method requires an additional process to define the code (coding). For example, the use of ion doping to penetrate a sacrificial oxide layer or a compound stone layer. The above-mentioned process is time-consuming and ion implantation can reduce the characteristics of the gate polarization layer and the complex-crystal layer. Please read the notes

Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economics Purpose and Summary of the Invention: The purpose of the present invention is to provide a systematic process. A kind of mask read-only memory with a low light army number. A thick-field oxide region (f0x) is produced on a predetermined area by thermal oxidation.

·, A7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs _______ B7 V. Invention Description (). An oxide layer is formed by oxidation in an oxygen environment. After forming the above oxide layer, a polycrystalline silicon layer is deposited on the oxide layer by a chemical vapor deposition method. The lithography process is used to etch the above-mentioned oxide layer and the polycrystalline silicon layer to form a idle structure on the PMOS region, the NMOS region, and the NMOS memory cell region. A comprehensive p-type ion is then implanted to implant the ions into the PMOS region, NMOS region, and NMOS memory cell region described above to form a lightly doped drain (LDD) region next to the idler structure. In this embodiment, a slight amount of ions is preferably doped, and the doped impurities may be B F 2 or rotten. The ion implantation dose is about 1E12 to 1E14 atoms / cm2, and the energy of this step is about 5 to 100 KeV. Next, a second ion doping is performed at a large angle to form a P-type anti-abutment region on the substrate. The dose of ion implantation is about 5E11 to 5E13 at oms / cm2, and the energy of ion implantation is about 10 to 15 KeV ′, and the angle of implantation corresponds to about 12 to 60 degrees to the surface of the substrate. Using a photoresist as a mask power, a third ion doping is performed to implant impurities to convert the p-type LDD region and p-type anti-punch-through region in the NMOS region into n-type L D D regions. Then, the photoresist is removed. A sidewall gap is formed above the gate structure. A photoresist is then formed on the PMOS region, and a fourth ion doping is performed on the exposed portion. In a preferred embodiment, an n-type ion such as hafnium or phosphorus is doped to facilitate the formation of its drain and The source region is in the NMOS region and the NMOS memory cell region. The NMOS memory cell region has a p-type conductive ion offset structure below the sidewall gap. This paper size applies to China National Standard (CNS) A4 (210X297 mm)

(Please read the precautions on the back H • Installation ^ — — This page) Order-line · A7 B7 V. Description of the invention () The offset structure has a higher resistance 値 'Dose and ion implantation in this step The implantation energy is 5E14 to 5E16 atoms / cm2, 0.1 to 80 KeV. Then remove the photoresist. The next step is to form the drain and source regions in the PMOS region. Finally, a high-temperature thermal tempering process is performed in the environment of 0, 2 and N20 to activate the ions to form a shallow junction. The temperature of this step is about 850 to 11001 :. -B—Jian Jun's explanation: The contents of the present invention and the many advantages of the invention can be easily understood by the following detailed description combined with the attached drawings, where: The first figure is a cross-sectional view of a semiconductor wafer, showing the basis The present invention performs a first ion doping step in a semiconductor substrate. The second figure is a cross-sectional view of a semiconductor wafer, showing a step of performing a second ion doping in accordance with the present invention. The third figure is a cross-sectional view of a semiconductor wafer, showing a third step of performing ion doping according to the present invention. The fourth figure is a cross-sectional view of a semi-conductor wafer, showing a step of forming a side wall gap on a side wall of a gate structure according to the present invention. The fifth figure is a cross-sectional view of a semiconductor wafer, showing a fourth step of performing ion doping according to the present invention. The sixth figure is a cross-sectional view of a semiconductor wafer, showing a step of performing a fifth ion implantation according to the present invention. The seventh figure is a cross-sectional view of a semiconductor wafer, showing the steps of a heat treatment according to the present invention.

A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (Figure 8 shows the current-voltage curve of a general NMOS device in the invention. -Voltage curve. Detailed description of the invention: The present invention provides a new method for manufacturing a mask read-only memory on a semiconductor substrate. In a preferred embodiment, a < 1 00 > crystal orientation is provided. The single-crystal silicon substrate 2 is divided into three main parts: PMOS region 210, NMOS region 220, and NMOS memory cell region 230. NMOS memory cell region 2 3 0 is used to program data such as 1. Or 〇. Then, a thick field oxide region (FOX) 4 is formed on a predetermined region by using a thermal oxidation method. Generally, an oxide layer and a silicon nitride layer are used as an oxidation mask, and in a vapor environment, The thermal oxidation can be performed in the middle to form an F OX region 4 'with a thickness of about 3000 to 8000 angstroms, as shown in the first figure. After the thermal oxidation and η f are used, the above oxidation masks can be separated respectively. Removal. A gate structure can be made by a known process It is formed on the substrate 2. First, an oxide layer 6 is oxidized and formed in an oxygen environment at a temperature of about 800 to 100 ° C, and secondly, a chemical vapor deposition method using teoS as a reactant at a temperature of 600 can be used. The above-mentioned oxide layer 6 is formed between 800 ° C and 800 ° C, and the process pressure is about 0 to 10 Torr. In this embodiment, the thickness of the oxide layer 6 is about 15 to 200 angstroms. After the above-mentioned oxide layer 6 is formed, A polycrystalline silicon layer 8 is deposited on the oxide layer 6 by chemical vapor deposition. The lithography process is used to etch the above-mentioned t-paper scale towards the family Guan Guanpi (CNS) A4 ^ (21Qx297)-(Please read first Note on the back write this page)-bite,-line_ A7

The oxide layer 6 and the polycrystalline silicon layer 8 can form the gate structure described above on the PM 0S region 210, the NMOS region 220, and the NMOS memory cell region 230. Subsequently, a comprehensive p-type ion doping is performed to implant ions into the PMOS region 210, NMOS region 220, and NMOS memory cell region 230 described above, and a lightly doped drain (LDD) region 10 is formed next to the gate structure. In this embodiment, it is preferable to dope a small amount of ions. The doped impurity may be BF2 or boron. The ion implantation dose is about 1E12 to 1E14 atoms / cm2, and the energy of this step is about 5 to 100 KeV. Next, referring to the second figure, a second ion doping is performed at a large angle to form a p-type anti-breakdown region 12 in the substrate 2 and surround the Ldd region 10 described above. The dose of ion implantation is about 5E11 to 5E13 at 0ms / cm2, and the energy of ion implantation is about 10 to 150 KeV, and its implantation, s corresponding to the surface of substrate 2 is about 12 to 60 degrees. Referring to the third figure, a photoresist pattern 14 is formed on the substrate 2 to expose the NMOS region 220. Using the above photoresistance μ & ^ -mask, a third ion doping is performed on the exposed lacking part, and the commanded male is implanted into the substrate to p-type LDD region 10 in NMOS region 220. The "blood" agent 1, ', and P distorted the anti-impedance region 12 into the n-type LDD region 16. For example, the ion dust drag "quoted the impurity of the cone", the dose and ion implantation in this step can Eight "m fresh slicing knife is 5 Ε 1 2 $ 5E14 atoms / cm2, 5 to 120 KeV. Then, remove the photoresist pattern 14 above as shown in Figure 7 of the wide hanging crane + soil. As shown in the fourth figure, use a Chemical vapor deposition also forms an oxide layer on 7 A7 _______B7 V. Description of the invention () The gate structure. The above-mentioned oxide layer is etched using a non-isotropic etching process to make a sidewall gap 1 8 on the gate structure Above.

(Please read the precautions on the back first. Order a photoresist pattern 20 and then form it on the PMOS area 210, as shown in the fifth figure. Use the above photoresist pattern 20 as a mask power to the exposed part. A fourth ion doping is performed, and in a preferred embodiment, an n-type ion such as hafnium or phosphorus is doped to facilitate the formation of its drain and source regions 22 in the N M 0 S region 2 2 0 and N M 0 S memory cell region 2 3 0. It must be noted that the NMOS memory cell region 230 has a p-type conductive ion offset structure 24 below the sidewall gap 18. This offset structure 24 Has a higher resistance, so after this step, the initial voltage of the NM 0 S memory cell region 2 30 will be higher than the initial voltage of the ν M 0 S region 2 2 0. The dose and ion implantation in this step The input energy is 5 Ε 1 4 to 5 Ε16 atoms / cm2, 0.1 to 80 KeV. Then the above photoresist pattern 20 is removed. -Line · 员工 Printed by the Consumers' Cooperative of the Central Standards Bureau, Ministry of Economic Affairs, the next step is to form The pole and source regions 26 are in the PM0S region 210, and the fifth ion doping implantation can be performed. The ions are in the PM0S region 2 1 0. The dose of ion implantation is about 5E14 to 5E16 atoms / cm2, and the energy of ion implantation is about 0_1 to 80 KeV. For the structure diagram of this step, please refer to Figure 6. In this step, a photoresist pattern 28 is introduced to be formed on the NMOS region 220 and the NMOS memory cell region 230. Therefore, the photoresist pattern 28 will be removed after the implantation is completed. In one embodiment, BF2 is used as a doping agent. Miscellaneous ions The size of this paper is applicable to China National Standard (CNS) 8-4 specification (210X297 mm) A7 ___ B7 V. Description of the invention () A high temperature thermal tempering procedure is performed in the environment of N2, 02 & N20 to activate The ions form a shallow junction. The temperature of this step is about 850 to 1 100, which is shown in the seventh figure. The eighth figure shows the current-voltage line of a general NMOS device in the present invention. The ninth figure is the present invention The current-voltage curve of the NMOS S memory cell in the middle-mask read-only memory. From the figure, the starting voltage of the general NMOS device is about 0.68V. 3 5 V. The advantages of the present invention are (1) the use of the present invention does not need to increase the number of hoods. Different starting voltages can be obtained. (2) The present invention can save at least two photomask-related steps when compared with the general quasi-CMOS process. Although the present invention is illustrated above with a preferred example, it is not intended to be limited. The spirit of the present invention and the entity of the invention are limited to this embodiment. The modifications made by those skilled in the art without departing from the spirit and scope of the present invention should be included in the patent application park described below. 9 This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297mm).

Claims (1)

AS B8 C8 Soil D8 too ... 6. Application for Patent Scope Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 1. A method for manufacturing mask read-only memory (mask ROM) on a semiconductor substrate, the semiconductor substrate The method includes a PMOS region, an NMOS region, and an N M 0 S memory cell region formed therein. The method includes at least the following steps: forming a gate structure in the P M 0 S region, the N M 0 S region, and the v M ◦ S memory Performing a first ion doping to form a p-type lightly doped drain adjacent to the gate structure; performing a second ion doping and tilting an implantation angle to form a p-type anti-breakdown region; υ Forming a first photoresist pattern to expose the NM 0 S region; ν performing a third ion doping with the first photoresist pattern to form a η 4η micro-doped drain adjacent to the NMOS region The gate structure; removing the photoresist pattern; forming a side wall gap on the side wall of the gate structure; forming a second photoresist pattern to cover the PMOS area; using the second photoresist pattern as a mask to perform the first step Quaternary ion doping Forming an n-type drain and source electrode in the NMOS region and t in the NMOS memory cell region to remove the second photoresist pattern; forming a third photoresist pattern to expose the PMOS region; using the third photoresist pattern as a mask The curtain performs the fifth ion doping to form a p-type drain and source in the PMOS region; removes the third photoresist pattern; and this paper uses the Chinese National Standard (CNS) A4 specification (210X297 cm) ) -------- # ¾ ------ 1T ------ 9 (Please read the precautions on the back before filling this page) 々, apply a heat treatment to the patent scope to activate the blend Miscellaneous ions. 2. The method of claim 1 in the scope of patent application, wherein the first-time ion-doped ions include BF2. 3. The method according to item 1 of the scope of patent application, wherein the dose of the first ion doping is about 1E12 to 1E14 atoms / cm2. 4. The method according to item 1 of the patent application range, wherein the energy of the first ion doping is about 5 to 100 KeV. 5. The method according to item 1 of the scope of patent application, wherein the ions doped with the second ions mentioned above include phosphorus. 6. The method according to item 1 of the patent application range, wherein the dose of the second ion doping is about 5E11 to 5E13 atoms / cm2. 7. The method according to item 1 of the patent application park, wherein the energy of the above-mentioned second ion doping is approximately 10 to 150 KeV. Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives (please read the precautions on the back before filling in this card) 8. If you apply for the method in the first scope of the patent application, where the above-mentioned second ion doping implantation angle The surface corresponding to the semiconductor substrate is approximately 12 to 60 degrees. 9. For the method of applying for the first item of the patent scope, in which the third ion mentioned above applies to the Chinese National Standard (CNS) A4 specification (210X297 mm). 々 The scope of the patent application The doped ion contains phosphorus. 10. The method according to item 1 of the scope of the patent application, wherein the dose of the third ion doping is about 5E12 to 5E14 atoms / cm2. 1 1. The method according to item 1 of the patent application range, wherein the energy of the third ion doping described above is approximately 5 to 120 KeV. 1 2. The method according to item 1 of the scope of patent application, wherein the ions doped for the fourth time include arsenic. 13. The method according to item 1 of the scope of patent application, wherein the dose of the fourth ion doping is about 5E14 to 5E16 atoms / cm2. 14. The method according to item 1 of the scope of patent application, wherein the energy of the fourth ion doping described above is about 0.1 to 80 KeV. 15. The method according to item 1 of the scope of patent application, wherein the fifth ion-doped ion described above comprises BF2. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 16. For the method of applying for the first item of the patent scope, the dose of the fifth ion doping mentioned above is approximately 5E14 to 5E16 atoms / cm2. 1 7. The method according to item 1 of the scope of patent application, wherein the energy of the fifth ion doping described above is approximately 0.1 to 80 KeV. This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Λ8 B8 C8 D8 6. Application for patent scope 1 8 · If the method of applying for patent scope item 1 The thermal tempering procedure described above for recovering the etching defects is performed in an N 2 0 environment. 19. The method according to item 1 of the patent application park, wherein the thermal tempering procedure used to restore the etching defect is performed in a 02 environment. 20 · The method according to item 1 of the scope of patent application, wherein the above heat treatment is activated in an N2 environment. 2 1. The method according to item 1 of the scope of patent application, wherein the above-mentioned heat treatment is activated in a 02 environment. 2 2. The method according to item 1 of the scope of patent application, wherein the above heat treatment is activated in a N20 environment. 23 · The method according to item 1 of the patent application park, wherein the above-mentioned heat treatment temperature is about 850 to 110 ° C. 24. The method of claim 1 in the scope of patent application, wherein the above-mentioned sidewall gap is formed by silicon oxide. 13 This paper size applies Chinese National Standard (CNS) A4 specification (2 丨 〇 × 297 mm) (Please read the precautions on the back before filling this page)