TW396574B - A method for fabricating T-type plug to increase contact area - Google Patents

A method for fabricating T-type plug to increase contact area Download PDF

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Publication number
TW396574B
TW396574B TW87121318A TW87121318A TW396574B TW 396574 B TW396574 B TW 396574B TW 87121318 A TW87121318 A TW 87121318A TW 87121318 A TW87121318 A TW 87121318A TW 396574 B TW396574 B TW 396574B
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Taiwan
Prior art keywords
plug
layer
insulating layer
forming
scope
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TW87121318A
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Chinese (zh)
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Ching-Fu Lin
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Taiwan Semiconductor Mfg
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Abstract

A method for fabricating T-type plug on semiconductor substrate comprises the following steps: form the first dielectric layer on a substrate and the second dielectric layer above the first dielectric layer, and define the second dielectric layer and the first dielectric layer to form a contact opening and bare the substrate. Thereafter strip the dielectric layer surrounding the contact opening, deposit a conformal barrier metal layer on the second dielectric layer and in contact opening, and deposit the first conductive layer in said barrier metal layer and conduct opening. After the first conductive layer and said barrier metal layer above the second dielectric layer is removed, the residual of the first conductive layer is the plug therefore.

Description

4099twf.doc/006 A7 B7 五、發明説明(/ ) 本發明是有關於一種半導體製程’且特別是有關於一 種提高接觸窗插塞或介層窗插塞的接觸面積之方法。 苟半導體製程中,插塞常用以連接導電層,例如金屬 和離子摻雜層,第1圖至第3圖係繪示習知一種製造插塞 的剖面流程圖,請參照第1圖,於基底100上形成一層絕 緣層102,蝕刻絕緣層102以形成接觸窗開口(Contact 〇pening)104,於絕緣層102上與接觸窗開口 104中形成一 層共形的阻障金屬層(Barrier metal layer) 106,於阻障金屬 層106上與接觸窗開口 104中形成一層第一導電層108。 請參照第2圖,進行化學機械硏磨(Chemical Mechanical Polish ; CMP),去除絕緣層102上之部份第一導電層108 與部份阻障金屬層(Barrier metal layer)106,使部份第一導 電層108留在接觸窗開口 104中,形成插塞110。 請參照第3圖,於絕緣層102和插塞110上形成一層 第二導電層,使用傳統之微影蝕刻步驟,以絕緣層102爲 蝕刻終止層,去除部份第二導電層,使插塞110上形成導 電結構112,如第3圖所示,插塞110和導電結構U2並 非完全相互接觸,此種不理想的結果通常是因爲導電結構 112與插塞110沒有完全對準,或導電結構112與插塞11〇 之尺寸無法相互配合。 因此需要有改良的製程以製造出接觸面積比習知高的 之插塞。 ' 提出一種半導體基底上形成T形插塞之方法,包括下 列步驟:於基底上形成一層第〜絕緣層,於第一絕緣層上 夺4099twf.doc / 006 A7 B7 V. Description of the Invention (/) The present invention relates to a semiconductor process' and, in particular, to a method for increasing the contact area of a contact window plug or a via of an interlayer window. In the semiconductor manufacturing process, plugs are often used to connect conductive layers, such as metal and ion-doped layers. Figures 1 to 3 show a conventional cross-sectional flow chart for manufacturing plugs. Please refer to Figure 1 on the substrate. An insulating layer 102 is formed on 100, the insulating layer 102 is etched to form a contact window opening 104, and a conformal barrier metal layer 106 is formed on the insulating layer 102 and the contact window opening 104 A first conductive layer 108 is formed on the barrier metal layer 106 and the contact window opening 104. Referring to FIG. 2, chemical mechanical polishing (CMP) is performed to remove part of the first conductive layer 108 and part of the barrier metal layer 106 on the insulating layer 102 so that part of the first conductive layer 108 and the barrier metal layer 106 are removed. A conductive layer 108 is left in the contact window opening 104 to form a plug 110. Referring to FIG. 3, a second conductive layer is formed on the insulating layer 102 and the plug 110. Using the conventional lithographic etching step, the insulating layer 102 is used as an etching stop layer, and a part of the second conductive layer is removed to make the plug A conductive structure 112 is formed on 110. As shown in FIG. 3, the plug 110 and the conductive structure U2 are not completely in contact with each other. This undesirable result is usually caused by the conductive structure 112 and the plug 110 not being completely aligned, or the conductive structure. The size of 112 and plug 11 cannot match each other. Therefore, there is a need for improved processes to produce plugs with higher contact areas than conventional. '' A method for forming a T-shaped plug on a semiconductor substrate is proposed, which includes the following steps: forming a first ~ insulating layer on the substrate, and

I •Ιί % 本 1 裝 訂 線 本紙认尺度进川、丨· 象標彳(CNS ) Λ4規林(210X297公漦) 4099twf.doc/006 A7 B7 五、發明説明(〕) 形成一層第二絕緣層’定義第二絕緣層與第一絕緣層以形 成一接觸窗開口,暴露出基底,去除於接觸窗開口周圍之 部份第絕緣層,於第二絕緣層上與接觸窗開口中形成一 層共形之阻障金屬層,於阻障金屬層與接觸窗開口中形成 一層第一導電層’去除第二絕緣層上之部份第一導電層與 部份阻障金屬層,所餘留之部份第一導電層即爲插塞。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳 細說明如下: 圖式之簡單說明: 第1圖至第3圖係繪示習知一種製造插塞的剖面流程 圖;以及 第4圖至第7圖係繪示依照本舅製造插塞的 剖面流程圖。 圖式之標記說明: 基底:100、120 絕緣層:102 接觸窗開口 : 104、126 阻障金屬層:106、127 第一導電層:108、128 插塞:110、128a 導電結構:112、130 絕緣層:122 第二絕緣層:124 r 本紙认尺度试川屮:榡彳((,NS ) Λ4规招(210X297公釐) ---------裝------訂----„——丨線 . - (誚先閱讀背而之注意事項再硪寫本頁) 4099twf.doc/006 A 7 B7 五、發明説明(彡) 實施例 請參照第4圖,其繪示一半導體基底120,基底120 可能包I括半導體晶圓’晶圓中的主動區與被動區,晶圓上 的.膜層。亦即,基底包括形成於半導體晶圓中的元件與晶 圓上的膜層。 如第四圖所示,於基底120上形成一層第一絕緣層 122,第一絕緣層可以由氧化矽、磷矽玻璃(BPSG)、四乙 氧基矽甲烷(TEOS)、摻雜氟氧化物或任何相關之材質所形 成。於第一絕緣層122上形成一層第二絕緣層124,第二 絕緣層124之材質可以由氮化矽(SiNx)、氮氧化矽 (SixOYNz)、旋塗式玻璃(SOG)、碳矽化合物或低介電係數 材質所形成,厚度約100-2000 A。以第二絕緣層124當作 罩幕層,基底120則爲蝕刻終止層,進行傳統之微影蝕刻 步驟,形成接觸窗開口 126。 請參照第5圖,去除於接觸窗開口 126周圍之部份第 二絕緣層124,例如使用乾蝕刻、濕蝕刻或間隙壁製程, 第二絕緣層124與第一絕緣層122具有高蝕刻選擇率,第 二絕緣層124比第一絕緣層122更容易被蝕刻去除,第二 絕緣層124沿水平方向大約被蝕刻去除100-800 A,於第 二絕緣層124上與接觸窗開口 126中形成一層共形之阻障 金屬層(Barder metal layer)127,阻障金屬層127之材質例 如爲鈦(Ti)、氮化鈦(TixNY)、鉬(Ta)、化鎢(TixWY)或氮 化鎢(WXNY) ’厚度約100-2000 A。於阻障金屬層127與接 觸窗開口 126中形成一層第一導電層128,第一導電層128 6 ^纸张_Uli川ϋ W *栉々(CNS ) Λ4規梢(210父297公漤) 一 — ---------¾-----—ΪΤ-------.^ - - (对先閱讀背而之注意事^^填寫本頁) 4099twf_doc/006 A7 B7 五、發明説明(γ) 之材質例如爲鎢(W)、銅(Cu)或鋁(A1)。 請參照第6圖,使用化學機械硏磨(CMP)或其他傳統 方法考除第二絕緣層124上之部份第一導電層128與部份 阻障金屬層127,所餘留之導電層即爲插塞128a,如第6 圖所示,插塞128a之接觸面積藉回蝕刻或第二絕緣層124 的凹陷而提高。 請參照第7圖,於第二絕緣層124、阻障金屬層127 和插塞128a上形成一層第二導電層,使用傳統之微影蝕 刻法去除部份第二導電層,使得插塞128a上形成一導電 結構130。 增加插塞128a之接觸面積得以使導電結構130與插塞 128a完全接觸。除此之外,增加插塞128a上層部位之寬 度可以減低鎖洞問題(Keyhole problem),而如果第一絕緣 層122爲含有氟離子之材質,則第二絕緣層124可以防止 或降低氟離子之擴散。並且,於去除阻障金屬層127和第 一導電層128(第5圖,第6圖)之過程中,第二絕緣層124 可當作終止層。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍內,當可作各種之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 先 閱 讀 背 意 事 項 再 者 裝 訂 線 ^度诚川屮 ('NS ) Λ4说招(210X 297公釐)I • Ιί% Book 1 Glyph of the paper Recognition standard into Sichuan, 丨 · Icon Standard 彳 (CNS) Λ4 gauge Lin (210X297 public 漦) 4099twf.doc / 006 A7 B7 V. Description of the invention ()) Form a second insulating layer 'Define the second insulating layer and the first insulating layer to form a contact window opening, expose the substrate, remove a portion of the first insulating layer around the contact window opening, and form a conformation with the contact window opening on the second insulating layer. Barrier metal layer, forming a first conductive layer in the barrier metal layer and the opening of the contact window 'to remove part of the first conductive layer and part of the barrier metal layer on the second insulating layer, and the remaining part The first conductive layer is a plug. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 Figures 3 to 3 are cross-sectional flowcharts of a conventional method for manufacturing a plug; and Figures 4 to 7 are cross-sectional flowcharts of a method for manufacturing a plug according to the present invention. Description of drawing symbols: Base: 100, 120 Insulation layer: 102 Contact window opening: 104, 126 Barrier metal layer: 106, 127 First conductive layer: 108, 128 Plug: 110, 128a Conductive structure: 112, 130 Insulation layer: 122 Second insulation layer: 124 r Paper recognition standard test Chuanxiong: 榡 彳 ((, NS) 44 regulations (210X297 mm) --------- install -------- order ---- „—— Line.-(诮 Please read the precautions before writing this page) 4099twf.doc / 006 A 7 B7 V. Description of the Invention (彡) Please refer to Figure 4 for examples. A semiconductor substrate 120 is shown. The substrate 120 may include an active region and a passive region in a semiconductor wafer, and a film layer on the wafer. That is, the substrate includes components and crystals formed in the semiconductor wafer. As shown in the fourth figure, a first insulating layer 122 is formed on the substrate 120. The first insulating layer may be made of silicon oxide, phosphosilicate glass (BPSG), and tetraethoxysilylmethane (TEOS). , Doped with fluorine oxide or any related material. A second insulating layer 124 is formed on the first insulating layer 122, and the material of the second insulating layer 124 may be It is made of silicon nitride (SiNx), silicon oxynitride (SixOYNz), spin-on-glass (SOG), carbon-silicon compound, or low-dielectric constant material, with a thickness of about 100-2000 A. The second insulating layer 124 is As the cover layer, the base 120 is an etching stop layer, and the conventional lithographic etching step is performed to form the contact window opening 126. Please refer to FIG. 5 to remove a portion of the second insulating layer 124 around the contact window opening 126, for example, Using dry etching, wet etching, or a spacer process, the second insulating layer 124 and the first insulating layer 122 have a high etching selectivity. The second insulating layer 124 is easier to be removed by etching than the first insulating layer 122, and the second insulating layer 124 Approximately 100-800 A is removed by etching in the horizontal direction, and a conformal Barder metal layer 127 is formed on the second insulating layer 124 and the contact window opening 126. The material of the barrier metal layer 127 is, for example, Titanium (Ti), titanium nitride (TixNY), molybdenum (Ta), tungsten nitride (TixWY), or tungsten nitride (WXNY) 'thickness is about 100-2000 A. It is formed in the barrier metal layer 127 and the contact window opening 126 One layer of the first conductive layer 128, the first conductive layer 128 6 ^ 纸 _Uli 川 ϋ W * CN (CNS) Λ4 gauge (210 fathers and 297 males) One ----------- ¾ ------- ΪΤ -------. ^-- Note: ^^ Fill in this page) 4099twf_doc / 006 A7 B7 5. Description of the invention (γ) The material is, for example, tungsten (W), copper (Cu) or aluminum (A1). Please refer to FIG. 6, using chemical mechanical honing (CMP) or other traditional methods to remove part of the first conductive layer 128 and part of the barrier metal layer 127 on the second insulating layer 124. The remaining conductive layer is For the plug 128a, as shown in FIG. 6, the contact area of the plug 128a is increased by etching back or the depression of the second insulating layer 124. Referring to FIG. 7, a second conductive layer is formed on the second insulating layer 124, the barrier metal layer 127 and the plug 128a, and a portion of the second conductive layer is removed using a conventional lithographic etching method, so that the plug 128a is formed on the plug 128a. A conductive structure 130 is formed. Increasing the contact area of the plug 128a allows the conductive structure 130 to fully contact the plug 128a. In addition, increasing the width of the upper part of the plug 128a can reduce the keyhole problem, and if the first insulating layer 122 is made of a material containing fluorine ions, the second insulating layer 124 can prevent or reduce the fluoride ion diffusion. In addition, during the process of removing the barrier metal layer 127 and the first conductive layer 128 (FIG. 5 and FIG. 6), the second insulating layer 124 can be used as a termination layer. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. Read the memorandum first and then the gutter. ^ Ducheng Chuanxiong ('NS) Λ4 said (210X 297 mm)

Claims (1)

396574 4099twf.doc/006 __ D8 _ 六、申請專利範圍 1. 一種於半導體基底上形成插塞的方法,該方法包括: 於該基底上形成一第一絕緣層; 於該第一絕緣層上形成一第二絕緣層; 定義該第二絕緣層與該第一絕緣層’形成一接觸窗 開口,暴露出該基底; 去除於該接觸窗開口周圍之部份該第二絕緣層; 於該第二絕緣層上與該接觸窗開口中形成一共形之 阻障金屬層; 於該阻障金屬層與該接觸窗開口中形成一第一導電 層;以及 去除該第二絕緣層上之部份該第一導電層與部份該 阻障金屬層,所餘留之部份該第一導電層即爲一插塞。 2. 如申請專利範圍第1項所述之半導體基底上形成插 塞的方法,其中該第一絕緣層之材質包括氧化矽、磷矽玻 璃、四乙氧基矽甲烷,相關之材質其中之一。 3. 如申請專利範圍第1項所述之半導體基底上形成插 塞的方法,其中該第二絕緣:層之林質包括氮化矽、氮氧化 石夕、旋塗式玻璃或碳砍.化合物其中之一..。 經濟部中央標準局男工消費合作社印製 (請先W讀背面之注項寫本頁) 4. 如申請專利範圍第1項所述之半導體基底上形成插 塞的方法,其中該第二絕緣層之厚度約100-2000 A左右。 5. 如申請專利範圍第1項所述之半導體基底上形成插 塞的方法,其中被去除之部份該第二絕緣層寬約100-800 A 〇 6. 如申請專利範圍第1項所述之半導體基底上形成插 % 本紙張尺度適用中國國家揉準(CNS ) A4規格(210X297公釐) S96574 A8 B8 4099twf.doc/006 C8 D8 六、申請專利範圍 塞的方法,其中該阻障金屬層之材質包括鈦、氮化鈦、鉬、 鈦化鎢和氮化鎢。 7. 如申請專利範圍第1項g述之半導體基底上形成插 塞的方法,其中該阻障金屬層厚度約100-2000 A。 8. 如申請專利範圍第1項所述之半導體碁遽上形成插 塞的方法,其中該第一導電層之材質包括鎢、銅和鋁。 9. 如申請專利範圍第1項所述之半導體基;1上形成插 _塞的方法,其中該方法更包括下列步驟: 於該第二絕緣層、該阻障金屬層和該插塞上形成一第 '二導電層;以及 去除部分該第二導電層,使得該插塞上形成由部份該 第二導電層所構成的一導電結構。 ---------^------L1T----------^ " (請先聞讀背面之注意事項^填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS > A4说格(210X297公釐)396574 4099twf.doc / 006 __ D8 _ 6. Scope of Patent Application 1. A method for forming a plug on a semiconductor substrate, the method comprising: forming a first insulating layer on the substrate; forming on the first insulating layer A second insulating layer; defining the second insulating layer and the first insulating layer to form a contact window opening, exposing the substrate; removing a portion of the second insulating layer around the contact window opening; on the second Forming a conformal barrier metal layer on the insulating layer and the contact window opening; forming a first conductive layer on the barrier metal layer and the contact window opening; and removing a portion of the first insulating layer on the second insulating layer. A conductive layer and part of the barrier metal layer, and the remaining part of the first conductive layer is a plug. 2. The method for forming a plug on a semiconductor substrate as described in item 1 of the scope of the patent application, wherein the material of the first insulating layer includes silicon oxide, phosphosilicate glass, tetraethoxysilylmethane, one of the related materials . 3. The method for forming a plug on a semiconductor substrate as described in item 1 of the scope of the patent application, wherein the forest material of the second insulation: layer includes silicon nitride, oxynitride, spin-on glass or carbon chopping. one of them... Printed by the Men ’s Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the note on the back to write this page) 4. The method for forming a plug on a semiconductor substrate as described in item 1 of the scope of patent application, wherein the second insulation The thickness of the layer is about 100-2000 A. 5. The method for forming a plug on a semiconductor substrate as described in item 1 of the scope of the patent application, wherein the removed portion of the second insulation layer is about 100-800 A in width. Insertion% on semiconductor substrate This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) S96574 A8 B8 4099twf.doc / 006 C8 D8 6. Method for applying patent scope plug, where the barrier metal layer Materials include titanium, titanium nitride, molybdenum, tungsten titanide, and tungsten nitride. 7. The method for forming a plug on a semiconductor substrate as described in item 1g of the scope of patent application, wherein the thickness of the barrier metal layer is about 100-2000 A. 8. The method for forming a plug on a semiconductor wafer as described in item 1 of the patent application scope, wherein the material of the first conductive layer includes tungsten, copper, and aluminum. 9. The method for forming a plug on a semiconductor substrate according to item 1 of the scope of patent application, wherein the method further includes the following steps: forming on the second insulating layer, the barrier metal layer and the plug; A second conductive layer; and removing a portion of the second conductive layer, so that a conductive structure composed of a portion of the second conductive layer is formed on the plug. --------- ^ ------ L1T ---------- ^ " (Please read the notes on the back first ^ Fill in this page) Staff of Central Bureau of Standards, Ministry of Economic Affairs The paper size printed by the consumer cooperative is applicable to the Chinese national standard (CNS > A4 scale (210X297 mm)
TW87121318A 1998-12-21 1998-12-21 A method for fabricating T-type plug to increase contact area TW396574B (en)

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