322622 1 S0 8TWF.DOC/Frank/005 A7 B7 經濟部中央樣準局貝工消費合作社印裝 五、發明説明（I ) 本發明是有關於一種積體電路元件的製造方法，且特 別是有關於一種動態隨機存取記憶體的製造方法。 動態隨機存取記憶體是一種廣泛使用的積體電路元 件，尤其在今日資訊電子產業中更佔有不可或缺的地位。 事實上動態隨機存取記憶體的記憶單元是由一個轉移電晶 體與一個電容器所構成的，第1圖是顯示習知一個動態隨 機存取記憶體記憶單元的正視剖面圖，提供一基底10，在 基底10上包括閘極區11，且在閘極區11側壁有間隙壁12、 源極/汲極區13、場氧化層14 *以及一位元線15，位元線 15與源極/汲極區13相藕接。在上述元件表面形成有一絕緣 層16,例如是氧化矽層。在絕緣層16中有複數個接觸窗17， 且在接觸窗17中形成插塞(Plug)18，插塞18與源極/汲極區 13相藕接。且在插塞18表面還有一複晶矽層19作爲電容 之下電極，以及在複晶矽層19與絕緣層16表面形成一半球 狀晶粒之複晶砂層(Hemispherical Grain)20。在上述習知的 動態隨機存取記憶體中，需利用微影與蝕刻將形成在絕緣 層16表面之半球狀晶粒之複晶矽層20去除，以得到單獨之 電容。由於在目前元件線寬愈來愈小的趨勢下，複晶矽層 19之間的距離也愈來愈小，以及曝光寬度的極限，造成元 件縮小不易。 因此，提出另一種動態隨機存取記憶體之結構，第參 照第2A-2D圖爲習知另一種動態隨機存取記憶體的製造方 法，首先請參照第2A圖，提供一基底21，在基底21上已 形成有閘極區22、源極/汲極區23、場氧化層24、間隙壁 3 ,I. I 裝 訂 7"線 - < {請先閲東背面之注意事項再填寫本買) 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） 1808TWF.DOC/Frank/00 5 A7 ________B7_ 五、發明説明（>* ) (請先閲讀背面之注意事項再填寫本頁) 25、以及位元線26。在上述元件表面形成一絕緣層27氮 化矽層28，並定義氮化矽層的圖案形成複數個開口 29，露 出絕緣層27，開口 29位於源極/汲極區23上方。 接著，請參照第2B圖，在氮化矽層28表面形成一氧化 層30 ’例如是以電漿化學氣相沈積法形成之二氧化矽層。 再定義氧化層30的圖案，蝕刻去除氧化層30，同時經由開 口 29將絕緣層27去除，露出源極/汲極區23形成介層窗31 » 接著’在氧化層30表面與介層窗31表面形成一高雜質濃度 之複晶矽層32，作爲電容之下電極，以及在高雜質濃度之 複晶矽層32表面形成一半球狀晶粒之複晶矽層33。 之後請參照第2C圖，以化學機械硏磨法去除半球狀晶 粒之複晶矽層33與高雜質濃度之複晶矽層32，並以氧化層 3〇爲終止層。 最後，請參照第2D圖，以濕蝕刻去除氧化層30，接 著’在表面形成一氧化層/氮化層/氧化層34，例如是TiN 和Ta2〇5。最後在氧化層/氮化層/氧化層34表面形成一複晶 砂層35，作爲電容之上電極。 上述動態隨機存取記億體之製造方法中，在進行化學 機械硏磨法去除半球狀晶粒之複晶矽層33與高雜質濃度之 複晶矽層32時，會有硏漿(Sluiry)殘留，造成在半球狀晶粒 之複晶矽層33表面受到污染，使元件效能降低。 因此本發明的主要目的就是在提供一種動態隨機存取 6己憶體的製造方法，利用一介電層保護半球狀晶粒之複晶 矽層表面，不受化學機械硏磨法產生硏漿之污染。 張尺度相中gj时鄉（C A4胁（2獻297公董） 經濟部中央標準局員工消費合作社印製 322622 1 8〇8TWF. DOC/Frank/005 A 7 ___;______B7_ 五、發明説明（3 ) 本發明的另一目的就是在提供一種動態隨機存取記憶 體的製造方法，可利用化學機械硏磨法與回蝕刻法去^半 球狀晶粒之複晶矽層與高雜質濃度之複晶矽層。 本發明的又一目的就是在提供一種動態隨機存取記憶 體的製造方法，可同時去除氧化層與介電層，不需增加步 驟。 本發明的再一目的就是在提供一種動態隨機存取記憶 體的製造方法，其半球狀晶粒之複晶矽層的去除，不受元 件縮小以及曝光極限的限制。 本;發明一種動態隨機存取記憶體的製造方法，包括下 列步驟： (a) 提供一基底，其上形成有至少一金氧半元件，包括 一閘極、一間隙壁、一源極/汲極區以及一場氧化層； (b) 在表面形成一絕緣層，並定義該絕緣層的圖案，形 成一第一開口，露出部分該源極/汲極區； (c) 在上述各層表面依序形成一第一高雜質之複晶矽層 與一矽化鎢層，並使該第一高雜質之複晶矽層與該矽化鎢 層塡滿該第一開口； (d) 同時定義該第一高雜質之複晶矽層與該矽化鎢層之 圖案’形成一位兀線，且該位兀線經由該第一開口與該源 極/汲極區藕接； (e) 在該絕緣層與該位元線表面依序形成一第一氧化層 與一第一介電層，並經熱流使該第一介電層表面平坦化： ⑴在該第一介電層表面形成一氮化矽層，並定義該氮 5 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） ----f I---人 1裝------訂-----丄银 *- (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 ^2622 A7 1 80 8TWF.DOC/Frank/00 5 A1 B7 五、發明説明（¥ ) 化矽層之圖案，形成複數個第二開口，露出該第一介電層； (g) 在該氮化矽層表面形成一第二氧化層，定義該第二 氧化層之圖案，同時經由該些第二開口去除該第一介電 層、該第一氧化層與該絕緣層，形成複數個介層窗，露出 該源極/汲極區； (h) 在上述露出之表面依序形成一第二高雜質濃度之複 晶矽層與半球狀晶粒之複晶矽層； ⑴在該半球狀晶粒之複晶矽層表面形成一第二介電 層，並使該第二介電層塡滿該些介層窗，且該第二介電層 之厚度超該第二氧化層之高度； (j) 去除該第二介電層、該半球狀晶粒之複晶矽層與該 第二高雜質濃度之複晶矽層，並以該第二氧化層爲終止 層；以及 (k) 以濕蝕刻去除該第二氧化層與該第二介電層，並以 該氮化矽層爲終止層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖是習知一種動態隨機存取記憶體之結構剖面 圖， 第2A-2D圖是習知另一種動態隨機存取記憶體的製造 方法剖面流程圖；以及 第3A-3F圖是依照本發明一較佳實施例，一種動態隨 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------丨裝------訂------ί级 • · (請先閲讀背面之注意事項再填寫本頁) 180 8TWF.DOC/Frank/00 5 A7 五、發明説明（f ) '~~'—" ' 機存取記憶體的製造方法剖面流程圖。 實施例 (請先閲讀背面之注意事項再填寫本頁) 第3A-3F圖是依照本發明一較佳實施例，—種動態隨 機存取記憶體的製造方法，首先請參照第3八圖，提供—基 底40，例如是一 P型矽基底，至少已形成一金氧半元件包 括：閘極區41、閘極區41兩側之間隙壁42、源極/汲極區 43以及場氧化層44。在基底40表面形成一絕緣層46，例 如是以低壓化學氣相沈積法形成並以四乙氧基矽甲院爲反 應氣體形成之二氧化矽層，其厚度約爲1500A，並經熱流處 理’其溫度約爲800 °C。接著定義絕緣層46的圖案，形成 一開口 47，經由開口 47露出部分源極/汲極區43。 之後請參照第3B圖，在上述各層表面依序形成一含雜 質之複晶矽層48與矽化鎢層49，並使複晶矽層48與砂化 鎢層49塡滿開口 47。同時定義複晶矽層48與矽化鎢層49 之圖案，形成位元線50，位元線50經由開口 47與源極/汲 極區43相連接。 經濟部中央標準局員工消費合作社印掣 接著，請參照第3C圖，在絕緣層46與位元線50表面 形成一氧化層52與一介電層53，氧化層52例如是以常壓 化學氣相沈積法形成之二氧化砂層，而介電層53例如是硼 磷矽玻璃。再經由熱流使介電層53表面平坦化。然後在介 電層53表面形成一氮化矽層54，之後定義氮化矽層54的 圖案，形成複數個開口 55，露出介電層53 ’開口 55位於 源極/汲極區43上方。 之後，請參照第3D圖’在氮化矽層54表面形成一氧 7_ 本紙張尺度適用中國國家標準（CNS ) A4規格（21 〇 X 297公釐） 經濟部中央標準局員工消費合作社印裝 1808TWF.DOC/Frank/005 Λ/ _____B7_ 五、發明説明（t ) 化層57，例如是以電漿化學氣相沈積法形成之二氧化矽 層。再定義氧化層57的圖案，蝕刻去除氧化層57，同時經 由開口 55將介電層53、氧化層52以及絕緣層46去除，露 出源極/汲極區43形成介層窗58。接著，在氧化層57表面 與介層窗58表面形成一高雜質濃度之複晶矽層59，作爲電 容之下電極，以及在高雜質濃度之複晶矽層59表面形成一 半球狀晶粒之複晶矽層60。 接著，請參照第3E圖，在半球狀晶粒之複晶矽層59 表面形成一介電層61，例如是硼磷矽玻璃，並使介電層61 塡入介層窗58,且介電層61的厚度超過氧化層57的高度。 再以回蝕刻或化學機械硏磨法去除介電層61、半球狀晶粒 之複晶矽層59與高雜質濃度之複晶矽層58，並以氧化層57 爲終止層。 最後，請參照第3F圖，以濕蝕刻去除氧化層57與介電 層61，例如使用20:1之緩衝氧化蝕刻液（BOE)，並以氮化 矽層爲蝕刻終止層。隨後在表面形成一氧化層/氮化層/氧化 層62，例如是TiN和Ta2〇5。最後在氧化層/氮化層/氧化層 62表面形成一電導體層63，例如是複晶矽層，作爲電容之 上電極，後續製程與習知相同在此不多贅述。 利用本發明一較佳實施例之動態隨機存取記憶體，具 有下列優點： 1.利用介電層61形成在半球狀晶粒之複晶矽層59表 面，可保護半球狀晶粒之複晶矽層59不會因習知利用化學 機械硏磨法而造成泥漿殘留。 8 本紙張尺度適用中國國家標準（CNS ) Α4规格（210X2.97公釐） I-----------1 裝------訂------ί 線 (請先閲讀背面之灰意事項再填寫本頁) 322622 1808TWF.DOC/Frank/005 A7 B7 五、發明説明（7) 2. 介電層61的去除和氧化層57可同時以濕蝕刻去除， 不需增加製程步驟。 3. 可適用於積集度愈來愈大的元件製程上’改進習知唯 讀記憶體製程中因元件間距過近，而無法使用微影與蝕刻 定義半球狀晶粒之複晶矽層。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 11.!_---JU..丨裝------訂------{練 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作杜印製 本紙張尺度適用中國國家榡率（CNS ) A4規格（2丨〇><297公釐）322622 1 S0 8TWF.DOC / Frank / 005 A7 B7 Printed by the Central Sample Bureau of the Ministry of Economic Affairs, Beigong Consumer Cooperative V. Description of the invention (I) The present invention relates to a method for manufacturing integrated circuit components, and in particular A manufacturing method of dynamic random access memory. Dynamic random access memory is a widely used integrated circuit element, especially in today's information and electronics industry. In fact, the memory unit of the dynamic random access memory is composed of a transfer transistor and a capacitor. Figure 1 is a front sectional view showing a conventional dynamic random access memory memory unit, providing a substrate 10, A gate region 11 is included on the substrate 10, and a spacer 12, a source / drain region 13, a field oxide layer 14 *, and a bit line 15 are formed on the side wall of the gate region 11, and the bit line 15 and the source / The drain pole 13 is connected in phase. An insulating layer 16, such as a silicon oxide layer, is formed on the surface of the element. There are a plurality of contact windows 17 in the insulating layer 16, and plugs 18 are formed in the contact windows 17, and the plugs 18 are coupled to the source / drain regions 13. In addition, a polycrystalline silicon layer 19 is further formed on the surface of the plug 18 as a lower electrode of the capacitor, and a semi-spherical grain layer (Hemispherical Grain) 20 is formed on the surfaces of the polycrystalline silicon layer 19 and the insulating layer 16. In the conventional dynamic random access memory mentioned above, the polycrystalline silicon layer 20 of hemispherical crystal grains formed on the surface of the insulating layer 16 needs to be removed by lithography and etching to obtain a separate capacitor. In the current trend of smaller and smaller device line widths, the distance between the polysilicon layers 19 is also getting smaller and smaller, and the limit of the exposure width makes it difficult to shrink the device. Therefore, another structure of a dynamic random access memory is proposed. Refer to FIGS. 2A-2D to learn another method for manufacturing a dynamic random access memory. First, please refer to FIG. 2A to provide a substrate 21 on which The gate region 22, source / drain region 23, field oxide layer 24, spacer 3, I. I binding 7 " line- < {please read the precautions on the back of the east before filling in this purchase ) This paper scale is applicable to the Chinese national standard (CNS > A4 specification (210X297mm) 1808TWF.DOC / Frank / 00 5 A7 ________B7_ V. Invention description (> *) (Please read the precautions on the back before filling this page ) 25, and bit line 26. An insulating layer 27 is formed on the surface of the device, a silicon nitride layer 28 is formed, and a pattern of the silicon nitride layer is defined to form a plurality of openings 29 to expose the insulating layer 27, the openings 29 are located at the source / drain Above the polar region 23. Next, referring to FIG. 2B, an oxide layer 30 'is formed on the surface of the silicon nitride layer 28, for example, a silicon dioxide layer formed by plasma chemical vapor deposition. The pattern of the oxide layer 30 is further defined , The oxide layer 30 is etched away, while the The edge layer 27 is removed to expose the source / drain region 23 to form a via 31. Then, a polysilicon layer 32 with a high impurity concentration is formed on the surface of the oxide layer 30 and the via 31 to serve as a capacitor lower electrode. And forming a semi-spherical crystal polycrystalline silicon layer 33 on the surface of the high-impurity polycrystalline silicon layer 32. After that, please refer to FIG. 2C to remove the semi-spherical crystal polycrystalline silicon layer 33 and chemical mechanical polishing A polysilicon layer 32 with a high impurity concentration, and the oxide layer 30 is used as a stop layer. Finally, please refer to FIG. 2D, the oxide layer 30 is removed by wet etching, and then an oxide layer / nitride layer / oxidation is formed on the surface The layer 34 is, for example, TiN and Ta205. Finally, a polycrystalline sand layer 35 is formed on the surface of the oxide layer / nitride layer / oxide layer 34 as an upper electrode of the capacitor. In the above method for manufacturing a dynamic random access memory, When the chemical-mechanical polishing method is used to remove the polycrystalline silicon layer 33 of the hemispherical grains and the polycrystalline silicon layer 32 of high impurity concentration, there will be sludge remaining, resulting in the polycrystalline silicon layer of the hemispherical grains 33 The surface is contaminated, which reduces the efficiency of the device. Therefore, the main purpose of the present invention It is to provide a manufacturing method of dynamic random access 6 memory, using a dielectric layer to protect the surface of the polycrystalline silicon layer of hemispherical crystal grains, and not to be contaminated by the slurry produced by the chemical mechanical grinding method. gj Shixiang (C A4 threatened (2 dedicated 297 public directors) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 322622 1 8〇8TWF. DOC / Frank / 005 A 7 ___; ______ B7_ V. Description of the invention (3) Another object is to provide a method for manufacturing a dynamic random access memory, which can utilize chemical mechanical grinding and etch-back methods to remove the polycrystalline silicon layer of hemispherical grains and the polycrystalline silicon layer of high impurity concentration. Another object of the present invention is to provide a method for manufacturing a dynamic random access memory, which can simultaneously remove the oxide layer and the dielectric layer without additional steps. Another object of the present invention is to provide a method for manufacturing a dynamic random access memory, in which the removal of the polycrystalline silicon layer of hemispherical crystal grains is not limited by the shrinkage of components and the exposure limit. The present invention; a method for manufacturing a dynamic random access memory, including the following steps: (a) providing a substrate on which at least one metal oxide half element is formed, including a gate, a spacer, and a source / drain A polar region and a field oxide layer; (b) forming an insulating layer on the surface and defining the pattern of the insulating layer to form a first opening to expose part of the source / drain region; (c) sequentially on the surface of each layer Forming a first high impurity polycrystalline silicon layer and a tungsten silicide layer, and filling the first opening with the first high impurity polycrystalline silicon layer and the tungsten silicide layer; (d) defining the first high The polysilicon layer of impurities and the pattern of the tungsten silicide layer form a bit line, and the bit line is coupled to the source / drain region through the first opening; (e) in the insulating layer and the A first oxide layer and a first dielectric layer are sequentially formed on the surface of the bit line, and the surface of the first dielectric layer is planarized by heat flow: (1) A silicon nitride layer is formed on the surface of the first dielectric layer, And define the nitrogen 5 paper scale to use the Chinese National Standard (CNS) A4 specification (210X297 mm) ---- f I --- Person 1 Pack ------ Order ----- Silver Silver *-(Please read the precautions on the back before filling this page) Printed by Employee Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs ^ 2622 A7 1 80 8TWF.DOC / Frank / 00 5 A1 B7 5. Description of the invention (¥) The pattern of the silicon layer is formed to form a plurality of second openings, exposing the first dielectric layer; (g) forming a layer on the surface of the silicon nitride layer The second oxide layer defines the pattern of the second oxide layer, and at the same time removes the first dielectric layer, the first oxide layer and the insulating layer through the second openings to form a plurality of dielectric windows to expose the source electrode / Drain region; (h) Form a second high impurity concentration polycrystalline silicon layer and hemispherical crystal polycrystalline silicon layer on the exposed surface in sequence; (1) In the hemispherical crystal polycrystalline silicon layer A second dielectric layer is formed on the surface, and the second dielectric layer fills the dielectric windows, and the thickness of the second dielectric layer exceeds the height of the second oxide layer; (j) remove the second A dielectric layer, the polycrystalline silicon layer of the hemispherical crystal grains and the polycrystalline silicon layer of the second highest impurity concentration, and using the second oxide layer as a termination layer; and (k) wet etching Removing the second oxide layer and the second dielectric layer, and the silicon nitride layer is to stop. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in conjunction with the attached drawings, which are described in detail as follows: Brief description of the drawings: Figure 1 It is a cross-sectional view of a structure of a conventional dynamic random access memory. Figures 2A-2D are cross-sectional flowcharts of another method of manufacturing a dynamic random access memory; and Figures 3A-3F are a comparison according to the present invention. A preferred embodiment, a kind of dynamic with 6 paper scales is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) --------- 丨 installation ------ order ------ ί Level • (Please read the precautions on the back before filling in this page) 180 8TWF.DOC / Frank / 00 5 A7 5. Description of the invention (f) '~~' — " 'Section of manufacturing method of machine access memory section flow chart. Embodiment (please read the precautions on the back before filling in this page) Figures 3A-3F are according to a preferred embodiment of the present invention, a method for manufacturing a dynamic random access memory, first please refer to Figure 3, Provide a substrate 40, such as a P-type silicon substrate, at least one metal oxide semiconductor element has been formed including: a gate region 41, a spacer 42 on both sides of the gate region 41, a source / drain region 43, and a field oxide layer 44. An insulating layer 46 is formed on the surface of the substrate 40, for example, a silicon dioxide layer formed by a low-pressure chemical vapor deposition method and formed by using tetraethoxysilicone as a reaction gas, and has a thickness of about 1500A, and is subjected to heat flow treatment Its temperature is about 800 ° C. Next, the pattern of the insulating layer 46 is defined to form an opening 47 through which a portion of the source / drain region 43 is exposed. Then, referring to FIG. 3B, an impurity-containing polycrystalline silicon layer 48 and a tungsten silicide layer 49 are sequentially formed on the surfaces of the above layers, and the polycrystalline silicon layer 48 and the tungsten sand layer 49 are filled with openings 47. At the same time, the pattern of the polycrystalline silicon layer 48 and the tungsten silicide layer 49 is defined to form a bit line 50. The bit line 50 is connected to the source / drain region 43 via the opening 47. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Next, please refer to Figure 3C. An oxide layer 52 and a dielectric layer 53 are formed on the surface of the insulating layer 46 and the bit line 50. The sand layer formed by the phase deposition method, and the dielectric layer 53 is, for example, borophosphosilicate glass. The surface of the dielectric layer 53 is flattened by heat flow. Then, a silicon nitride layer 54 is formed on the surface of the dielectric layer 53, and then a pattern of the silicon nitride layer 54 is defined to form a plurality of openings 55 to expose the openings 55 of the dielectric layer 53 'above the source / drain regions 43. After that, please refer to the 3D picture 'Forming an oxygen 7 on the surface of the silicon nitride layer 54_ This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (21 〇X 297 mm) Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative 1808TWF .DOC / Frank / 005 Λ / _____B7_ 5. Description of the invention (t) The chemical layer 57 is, for example, a silicon dioxide layer formed by plasma chemical vapor deposition. The pattern of the oxide layer 57 is further defined, the oxide layer 57 is etched away, and the dielectric layer 53, the oxide layer 52 and the insulating layer 46 are removed through the opening 55, and the source / drain region 43 is exposed to form a via window 58. Next, a polysilicon layer 59 with a high impurity concentration is formed on the surface of the oxide layer 57 and the via window 58 as a lower electrode of the capacitor, and half-spherical grains are formed on the surface of the polysilicon layer 59 with a high impurity concentration Polycrystalline silicon layer 60. Next, referring to FIG. 3E, a dielectric layer 61, such as borophosphosilicate glass, is formed on the surface of the polycrystalline silicon layer 59 of the hemispherical grain, and the dielectric layer 61 is inserted into the dielectric window 58 and the dielectric The thickness of layer 61 exceeds the height of oxide layer 57. Then, the dielectric layer 61, the polycrystalline silicon layer 59 of hemispherical crystal grains and the polycrystalline silicon layer 58 with high impurity concentration are removed by etching back or chemical mechanical grinding, and the oxide layer 57 is used as a termination layer. Finally, referring to FIG. 3F, the oxide layer 57 and the dielectric layer 61 are removed by wet etching. For example, a 20: 1 buffer oxide etchant (BOE) is used, and the silicon nitride layer is used as an etching stop layer. Subsequently, an oxide layer / nitride layer / oxide layer 62, such as TiN and Ta205, is formed on the surface. Finally, an electrical conductor layer 63 is formed on the surface of the oxide layer / nitride layer / oxide layer 62, for example, a polycrystalline silicon layer, which is used as the upper electrode of the capacitor. The subsequent process is the same as the conventional one and will not be repeated here. Using the dynamic random access memory of a preferred embodiment of the present invention has the following advantages: 1. The dielectric layer 61 is formed on the surface of the polycrystalline silicon layer 59 of the hemispherical crystal grains, which can protect the polycrystal of the hemispherical crystal grains The silicon layer 59 will not cause mud residue due to the conventional chemical mechanical grinding method. 8 This paper scale is applicable to China National Standard (CNS) Α4 specification (210X2.97mm) I ----------- 1 Packing ------ order ------ ί line ( Please read the gray matters on the back before filling out this page) 322622 1808TWF.DOC / Frank / 005 A7 B7 5. Description of the invention (7) 2. The removal of the dielectric layer 61 and the oxide layer 57 can be simultaneously removed by wet etching, no Need to add process steps. 3. It can be applied to the device process with more and more accumulation degree. ”Improvement of the conventional read-only memory system. Because the device pitch is too close, lithography and etching cannot be used to define the polycrystalline silicon layer of hemispherical grains. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone who is familiar with this skill can make various modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. 11.! _--- JU .. 丨 installation ------ order ------ {practice (please read the precautions on the back and then fill in this page) Central Bureau of Standards, Ministry of Economic Affairs The size of the printed paper is applicable to the Chinese national rate (CNS) A4 specification (2 丨 〇 < 297mm)