415004 A7 87 δ9. 五、發明説明（1 ) ~—— 本發明是，在半導體基板上製造積體電路的方法 ’特別是有關於具有低介電質常數（k)之金屬間介電質 (IMD)層的形成方法’以減少半導體積體電路的多層佈線 請 先 閱 讀 背 之· 注 意 事_ 項 再 填 ί ί 頁 的RC時間延遲，這個方法特別適用於最小特徵尺寸 (fe咖e Size)小於0.25微米（um)特大型積體電路肌叫 間之交互連接。 訂 在半導體基板上製造特大型積體電路（ULSI)時需要 多層的金屬互相連接，藉以將諸如在半導體晶片上之場 效電晶體（FETs)和雙極電晶體等個別半導體元件予以連 接。習知的方法之中，大抵是以電漿輔助化學汽相沉積 法（PEC VD)形成氧化矽物（Si〇2)，設置於相鄰金屬線間和 不同金屬交連層間做為絕緣層，藉以交將此等金屬線予 以電性隔離，並對此等絕緣層蝕刻成通孔（via h〇le)，藉 以連接一金屬層至下一個金屬層。 經消部中央標準局員工消贽合作社印製 一般而言，氧化矽物具有相當高的介電質常數k(相 對於真空）’大約是4.1〜4·5。然而，若能減少rc時間常 數對電路性能必然會有所提昇，因此，必須能降低金屬 線的電阻R和金屬線間的電容C。當於元件尺寸縮減和 組裝密度增加的趨勢下，為能減少交連金屬線間的間隔 ’以有效地連接積體電路’則降低金屬線阻值R和金屬 線間電容C便顯得格外重要。然而，當金屬線間的間隔 減y時’因電谷C疋和接線間搞d成反比（c=ke〇A/d，其 中’ k是相對介電質常數’ e〇是真空的電容率 (permittivity)，A是面積’ d是在接線間的間距），故會 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210x 297公釐） 415004 A7 87 δ9. 五、發明説明（1 ) ~—— 本發明是，在半導體基板上製造積體電路的方法 ’特別是有關於具有低介電質常數（k)之金屬間介電質 (IMD)層的形成方法’以減少半導體積體電路的多層佈線 請 先 閱 讀 背 之· 注 意 事_ 項 再 填 ί ί 頁 的RC時間延遲，這個方法特別適用於最小特徵尺寸 (fe咖e Size)小於0.25微米（um)特大型積體電路肌叫 間之交互連接。 訂 在半導體基板上製造特大型積體電路（ULSI)時需要 多層的金屬互相連接，藉以將諸如在半導體晶片上之場 效電晶體（FETs)和雙極電晶體等個別半導體元件予以連 接。習知的方法之中，大抵是以電漿輔助化學汽相沉積 法（PEC VD)形成氧化矽物（Si〇2)，設置於相鄰金屬線間和 不同金屬交連層間做為絕緣層，藉以交將此等金屬線予 以電性隔離，並對此等絕緣層蝕刻成通孔（via h〇le)，藉 以連接一金屬層至下一個金屬層。 經消部中央標準局員工消贽合作社印製 一般而言，氧化矽物具有相當高的介電質常數k(相 對於真空）’大約是4.1〜4·5。然而，若能減少rc時間常 數對電路性能必然會有所提昇，因此，必須能降低金屬 線的電阻R和金屬線間的電容C。當於元件尺寸縮減和 組裝密度增加的趨勢下，為能減少交連金屬線間的間隔 ’以有效地連接積體電路’則降低金屬線阻值R和金屬 線間電容C便顯得格外重要。然而，當金屬線間的間隔 減y時’因電谷C疋和接線間搞d成反比（c=ke〇A/d，其 中’ k是相對介電質常數’ e〇是真空的電容率 (permittivity)，A是面積’ d是在接線間的間距），故會 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210x 297公釐） 415004 A7 ------- B7 五、發明説明（2 ) 增加電容C。 經濟部中央標準局員工消费合作社印31 • - ^^^1 I l^nf Lvr^i — » i \~~J (請先閉讀背面"注意Ϋ項再填寫本頁) 請參考第1圖所示之橫截面圖，可以對這個問題有 作較好的示例說明。圖示中所顯示的是在包含半導體元 件之基板上一絕緣層12的部分，為簡化圖示和說明起見 ，圖中並未顯示出基板和元件。一第一金屬（導電）層14 經定義圖案以形成金屬線丨4，一低介電質常數旋覆聚合 物16(此後以低k聚合物簡稱）係沉積於第一金屬線丨4上 方暨其間，做為一金屬間介電質（1%〇)層16 ，並業經平 面化處理〇 —無機的絕緣層18(如氧化矽）經沉積，並對 層18和IMD層16蝕刻呈通孔。接著，金屬栓或第二金 屬線形成於通孔中，與第—金屬線14做電性接觸，如第 1圖所示’此等通孔20中之一者具有一金屬栓22 ^接著 ’沉積第二金屬層24並經定義圖案，以形成第二金屬交 連線24。當元件的最小特徵尺寸減小且組裝密度增加時 ’用以連接元件的金屬線14間相對應的間隔七亦減小， 故增加電容C1(如第1圊所示）導致較長的rc延遲時間。 再者，隨著佈線密度的增加，因為增加了表面積A，故 也會增加金屬層（14和24)間的電容C2。因此，可使用如 層16之低k聚合物來減少整體電容，以增加電路速度且 減少相鄰金屬線間的耦合。 然而，當钱刻低k聚合物成通孔時，在電毁餘刻施 行後，為移除通孔光阻钮刻遮罩（etch mask)，會施以氧 電漿灰化（ashing)，此時，會對通孔内露出之聚合物造成 破壞。此低k聚合物（或低k旋覆玻璃（SOG))被破壞的部 本紙浪尺度適汛中國國家標準（CNS ) Λ4現格（210X297公釐） 415004 Α7 Β7 經濟部中央標泽局負工消費合作社印梦 五、發明説明（3) 刀因應力而斷裂’而變得更易吸濕（hygr〇SC〇piC)，因此’ 被破壞的低k聚合物或低k旋覆玻璃在爾後暴露於大氣 時’對濕氣的吸收導致金屬腐敍及通孔内的高接觸電阻 。這個問題請參照第2〜4圖做為示例，說明習知形成低k 聚合物IMD層/通孔結構。 如第2圖所示，沉積一第一金屬層μ並經定義圖案 以形成金屬線14，位於一基板上元件上方之一絕緣層i2 上’圖示中並未顯示基板和半導體元件，以簡化圖示和 說明。接著’選擇性地經由一黏附層/障礙層 (adhesi〇n/barrier)17(如一低溫電漿辅助化學汽相沉積 (PEC VD)氧化矽）’旋轉塗佈一低让聚合物層丨6。低k聚 合物經固化（curing)後，沉積一第二iMD層〖8 ,並籍由 化學/機械拋光法（CMP)予以平面化，此第二imd .層18 通常是一電漿輔助化學汽相沉積（pECVD)氧化矽。一通 孔光阻遮罩30經傳統方法形成，在第一金屬線14上方 IMD層16和18内所需處形成開口。現在，如第3圊所 示’％以非等向電漿姓刻形成例如通孔2，如第$圖所 顯示，在通孔蝕刻之後，光阻遮罩3〇是藉由氧電漿灰化 (ashing)來移除。但是，低k聚合物16(或s〇G)暴露於通 孔中之部分16’，遭致氧電漿破壞，產生一多孔且繃緊之 吸濕層，其會吸收濕氣（水）並劣化（腐蝕）後續形成於通孔 内用以與下一金屬交連之金屬检。 為防止低k聚合物暴露問題的發生，一般是施以部 分回餘法（partial etch back) ’其中，低k聚合物Μ經蝕 本紙張尺度適用中國阀家標準（CNS ) Λ4現格（2]〇χ297公釐） ---I- -1 f — If Ikl - -'.衣--- I I -- si - - - (請先s讀背*-之注意Ϋ-項再填寫本百) 經濟部中次標準局員工消资合作社印製 415004 at ______ 87 五、發明説明（5 ~〜 刻或拋光至在金屬線14上的障礙層n，接著沉積第二 CVD氧化矽絕緣層丨8。通孔係經蝕刻形成於層18和17 内’因此，如第5圖所示，可防止低以合物或s〇(}暴 路然而’這個製程比杈複雜’而且喪失了金屬層間使 用低k聚合物層以降低層間電容^2的優點。 有數種採用SOG形成平面化交互連接做為金屬間介 電質的方法已被提出，例如，Sayka u s, patent N〇 5,472,825揭示類似於第5圖所顯示的習知技術的s〇G回 蝕法，但對非回蝕方法中低1^聚合物或s〇G的破壞問題 未予著墨。另一多層交互連接和絕緣層的形成方法是由415004 A7 87 δ9. V. Description of the invention (1) ~ —— The present invention is a method for manufacturing integrated circuits on a semiconductor substrate, and particularly relates to an intermetal dielectric having a low dielectric constant (k) ( IMD) layer formation method 'to reduce the multilayer wiring of semiconductor integrated circuits, please read the back · Caution _ item, and then fill in ί page RC time delay, this method is particularly suitable for the minimum feature size (fee e size) Interconnection between the muscles of extra-large integrated circuits smaller than 0.25 microns (um). The manufacture of ultra-large integrated circuits (ULSI) on semiconductor substrates requires multiple layers of metal interconnections to connect individual semiconductor components such as field-effect transistors (FETs) and bipolar transistors on semiconductor wafers. Among the known methods, the silicon oxide (SiO2) is formed by plasma-assisted chemical vapor deposition (PEC VD), which is placed between adjacent metal lines and between different metal cross-linked layers as an insulating layer. The metal wires are electrically isolated, and the insulating layers are etched into via holes to connect a metal layer to the next metal layer. Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Generally speaking, silicon oxides have a relatively high dielectric constant k (relative to vacuum)', which is approximately 4.1 to 4.5. However, if the rc time constant can be reduced, the circuit performance will be improved. Therefore, the resistance R of the metal line and the capacitance C between the metal line must be reduced. Under the trend of shrinking component size and increasing assembly density, in order to reduce the distance between the interconnected metal lines ′ to effectively connect the integrated circuit, it is particularly important to reduce the resistance R of the metal line and the capacitance C between the metal lines. However, when the interval between the metal lines is reduced by y ', because the electric valley C 疋 and the wiring are inversely proportional (c = ke〇A / d, where' k is the relative dielectric constant 'and e〇 is the permittivity of the vacuum (permittivity), A is the area 'd is the distance between the wiring), so this paper size applies the Chinese National Standard (CNS) Λ4 specification (210x 297 mm) 415004 A7 87 δ 9. V. Description of the invention (1) ~ —— The present invention is a method for manufacturing integrated circuits on a semiconductor substrate 'particularly, a method for forming an intermetal dielectric (IMD) layer having a low dielectric constant (k)' to reduce semiconductor integrated circuits Please read the back of the multi-layer wiring. Note the _ item, and then fill in the RC time delay of the page. This method is especially suitable for extra large integrated circuit circuits with a minimum feature size of less than 0.25 microns (um). Interconnection. The manufacture of ultra-large integrated circuits (ULSI) on semiconductor substrates requires multiple layers of metal interconnections to connect individual semiconductor components such as field-effect transistors (FETs) and bipolar transistors on semiconductor wafers. Among the known methods, the silicon oxide (SiO2) is formed by plasma-assisted chemical vapor deposition (PEC VD), which is placed between adjacent metal lines and between different metal cross-linked layers as an insulating layer. The metal wires are electrically isolated, and the insulating layers are etched into via holes to connect a metal layer to the next metal layer. Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Generally speaking, silicon oxides have a relatively high dielectric constant k (relative to vacuum)', which is approximately 4.1 to 4.5. However, if the rc time constant can be reduced, the circuit performance will be improved. Therefore, the resistance R of the metal line and the capacitance C between the metal line must be reduced. Under the trend of shrinking component size and increasing assembly density, in order to reduce the distance between the interconnected metal lines ′ to effectively connect the integrated circuit, it is particularly important to reduce the resistance R of the metal line and the capacitance C between the metal lines. However, when the interval between the metal lines is reduced by y ', because the electric valley C 疋 and the wiring are inversely proportional (c = ke〇A / d, where' k is the relative dielectric constant 'and e〇 is the permittivity of the vacuum (permittivity), A is the area 'd is the distance between the wiring), so this paper size applies the Chinese National Standard (CNS) Λ4 specification (210x 297 mm) 415004 A7 ------- B7 V. Invention Explanation (2) Add capacitor C. Printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 31 •-^^^ 1 I l ^ nf Lvr ^ i — »i \ ~~ J (Please close the back " note the items before filling out this page) Please refer to Section 1 The cross-sectional view shown in the figure can better illustrate this problem. The figure shows a part of an insulating layer 12 on a substrate containing a semiconductor element. For simplicity of illustration and description, the substrate and elements are not shown in the figure. A first metal (conductive) layer 14 has a defined pattern to form a metal line. A low dielectric constant spin-on polymer 16 (hereinafter referred to as a low-k polymer) is deposited on the first metal line. In the meantime, as an intermetallic dielectric (1% 〇) layer 16 and subjected to a planarization treatment, an inorganic insulating layer 18 (such as silicon oxide) is deposited, and the layer 18 and the IMD layer 16 are etched as through holes. . Next, a metal plug or a second metal wire is formed in the through hole to make electrical contact with the first metal wire 14 as shown in FIG. 1 'one of these through holes 20 has a metal plug 22 ^ followed by' A second metal layer 24 is deposited and has a defined pattern to form a second metal intersection line 24. When the minimum feature size of the component is reduced and the assembly density is increased, the corresponding interval between the metal wires 14 used to connect the components is also reduced, so increasing the capacitance C1 (as shown in Figure 1) results in a longer rc delay. time. Furthermore, as the wiring density increases, since the surface area A is increased, the capacitance C2 between the metal layers (14 and 24) is also increased. Therefore, a low-k polymer such as layer 16 can be used to reduce overall capacitance to increase circuit speed and reduce coupling between adjacent metal lines. However, when money is engraved with a low-k polymer into a through hole, oxygen plasmon ashing will be applied to remove the etch mask of the through hole photoresist button after the electrical destruction is performed. At this time, , Will cause damage to the polymer exposed in the through hole. This low-k polymer (or low-k spin-on-glass (SOG)) was damaged and the paper size of the paper was suitable for the flood season. Chinese National Standard (CNS) Λ4 is present (210X297 mm) 415004 Α7 Β7 Consumption cooperative Yin Meng 5. Description of the invention (3) The knife breaks due to stress and becomes more hygroscopic (hygroscopic), so 'the destroyed low-k polymer or low-k spin-on glass is subsequently exposed to Atmosphere's absorption of moisture leads to metal corrosion and high contact resistance in the vias. Please refer to Figures 2 to 4 as an example to illustrate the conventional formation of a low-k polymer IMD layer / via structure. As shown in FIG. 2, a first metal layer μ is deposited and a defined pattern is formed to form a metal line 14 on an insulating layer i2 above a component on a substrate. The substrate and semiconductor components are not shown in the illustration to simplify Graphic and description. Next, a low-admission polymer layer 6 is selectively spin-coated via an adhesion layer 17 (such as a low temperature plasma-assisted chemical vapor deposition (PEC VD) silicon oxide). After curing the low-k polymer, a second iMD layer [8] is deposited and planarized by chemical / mechanical polishing (CMP). This second imd. Layer 18 is usually a plasma-assisted chemical vapor Phase deposition (pECVD) silicon oxide. A through-hole photoresist mask 30 is formed by a conventional method, and an opening is formed in a desired place in the IMD layers 16 and 18 above the first metal line 14. Now, as shown in Figure 3, '% is engraved with a non-isotropic plasma name to form, for example, the through hole 2. As shown in FIG. $, After the through hole etching, the photoresist mask 30 is made of oxygen plasma gray. To remove. However, the low-k polymer 16 (or SOG) exposed to the portion 16 'in the through hole is damaged by the oxygen plasma, resulting in a porous and tight moisture absorption layer, which will absorb moisture (water) And the deterioration (corrosion) is subsequently formed in the through hole for metal inspection to be connected with the next metal. In order to prevent the problem of low-k polymer exposure, a partial etch back method is generally used. Among them, the low-k polymer M is etched and the paper size applies the Chinese valve standard (CNS). 〇χ297mm) --- I- -1 f — If Ikl--'. Yi --- II-si---(please read s back *-note Ϋ-item before filling in this hundred) Economy Printed by the Consumers ’Cooperative of the Ministry of Standards and Standards Bureau 415004 at ______ 87 V. Description of the invention (5 ~~ etched or polished to the barrier layer n on the metal wire 14, and then deposit a second CVD silicon oxide insulating layer 丨 8. The pores are formed in layers 18 and 17 through etching. Therefore, as shown in Fig. 5, low-alloy compounds or so () can be prevented. However, 'this process is more complicated than branching' and the use of low-k between metal layers is lost. The polymer layer has the advantage of reducing the interlayer capacitance ^ 2. Several methods using SOG to form a planar interactive connection as the intermetal dielectric have been proposed. For example, Sayka us, patent No. 5,472,825 reveals similar to that shown in Figure 5. Shown SOG etchback method for conventional techniques, but damage to low 1 ^ polymer or SOG in non-etchback methods Not inked. Another method for forming multilayer interconnections and insulating layers is
Nagata，U，S. Patent No. 5,082,801 提出’其中，一障礙/ 電子遷移層形成於經定義圖案之第一金屬層（A1)上，接 著障礙/電子遷移層經定義圖案以減少近通孔處後續覆 蓋之絕緣層所產生之應力，但Nagata並沒有說明也沒有 使用低k聚合物或SOG層以減少rc延遲時間或平面化 〇 因此，在半導體工業亟需一種簡單的非回姓法，用 以在多層金屬父互連接上’不會對低IMD層或SOG層造 成破壞’具有小的層級間暨層級内電容和較好的可靠度 〇 本發明的一目的，在於提供一金屬間介電質層，其 部分包含積體電路上，緊密地相隔的交連金屬線上方的 低介電貝常數方疋覆聚合物，因此可減小電路的時間延 遲。 本紙張尺度適用中S國家標準（CNS ) Λ4規格（210 x297公f ) (請先聞讀背面之注意事項再填寫本買) I--- i It I— - . - 1 - - 1 n ----訂____ 415004 經滴部中央標丰局貝工消费合作社印製 A7 B7 五、發明説明（5) 本發明的另一個目的，在於使用一個新的通孔蝕刻 製程’預防在光阻灰化（ashing)時，對低k聚合物（或SOG) 造成破壞（增加多孔性），引起的濕氣的吸收問題’係於通 孔中形成金屬栓之時或之後的濕氣逸散，導致可靠度降 低，此通柄為被破壞的通孔（p〇is〇nedvi£iho丨es)a 本發明的再一個目的，在於預防發生於被破壞的（有 孔的）和未被破壞的旋覆聚合物間邊界處的應力和膜斷 裂’進一步維持低k聚合物，否則會因通孔中破壞的旋 覆聚合物的污染而增加應力和膜斷裂口 為了符合本發明的目的，提供一新方法用以形成一 IMD層’部分包括一具有在多層互相連接且無破壞通孔 的低介電質常數旋覆聚合物，所改良的通孔是藉由在氧 中電漿灰化（ashing)，以移除通孔光阻遮罩時，保護低k 聚合物以免被破壞。 第一實施例的方法是由提供一具有一絕緣層的基板 開始’如一具有場效電晶體（FETs)和/或雙極電晶體元件 結構的半導體基板’且保護並藉由絕緣層電氣地隔離第 一導電層，沉積一第一導電層並經定義圖案，用以經由 在絕緣層的接觸開口和半導體元件建立電氣接觸，通常 第一導電層是銘（A1)或一鋁銅（Al-Cu)合金，且包含一在 下障礙層如鈦（Ti)或氮化鈦（Ti nitride)，以防止鋁刺穿在 矽基板上或中的半導體元件的淺接面，一第一金屬間介 電質（IMD1) ’包含一低k聚合物，這個低k聚合物是旋 覆在經定義圖案第一導電層之上，具有或不具有黏附層 本紙張尺度適刑中國國家標準（CNS ) Λ4规格（210X297公釐） C請先聞讀背面之注意事項再填寫本頁)Nagata, U, S. Patent No. 5,082,801 proposes' wherein a barrier / electron migration layer is formed on the first metal layer (A1) with a defined pattern, and then the barrier / electron migration layer is defined with a pattern to reduce the number of near vias The stress generated by the insulating layer that is subsequently covered, but Nagata does not explain or use a low-k polymer or SOG layer to reduce the rc delay time or planarization. Therefore, a simple non-return-to-name method is urgently needed in the semiconductor industry. In order to have no damage to low IMD layers or SOG layers on the multilayer metal parent interconnection, it has small inter-level and inter-level capacitance and good reliability. One object of the present invention is to provide an inter-metal dielectric The mass layer, part of which contains a low dielectric shell constant square polymer on the integrated circuit above the closely spaced cross-linked metal lines, can reduce the time delay of the circuit. This paper size applies to the National Standard (CNS) Λ4 size (210 x 297 male f) (please read the precautions on the back before filling in this purchase) I --- i It I---.-1--1 n- --- Order ____ 415004 Printed by Ai B7, Biaofeng Consumer Cooperative, Central Standard Bureau of Dibu Department, A7 B7 5. Invention Description (5) Another object of the present invention is to use a new through-hole etching process to prevent photoresist During ashing, damage to the low-k polymer (or SOG) (increased porosity), and the problem of moisture absorption caused by moisture escaping at or after the formation of metal plugs in the through holes, Leading to a reduction in reliability, this through-handle is a damaged through-hole (poisonedvi £ iho 丨 es) a yet another object of the present invention is to prevent the damage (porous) and unbroken from occurring The stress at the boundary between the spin-over polymers and the film fracture 'further maintain the low-k polymer, otherwise the stress and the film fracture opening will increase due to the contamination of the spin-over polymer destroyed in the through hole. In order to meet the purpose of the present invention, a New method for forming an IMD layer 'part includes a layer having interconnects in multiple layers Low dielectric constant spin-on polymer without damaging the vias. The improved vias are ashed by plasma in oxygen to protect the low-k polymer from being damaged when the photoresist mask of the vias is removed. damage. The method of the first embodiment begins by providing a substrate having an insulating layer, such as a semiconductor substrate having field-effect transistors (FETs) and / or bipolar transistor element structures, and protecting and electrically isolating through the insulating layer. A first conductive layer, a first conductive layer is deposited and a defined pattern is used to establish electrical contact with a semiconductor element through a contact opening in an insulating layer. Usually, the first conductive layer is an A1 or an Al-Cu ) Alloy, and includes a lower barrier layer such as titanium (Ti) or titanium nitride (Ti nitride) to prevent aluminum from piercing the shallow junction of the semiconductor element on or in the silicon substrate, a first intermetal dielectric (IMD1) 'Contains a low-k polymer. This low-k polymer is spin-coated on the first conductive layer of a defined pattern, with or without an adhesive layer. This paper is punishable by the Chinese National Standard (CNS) Λ4 specification ( 210X297mm) C Please read the notes on the back before filling in this page)
，1T 415004 A7 87 :驶濟部中央標隼局貝工消費合作社印褽 五、發明説明（6 ) (如一低溫、電漿加強電漿輔助化學汽相沉積（PEcVD)氧 化矽）’ 一第二金屬間介電質（IMD2)沉積，可以包含一第 無機絕緣層’如一電漿輔助化學汽相沉積（pECVD)氮 化矽，沉積一相當厚的第三金屬間介電質（IMD3)層，包 3第一無機絕緣層，如電漿輔助化學汽相沉積（PECVD) 氧化矽，第三IMD層（氧化矽）是藉由例如化學/機械拋光 (CMP)，一光阻層旋覆於第三IMD層上，曝光並顯影光 阻，以當在多層金屬間介電質需要通孔時，在經定義圖 案第一導電層上的光阻上形成開口。 接著且更明確地根據本發明的方法，非等向的電衆 轴刻’用於蝕刻在開口的暴露的第三IMD3層到第二 IMD2(Si3N4) ’使用一氧電漿來剝除光阻蝕刻遮罩，而第 二IMD2層保護金屬間介電質（iMD1)層，以避免在電漿 灰化（ashing)時的氧破壞，現在，第二和第一 ιΜΕ)層（IMD2 和IMD1)，使用第三ιΜΕ>層作為一蝕刻遮罩（硬遮罩）， 被非等向蝕刻’電漿蝕刻最好是使用一高密度電漿蝕刻 法和一钱刻劑氣體包含一種或多種以下的氣體：氧（〇2) 、三氟甲烷（CHF3)、四氟化碳（cf+)和二氧化碳，以及使 用一載體氣體如氬（Ar) ’這完成了在金屬間介電質多層 (IMD3、IMD2、IMD1)到第一導電層（如Al-Cu)的通孔 的形成’而防止了在通孔中的低k聚合物（IMD1)的氧電 漿破壞。 错由第一實施例的方法’一第一次平面化的相當厚 的第一 IMD層（IMD1)，包括一低k聚合物，例如使用化 4* 4li iX J? ^ iA If! cb IA1 TJH Ja, .v/i / \ 4 ^ in II. / _ - ? 1' i- 0 A y 午 公 7 9 2 X o <讀先閲讀背面之注意事項再填寫本買) ", 1T 415004 A7 87: Printed by the Central Bureau of Standards of the Ministry of Economy and Trade, Cooperate of Beigong Consumer Cooperative, V. Invention Description (6) (such as a low temperature, plasma enhanced plasma-assisted chemical vapor deposition (PEcVD) silicon oxide) 'a second IMD2 deposition may include a first inorganic insulating layer, such as a plasma-assisted chemical vapor deposition (pECVD) silicon nitride, to deposit a relatively thick third intermetal dielectric (IMD3) layer, Package 3 The first inorganic insulating layer, such as plasma-assisted chemical vapor deposition (PECVD) silicon oxide, and the third IMD layer (silicon oxide) is, for example, chemical / mechanical polishing (CMP), a photoresist layer is spin-coated on the first On the three IMD layers, a photoresist is exposed and developed to form an opening in the photoresist on the first conductive layer of the defined pattern when a through hole is required in the multilayer intermetal dielectric. Then and more specifically according to the method of the present invention, the non-isotropic electrical axis is engraved 'for etching the exposed third IMD3 layer to the second IMD2 (Si3N4) in the opening' using an oxygen plasma to strip the photoresist The mask is etched, and the second IMD2 layer protects the intermetal dielectric (iMD1) layer to prevent oxygen damage during plasma ashing. Now, the second and first ιME) layers (IMD2 and IMD1) The third ιΜΕ > layer is used as an etch mask (hard mask), which is anisotropically etched. Plasma etch is preferably performed using a high-density plasma etch method and a coining agent gas containing one or more of the following Gases: oxygen (〇2), trifluoromethane (CHF3), carbon tetrafluoride (cf +), and carbon dioxide, and the use of a carrier gas such as argon (Ar). This completes the intermetal dielectric multilayer (IMD3, IMD2 IMD1) formation of through-holes to the first conductive layer (such as Al-Cu) prevents oxygen plasma destruction of the low-k polymer (IMD1) in the through-holes. Incorrect by the method of the first embodiment, 'a first planarization of a fairly thick first IMD layer (IMD1), including a low-k polymer, for example using 4 * 4li iX J? ^ IA If! Cb IA1 TJH Ja, .v / i / \ 4 ^ in II. / _-? 1 'i- 0 A y PM 7 9 2 X o < Read the precautions on the back before filling in this purchase) "
,1T 經濟部中央標準局員工消費合作社印製 415004 a? _____________B7___ 五、發明説明（7) 學/機械拋光（CMP)的方法來平面化，接著，沉積一第二 金屬間介電質（IMD2)層，包括輔助化學汽相沉積 (PECVD)氧化矽’再接著沉積—第三金屬間介電質（IMD3) 層，包括ShN4，傳統光學微影術（ph〇t〇iith〇graphy)技術 (photolithographic techniques)是用以形成一光阻遮罩，具 有開口，在第一導電層上須要接觸的地方之上，第三IMD 層（IMD3)接著蝕刻到第二IMD層（ΙΜΕ>2)，且光阻是由氧 電漿灰化（ashing)剝除，而IMD2預防低k聚合物（ΪΜϋ1) 以免被破壞’第三低k聚合物（IMD3)層是用於作為一硬 遮罩，且在剩下的層中钱刻通孔到第一導電層，使用例 如一蝕刻混合氣體，如CF4和/或CHF3，並使用Ar作為 載體氣體。 在兩個實施例中’既然在相當長的電漿灰化（ashing) 步驟中’暴露的低k聚合物並未暴露到氧中，因此，低k 聚合物基本上是不會被破壞的。 為讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉可以實施例’並配合所附圖式，作 詳細說明如下： 圖示之簡單說明： 第1圖係顯示一習知的第一和第二金屬交互連接結 構的橫截面圖，此結構使用一低k聚合物作為在金屬層 中的金屬間介電質（IMD)層，同時也分別說明了所需減少 的層間和層内電容C1和C2 ; 第2〜4圖係顯示習知技術用以製造一金屬間介電質 10 本紙張尺度適;f]中國囤家標準（CNS ) A4規格（2丨0X 297公釐) 請先閱讀背面之注意事項再填寫本頁) 衣· 訂 415004 A7 B7 經濟部中央橾隼局員工消资合作社印焚 i、發明説明（8) 結構的一順序步驟的橫截面圖，金屬間介電質内具有通 孔’顯示在氡電漿灰化（ashing)以移除光阻遮罩時，所露 出的低k聚合物遭受破壞； 第3圖係顯示習知技術用以製造一金屬間介電質結 構的橫載面圖，其使用部分回蝕方法，以避免在去除光 阻遮罩時，氧電漿灰化（ashing)對低k聚合物的破壞； 第6〜8圖係顯示根據本發明的第一實施例的方法， 製造一無破壞的低k聚合物金屬間介電質的製造流裎步 驟的橫斷面圖；以及 第9〜II圖係顯示根據本發明的第二實施例的方法， 製造一無破壞的低k聚合物金屬間介電質之製造流程步 驟的橫斷面圖。 符號之簡單說明： 1 :開口； 2 :通孔：12 :絕緣層；14 :導電層； 16:低k聚合物；16': 16的部分；17:黏附/障礙層； 18:無機絕緣層；20:第三IMD層；20':第二IMD層 :22 :金屬栓；22':第三IMD層；24 :金屬層；30 :光阻遮罩；32 :金屬層；Cl、C2 :電容；dl、d2 :間隔。 實施例： 本發明是關於製造低k聚合物金屬間介電質（IMD) 的方法，其令I虫刻通孔時不會破壞暴露於通孔中的低k 聚合物。這個方法，在施以氧電漿移除通孔光阻遮罩之 後，利用部分蝕刻法在一多層金屬間介電質中形成一硬 Π 本紙張尺度適;t]中國國家標皁（CRS ) Λ4規格U〗〇X 297公釐） (請先閱讀背面之.注意事項再填寫本頁) [ 策. 訂 A7 415004 _______B7^_ 五、發明説明（9) I _ ί n _ n I I - ---In n T ，vs (請先閱讀背面之注意事項再填寫本頁} 遮罩。一第二IMD層（1MD2)避免低k聚合物遭受氧電毁 破壞。雖然這個方法係用以在第一和第二經定義圖案之 導電層（如鋁或鋁-銅）間形成一 IMD，熟習此技術者應該 很了解這個方法可以應用於在一多層互相連接結構的其 它金屬層之間的IMD層。 請參照第6圖’第一實施例的方法是始於提供一具 有由一緣層12所保遵之半導體元件的一半導體基板， 為簡化圖示及說明’只有顯示絕緣層12的上方部分。 經濟部中夾標隼局負工消费合作社印製 如第6圖所示，沉積一導電層14並經定義圖案，層 14最好是由鋁-銅合金所組成，並包含下方如鈦或氮化妖 之一障礙層，以防止鋁刺穿入矽基板，但未在圖示中分 以另一獨立層級做顯示。而沈積層14的方法，例如可藉 由物理；X相沈積（PVD)形成一第一金屬（Μ 1)層，其可以的 厚度約為4000〜8000埃。接著，以傳統光學微影術 (photolithography)技術和非等向蝕刻法定義層μ的圖案 ’此非等向姓刻法譬如可於含有氣之反應物混合氣體之 一活性離子蝕刻機（RIE)或一高密度電漿蝕刻機内 施行。第一金屬層U通常用以與基板上半導體元件做電 性接觸（未圖示）。在經定義圖案第一金屬層14上方的電 性絕緣層是藉由沉積三層IMD層（IMD1、IMD2、IMD3) 而得’第一金屬間介電質)層16可以者係經一黏附 層Π沉積，但也可以由製程需求決定，以無需黏附層17 的方式沉積。層16(IMD1)可以者係由一低k聚合物組成 ’並藉由旋轉塗佈來沉積。當欲使用黏附層17時，因為 _12 队ft尺度適用十國國家標準? CNS) Λ4規格公釐^ ^濟部中央標隼局貞工消費合作社印焚 415004 A7 B7 五、發明説明（10) I呂的溶點低的緣故，此黏附層17 —般是低溫氧化5夕層， 例如’層1 7可以由電漿輔助CVD在溫度範圍介於 250〜350°C之間，使用矽甲烷（SiH4)和氧作為反應物混合 氣體來沉積。接著’低k聚合物層16藉由旋轉塗佈沉積 ’例如’聚合物可以由有機物質組成，如聚醯胺 (polyimide)具有介電質常數在大約3_〇〜3 7之間、聚石夕倍 半氧烷（polysilsequioxane)其k值大約2.7〜3.0之間 '添加 氟素的聚醯胺（polyimide)具有一 k值大約2.5，以及類似 的矽和碳基之低k值有機聚合物薄膜，低k聚合物可以 厚度約2000至12000埃之間。 再請參照第6圖，沉積一第二金屬間介電質（imd2) 層18，可以是由一第一無機絕緣體組成，譬如是由電漿 輔助化學汽相沉積法（PECVD)形成之氮化矽（Si3N4)，此氮 化石夕（Si3N+)可以是由電漿輔助化學汽相沉積（pecvd)使 用矽甲烷（SiHO和氨（NH3)或矽曱烷（siH4)和氮（N2)作為 反應物混合氣體’並在溫度在200~350〇C之間沉積，層 1 8沉積的厚度約為1 〇〇〜2000埃。之後，沉積相對厚之一 第三金屬間介電質（IMD3)層2〇 ，此第三金屬間介電質 (IMD3)層係由一第二無機絕緣體組成，例如使是以電梁 輔助化學汽相沉積法（PECVD)形成之氧化矽，層2〇可以 是使用如矽甲烷（S〖H4)和氧之混合氣體，以電漿輔助化學 汽相沉積（PECVD)在溫度在200〜350°C間沉積，其厚度約 為2000〜8000埃之間。接著，對第三IMD層（氧化矽）2〇 施以化學/機械拋光（CMP)予以平面化，以提供一平坦之 本紙張尺度適用屮國國家標準i CNS ) Λ4规格（210X2*)7公楚） {請先閱讀背面之注意事項再填寫本頁) 裝. 訂 經濟部中央標革局負工消费合作社印^- 415004 A7 ---------87 五、發明説明（11 ) ' — 表面’以為下一層金屬交接之用。 第6圖_，一光阻層30藉由旋轉塗佈沉積於第三 IMD層20之上，利用傳統的光學微影術（ph〇t〇Uth〇graph^ 曝光顯影，而在光阻層30内形成開口，適位於經定義圖 案之第一導電層丨4需要通孔處上方，此等開口中之—者 即如第6圖所示之開口 1。 現在藉由本發明的方法，以具有開口丨之經定義圖 案光阻層30做為一通孔蝕刻遮罩，再對位於開口 ^内所 露出之第三IM D層（S丨& ) 2 〇進行非等向性電漿蝕刻及至 第二IMD層（SisNJU表面止，此舉會形成一經定義圖案 之硬遮罩（層20)，爾後此硬遮罩係用於完成到經定義圖 案第一金屬層14之通孔的蝕刻，第三1%〇層2〇可以使 用活性離子蝕刻法（RIE)或高密度電漿蝕刻法（HDp)配合 蝕刻混合氣體如四氟化碳（CFO和/或三氟化碳（CHF3)，並 可使用氬作為載氣（carrier gas)。 "月參考第7圖，使用一乳電槳灰化（asj^ng)剥除光阻 遮罩30，電漿灰化（ashing)可以在分離之一灰化（ashing) 系統中完成，但可以是在一多功能機台（dustert〇〇丨）或是 在與姓刻乳化石夕相同的社刻室中完成’以減少製程時間 和減少製造成本。在氧灰化時，第二IMD層18保護低k 聚合物（IMD1)層16，以避免發生習知方法之氧電裂破壞 〇 請參考第8圖’利用經定義圖案之第三imd層20做 為硬遮罩’蝕刻ShN4層1S(IMD2)和低k聚合物層 水紙张尺度適川中國S家找鼻（CNS ) Λ4况格（210X 297公疫） {請先閱讀背兩之注意事項再填寫本頁) τ____ --占 n A7 415004 五、發明説明（12) ! Γ— 於------1T - · (请先閱讀背面之注意事項再填寫本頁) 16(IMD1) ’完成通孔之剩餘部分，而及至金屬線μ。 SisN4層18可於一活性離子蝕刻機（RIE)或高密度電漿蝕 刻機（HDP)内經施以非等向電漿蝕刻，所使用的蝕刻混合 氣體諸如三氟化碳和氧。而低k聚合物層16也是經過非 等向電漿蝕刻，所使用之蝕刻氣體包含四氟化碳、二氧 化碳、以及三氟甲烷（CHF3)等之中一種或多種氣體，而 以氬作為載氣。根據第一實施例的方法，第8圖中位於 通孔2内露出之低k聚合物16部分16,，，是被保護以避 免在移除光阻層30(遮罩）時過量的氧電漿，所以低k聚 合物基本上是無破壞的。為完成多層金屬結構到第二金 屬層，則沉積一第二金屬層32並經定義圖案以形成金屬 線32(M2)，並在通孔2内和Ml成電性接觸。例如，第 二金屬層32可以是由物理汽相拋光（pVD)沉積得之鋁或 鋁銅合金，其下方亦可使用如鈦或氮化鈦一障礙層；另 一方面，也可以如鎢之金屬栓在M2金屬（鋁或是鋁銅合 金）形成前填充於通孔2内。 經濟部中"標弟局員工消资合作社印說 請參照第9〜11圖，以說明根據本發明之第二實施例 用以製造低k聚合物内之無破壞通孔’這個方法類似於 第實知例，所以各層的編號與第一實施例者類似。 請參考第9圖，在黏附層17形成於絕緣層12上之後 ，即如第一實施例，由旋轉塗佈沉積一相對厚低k聚合 物16以形成第一金屬間介電質（IMd 1)層1 6，層16是沉 積到一既定厚度，大約是8000〜丨5000埃’並經固化及迴 流（reflow)處理形成一平坦表面，或是經化學/機械拋光 15 本紙银尺度適用中國囤家標準（CNS ) Λ4规格（21〇χ 297公釐） 415004 經漪部中央標準局負工消资合作社印製 A7 B7 五、發明説明（13 ) ~-* (CMP)予以平坦化。接著，先沉積一第二金屬間介電質 (画2)層20,（電裝輔助化學汽相沉積法（pEcvd)形成之 乳化石夕物（Si02))，#沉積的第三金屬間介電質（1_)層 22 (Si#4所組成），氧化矽層2〇_的厚度約可介於 2000 4000埃之間’ Sl3N4的厚度約可介於剛〜之刪埃 之間。傳統光學«術（ph〇t〇mh〇graphy)技術則用於形成 在第-傳導層14的需要通孔處上方具有開口之光阻遮罩 ，即如第9圖t所示之開口 1。 參照第10圖’然後蝕刻第9圖開口 1内之第三IMD 層22’及於至第二丨^^層2〇,，以形成一硬遮罩做為通孔 蝕刻之用。接著’即如第一實施例，藉由在氧中電漿灰 化以剝除光阻，而硬遮罩22'用於完成通孔2及至第一金 屬層（Ml)的蝕刻處理’即如第丨丨圖所示。之後，沉積 第二金屬層32並經定義圖案形成下一個佈線層（M2)，完 成多層金屬結構到第二層。然而，因為低k聚合物層 16(IMD1)是相對較厚並平面化，故層22，(IMD3)與層 20’(IMD2)的總厚度可較第一實施例者為薄，更進一步能 減少電容值，因此縮短全部金屬間介電質 (IMD1+IMD2 + IMD3)厚度的RC時間延遲。 雖然本發明已以可以實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内’當可作更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 本紙裱尺度適用中國國家標準（CNS ) Λ4規格（210x 297公釐） ^1 m^i tfr— —ftn i 1^1^1 ^^^^1 \"J # (#先閱讀背面之注意事項再填寫本頁), 1T Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 415004 a? _____________B7___ V. Description of the Invention (7) Planarization by chemical / mechanical polishing (CMP) method, and then deposit a second intermetal dielectric (IMD2) Layers, including assisted chemical vapor deposition (PECVD) silicon oxide 'followed by deposition-a third intermetallic dielectric (IMD3) layer, including ShN4, photolithographic traditional photolithography technology Techniques) are used to form a photoresist mask with openings, where the first conductive layer needs to be contacted, the third IMD layer (IMD3) is then etched to the second IMD layer (ΙΜΕ > 2), and the light Resistance is stripped by oxygen plasma ashing, while IMD2 prevents low-k polymer (聚合物 ΜΪ1) from being damaged. The third low-k polymer (IMD3) layer is used as a hard mask and In the lower layer, a through hole is engraved to the first conductive layer. For example, an etching mixed gas such as CF4 and / or CHF3 is used, and Ar is used as a carrier gas. In both embodiments, since the low-k polymer exposed during the relatively long plasma ashing step is not exposed to oxygen, the low-k polymer is not substantially destroyed. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following specific examples can be used in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the diagram: Figure 1 shows A cross-sectional view of a conventional first and second metal interconnect structure that uses a low-k polymer as the intermetal dielectric (IMD) layer in the metal layer, and also illustrates the required reductions, respectively. Inter- and inter-layer capacitances C1 and C2; Figures 2 to 4 show the conventional technology used to make an intermetallic dielectric 10 papers of appropriate size; f] China Store Standard (CNS) A4 Specification (2 丨 0X 297 mm) Please read the precautions on the back before filling in this page) Clothing · Order 415004 A7 B7 Cross-sectional view of a sequential step of the structure of the Consumer Council of the Central Government Bureau of the Ministry of Economy The presence of through-holes in the intermetal dielectric indicates that the exposed low-k polymer was damaged when the plasmon was ashing to remove the photoresist mask; Figure 3 shows the conventional technology used to Fabricate a cross-sectional view of an intermetal dielectric structure that uses Partial etch-back method to avoid damage of low-k polymer by oxygen plasma ashing when removing the photoresist mask; Figures 6 to 8 show the method according to the first embodiment of the present invention, manufacturing A cross-sectional view of a non-destructive low-k polymer intermetal dielectric manufacturing process; and FIGS. 9 to II are diagrams showing a method according to the second embodiment of the present invention to produce a non-destructive low-k A cross-sectional view of the manufacturing process steps of a polymer-to-metal dielectric. Brief explanation of symbols: 1: opening; 2: through hole: 12: insulating layer; 14: conductive layer; 16: low-k polymer; 16 ': 16 portion; 17: adhesion / barrier layer; 18: inorganic insulating layer 20: third IMD layer; 20 ': second IMD layer: 22: metal plug; 22': third IMD layer; 24: metal layer; 30: photoresist mask; 32: metal layer; Cl, C2: Capacitance; dl, d2: interval. Example: The present invention relates to a method for manufacturing a low-k polymer intermetal dielectric (IMD), which prevents the low-k polymer exposed in the through-holes from being damaged when the worm is etched through-holes. In this method, after the through-hole photoresist mask is removed by applying an oxygen plasma, a hard etching method is used to form a hard paper in a multilayer intermetal dielectric using a partial etching method; t] China National Standard Soap (CRS) Λ4 Specification U〗 〇X 297 mm) (Please read the back. Note before filling out this page) [Policy. Order A7 415004 _______ B7 ^ _ V. Description of the invention (9) I _ ί n _ n II---- In n T, vs (Please read the notes on the back before filling this page} Mask. A second IMD layer (1MD2) protects the low-k polymer from oxygen electrical damage. Although this method is used in the first and A second defined pattern forms an IMD between conductive layers (such as aluminum or aluminum-copper). Those skilled in the art should understand that this method can be applied to IMD layers between other metal layers in a multilayer interconnected structure. Please refer to FIG. 6. The method of the first embodiment starts with providing a semiconductor substrate having a semiconductor element guaranteed by a marginal layer 12. To simplify the illustration and description, only the upper portion of the insulating layer 12 is shown. Printed by the Ministry of Economic Affairs, the Bureau of Work and Consumer Cooperatives, as shown in Figure 6 A conductive layer 14 is deposited and has a defined pattern. The layer 14 is preferably composed of an aluminum-copper alloy and includes a barrier layer such as titanium or a nitride nitride to prevent aluminum from penetrating into the silicon substrate. The figure is shown in another independent level. The method of depositing layer 14 can be, for example, physical; X-phase deposition (PVD) to form a first metal (M 1) layer, which can have a thickness of about 4000 ~ 8000 Angstroms. Next, the pattern of layer μ is defined by conventional photolithography and anisotropic etching. (RIE) or implemented in a high-density plasma etching machine. The first metal layer U is generally used to make electrical contact with a semiconductor element on a substrate (not shown). Electrical insulation over the first metal layer 14 in a defined pattern The layer is obtained by depositing three IMD layers (IMD1, IMD2, IMD3) to obtain the 'first intermetal dielectric' layer 16. The layer 16 can be deposited through an adhesion layer Π, but can also be determined by process requirements so that no adhesion is required Layer 17 was deposited. Layer 16 (IMD1) can be composed of a low-k polymer 'and deposited by spin coating. When the adhesive layer 17 is to be used, because the _12 team ft scale is applicable to the national standards of ten countries? CNS) Λ4 specification mm ^ ^ Printed by Zhengong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 415004 A7 B7 V. Description of the invention (10) Because of its low melting point, this adhesive layer 17 is generally a low-temperature oxidation layer. For example, layer 17 can be assisted by plasma-assisted CVD in a temperature range between 250 ~ 350 ° C. SiH4) and oxygen are deposited as a reactant mixed gas. Then the 'low-k polymer layer 16 is deposited by spin coating', for example, the polymer may be composed of an organic substance, such as polyimide, which has a dielectric constant between about 3 to 0 to 37, and polysilicon. Polysilsequioxane has a k value between about 2.7 and 3.0. 'Fluorimin-added polyimide has a k value of about 2.5, and similar silicon and carbon-based low-k organic polymer films. Low-k polymers can be between about 2000 and 12,000 angstroms thick. Referring to FIG. 6 again, a second intermetal dielectric (imd2) layer 18 is deposited, which may be composed of a first inorganic insulator, such as nitride formed by plasma-assisted chemical vapor deposition (PECVD). Silicon (Si3N4), this nitride (Si3N +) can be plasma-assisted chemical vapor deposition (pecvd) using silicon methane (SiHO and ammonia (NH3) or siloxane (siH4) and nitrogen (N2) as reactants The mixed gas is deposited at a temperature between 200 ~ 350 ° C, and the thickness of layer 18 is about 100 ~ 2000 angstroms. After that, a third thicker intermetal dielectric (IMD3) layer 2 is deposited. 〇, this third intermetal dielectric (IMD3) layer is composed of a second inorganic insulator, such as silicon oxide formed by electric beam-assisted chemical vapor deposition (PECVD), layer 20 can be used as A mixture of silicon methane (S 〖H4) and oxygen is deposited by plasma-assisted chemical vapor deposition (PECVD) at a temperature of 200 ~ 350 ° C, and its thickness is about 2000 ~ 8000 Angstroms. Three IMD layers (silicon oxide) 20 are planarized by chemical / mechanical polishing (CMP) to provide a flat surface. The paper size applies to the national standard i CNS) Λ4 specification (210X2 *) 7 Gongchu) {Please read the precautions on the back before filling in this page) Binding. Order printed by the Central Laboratories of the Ministry of Economic Affairs and Consumer Cooperatives ^-415004 A7 --------- 87 V. Description of the invention (11) '— Surface' is used for the next layer of metal transfer. FIG. 6_, a photoresist layer 30 is deposited on the third IMD layer 20 by spin coating, and is exposed and developed by using conventional optical lithography (ph0t0Uthgraph). An opening is formed inside, which is suitable to be located above the first conductive layer of the defined pattern, where a through hole is required, and one of these openings is the opening 1 shown in FIG. 6. Now, by using the method of the present invention, an opening is provided.丨 the defined pattern photoresist layer 30 is used as a through-hole etching mask, and then the third IMD layer (S 丨 &) 2 exposed in the opening ^ is subjected to anisotropic plasma etching to the second IMD layer (SisNJU surface only. This will form a hard mask with a defined pattern (layer 20). This hard mask is then used to complete the etching of the through holes to the first metal layer 14 of the defined pattern. % 〇 Layer 20 can use reactive ion etching (RIE) or high-density plasma etching (HDp) in combination with an etching mixed gas such as carbon tetrafluoride (CFO and / or carbon trifluoride (CHF3), and argon can be used. As a carrier gas. &Quot; Monthly reference to Figure 7, using a milk electric paddle ashing (asj ^ ng) to strip the photoresist Hood 30. Plasma ashing can be done in a separate ashing system, but it can be a multi-function machine (dustert〇〇 丨) or the same as the engraved emulsified stone eve Completed in the engraving chamber to reduce process time and reduce manufacturing costs. During oxygen ashing, the second IMD layer 18 protects the low-k polymer (IMD1) layer 16 to prevent oxygen electrocracking damage by conventional methods. Please Refer to Figure 8 'Using the third imd layer 20 with a defined pattern as a hard mask' Etching ShN4 layer 1S (IMD2) and low-k polymer layer Grid (210X 297 public epidemic) {Please read the two notes before filling in this page) τ ____-Account n A7 415004 V. Description of the invention (12)! Γ— In ----- 1T-· (Please Read the notes on the back before filling this page) 16 (IMD1) 'Complete the rest of the vias and reach the metal line μ. SisN4 layer 18 can be used in a reactive ion etching machine (RIE) or high-density plasma etching machine ( HDP) is subjected to non-isotropic plasma etching, using an etching mixture gas such as carbon trifluoride and oxygen. The low-k polymer layer 16 After anisotropic plasma etching, the etching gas used includes one or more of carbon tetrafluoride, carbon dioxide, and trifluoromethane (CHF3), and argon is used as a carrier gas. According to the first embodiment, The method, the low-k polymer 16 portion 16, exposed in the through hole 2 in FIG. 8, is protected from excessive oxygen plasma when the photoresist layer 30 (mask) is removed, so low-k polymerization Things are basically non-destructive. In order to complete the multilayer metal structure to the second metal layer, a second metal layer 32 is deposited and a defined pattern is formed to form a metal line 32 (M2), and M1 is electrically contacted in the through hole 2. For example, the second metal layer 32 may be aluminum or an aluminum-copper alloy deposited by physical vapor phase polishing (pVD), and a barrier layer such as titanium or titanium nitride may also be used below it. The metal plug is filled in the through hole 2 before the M2 metal (aluminum or aluminum-copper alloy) is formed. In the Ministry of Economic Affairs " Biaodi Bureau employee consumer cooperatives printed, please refer to Figures 9 to 11 to illustrate the method used to make non-destructive through holes in low-k polymers according to the second embodiment of the present invention. This method is similar to The first known example, so the number of each layer is similar to that of the first embodiment. Referring to FIG. 9, after the adhesive layer 17 is formed on the insulating layer 12, that is, as in the first embodiment, a relatively thick low-k polymer 16 is deposited by spin coating to form a first intermetal dielectric (IMd 1 ) Layers 16 and 16 are deposited to a predetermined thickness, approximately 8000 ~ 丨 5000 angstroms', and cured and reflowed to form a flat surface, or chemically / mechanically polished. 15 This paper is silver-scaled and suitable for use in China. Home Standards (CNS) Λ4 specifications (21〇χ 297 mm) 415004 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Consumers and Consumers Cooperatives, A7, B7. 5. Description of the invention (13) ~-* (CMP) to be flattened. Next, first deposit a second intermetallic dielectric (picture 2) layer 20, (emulsified stone (Si02) formed by Denso-assisted chemical vapor deposition (pEcvd)), #deposited third intermetallic The electrical (1_) layer 22 (composed of Si # 4), the thickness of the silicon oxide layer 20_ can be between 2000 and 4000 Angstroms', and the thickness of Sl3N4 can be between approximately Angstroms and Angstroms. The conventional optical technique (phOtmhgraphy) is used to form a photoresist mask having an opening above the through hole of the first conductive layer 14, which is the opening 1 shown in FIG. 9 t. Referring to Fig. 10 ', the third IMD layer 22' and the second ^^ layer 20 in the opening 1 in Fig. 9 are then etched to form a hard mask for through-hole etching. Then, as in the first embodiment, the plasma resist is stripped to remove the photoresist, and the hard mask 22 is used to complete the through hole 2 and the etching process to the first metal layer (M1). Figure 丨 丨 shown. After that, a second metal layer 32 is deposited and a next wiring layer (M2) is formed by a defined pattern to complete a multilayer metal structure to the second layer. However, because the low-k polymer layer 16 (IMD1) is relatively thick and planar, the total thickness of the layers 22, (IMD3) and 20 '(IMD2) can be thinner than that of the first embodiment, Reduce the capacitance value, and therefore shorten the RC time delay of the thickness of all intermetal dielectrics (IMD1 + IMD2 + IMD3). Although the present invention has been disclosed as above by way of examples, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention It shall be subject to the definition in the appended patent application scope. The mounting dimensions of this paper apply the Chinese National Standard (CNS) Λ4 specification (210x 297 mm) ^ 1 m ^ i tfr— —ftn i 1 ^ 1 ^ 1 ^^^^ 1 \ " J # (#Read the note on the back first (Fill in this page again)