TW396437B - A method of manufacturing a semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device in which a capacitor having a storage electrode is formed on a semiconductor substrate, comprising the steps of: forming silicon films on the semiconductor substrate and at the same time forming first and second endpoint marker layers for dividing the silicon films into three parts in a direction of thickness by using a material different from a material of the silicon films; etching the silicon films including the first and second endpoint marker layers; and controlling an etching depth of the silicon films based on the type of etched material, thereby forming the storage electrode.

Description

V. Description of the invention (1) Background of the invention The present invention relates to the conductor device of the Indri cal bulletin. It is a columnar electrode, so it has a large volume without increasing capacity. Production method. The steps. The selection of the gate electrode to the 4E diagram is only in a plurality of elements. 3, a manufacturing method of a semiconductor arrangement with a cylindrical capacitor (cyl capacltor). ': ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-dielectric The lower pole is made up-the contact surface of the core electrode and the lower electrode occupied by the round plus capacitor is in the range of the region and the capacitor is kept long: South accumulation. Jinyuan 4 Z (/ 1T, 4 ® cylindrical lower electrode is commonly referred to as the 4th to 4th E diagrams! § + 仏 ^ .a α is not obvious—see the conventional cylindrical capacitor, see Figure 4A, riding丄 Each from the detailed description, a gate oxide layer 2, a 3, a diffusion region 4 and the like are formed on a silicon substrate 1 according to a conventional manufacturing method to form an element. Section 4a Du Du, h% w + Ding Fan pieces, but the silicon substrate 1 actually has 仵 0 f. These elements and the isolation layer element 5 sequentially form an interlayer insulating layer 6 :: emulsion layer 7. The contact window 14 penetrates the interlayer insulation An oxide layer 7 κ scattered area 4. An oxide layer 8 is formed on the sidewall surface of the contact window 4 to change the electrical characteristics. When the contact window 14 is filled, it is also an oxide layer. 7 forms a polycrystalline silicon layer 9 of a predetermined thickness. An oxide layer 30 and a polycrystalline silicon layer of a predetermined width are stacked on the polycrystalline silicon layer 9. The oxide layer 30 and a silicon layer 1 3 A silicon oxide sidewall is formed on the sidewall. As shown in FIG. 4B, the oxide layer 7 is used as an etching final soil layer.

V. Description of the invention (2) = to describe the dream layer 9 and to use the oxide layer 30 as the termination layer to remove the oxide layer 30, as shown in FIG. 4C, to expose the silicon layer 9. As shown in the 4D picture, the sidewall is used as an etching mask, and the bottom is etched with a predetermined thickness. Then, a storage electrode 16 having a recessed opening is formed from the top of the stone layer 9. As shown in FIG. 4E, a dielectric-acoustic layer 18 is formed on the surface of the storage electrode 16—a cell thin plate electrode (ce), and the cylindrical capacitor is completed. Known technically, because in the step of carving the stone layer 9 in FIG. 4D, 2: 5: not easy to do, the thickness of the silicon sound on the bottom of the storage electrode 16: f is not easy to control. If the silicon layer on the bottom is too thin, memory operation error (hold error); if the stone layer is too thick, the inner area of the storage electrode 16 (inj, / capacity reduction, ner area) SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method capable of easily disposing a conductor. I Easy to control half of the etching depth In order to achieve the above-mentioned object, the present invention provides a semiconducting semiconductor ;;: is formed on a -semiconductor substrate-= ΐ;: ΐΓ. . . The method of making clothes includes the following steps: the hair layer is formed in the above-mentioned semi-electrochemical multiple layers, and the material different from the above-mentioned Shi Xi layer-the end point § end point marker (endpoint marker), . The above-mentioned silicon layer and the first and the first are etched; the Shixi layer is divided into three layers, and the etching depth of the above-mentioned silicon layer is controlled according to the description of the invention (3) to be etched to form the above storage electrode. Brief Description of the Drawings The first to the eighth drawings are cross-sectional views each showing a step of manufacturing a semiconductor device according to the first embodiment of the present invention. 2A to 2B are cross-sectional views each showing a step of manufacturing a semiconductor device according to a second embodiment of the present invention. Fig. 3 is a graph showing the relationship between the thickness of the undoped amorphous stone layer and the number of erroneous shapes HSG above it. 4A to 4E are cross-sectional views each showing a step of manufacturing a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1 01 ~ Si substrate; 102 ~ Gate oxide layer; 103 ~ Gate electrode; 104 ~ Diffusion area; 105 ~ Element isolation layer; 106 ~ Interlayer insulation layer; 107 ~ 未 # 杂 氧"Chemical layer; 109 to silicon layer; 1 10 to end point mark layer; 1 1 1 to silicon 4; 1 12 to end point mark layer; 1 1 3 to silicon layer; 1 1 5 to oxide layer; 1 1 5 a ~ sidewall; 1 1 6 ~ storage electrode; 1 1 7 ~ core; 1 1 8 'dielectric layer; 1 1 9 ~ unit plate electrode. Embodiments In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with reference to the accompanying drawings. 1A to 1E are cross-sectional views each showing a step of manufacturing a semiconductor device according to the first embodiment of the present invention.

Page 6 V. Description of the invention (4) Oxide oxide: ΑΛ is selectively formed on the silicon substrate 101-a gate electrode; il03 is formed on the mask = emulsion layer 1G2-an interelectrode electrode 1Q3. With a mask, the diffusion region 104 is formed on both sides of the gate electrode 103 in the silicon substrate 101. The gate oxide layer 102, the inter electrode 103 ', and the diffusion region 104 constitute an element. official. Figures 1 ^ to 1Η show only one element ', but in practice, a plurality of elements 711 are separated from each other by an element isolation layer (e 1 ement i solat ion f i lm) 1 05. An interUvel insulating film 106 and an undoped oxide layer 107 are sequentially formed on these elements and the element isolation layer 05. The contact window 114 passes through the layers 106 and 107 and communicates with the diffusion region 104. An oxide layer is formed on the inner side of the contact 1 1 4 to improve the electrical characteristics. A dilute cyanofluoric acid is used to remove a natural oxide layer formed on the diffusion region, the contact window, and the bottom of the contact window, and a predetermined layer is formed on the oxide layer. ) The thickness of the silicon layer 109. At the same time, the silicon layer 109 will fill the contact window 11 4. An end mark layer 110, a silicon layer 111, an end mark layer 丨 2 and a silicon layer 丨 3 are sequentially formed on the silicon layer 109. When a silicon layer 10, 111, and 11 3 is composed of phosphorus-doped amorphous silicon, a gas containing silicon methane and phosphine can be placed between 52 ° ~ 53 °° C, 0.5 It is formed under a growth pressure of ~ 2.0 torr, and a concentration of i.oe20atoms / ccl0 or higher. The stone layer 111 may be doped or undoped amorphous silicon. The amorphous silicon can also be formed by plasma enhanced chemical vapor deposition (PE-CVD). When HSG (hemispherical particles,

Page 7 1 V. Description of the invention (5)

Henii-Spherical Grain) does not appear in the subsequent steps, 109, 1 1 1 and 1 1 3 can also be used polycrystalline. The end mark layers 11 0 and 1 丨 2 are about 2 nm thick silicon oxide layer or nitride ^ layer, which is formed by adding / adding 'milk or ammonia in the silicon layer ^ ㈣ and ^! Below. s end mark layer 丨 丨 〇 and 丨 丨 2 additional _ 軎 to stop the growth of silicon layers 109 and 111, add oxygen, so that a natural, oxide layer (nat i ve 〇xide) is formed on the surface of the silicon layer In this way, the silicon layers 10, 9, 11 and 1 1 3 can be continuously grown. As shown in FIG. 1B, the silicon layer 113 is subjected to anisotropic dry etching so that it only leaves a predetermined width in contact. Window 丨 丨 4. At this time, monitor the excitation of the etched material in the plasma at any time, and decide whether the etching should be stopped or not according to the luminous intensity of the substance contained in the end mark layer 2: End mark layer 11 When 2 is silicon oxide, the luminous intensity of oxygen is monitored. Mass spectrometers can also be used to analyze the inscription of the surname, instead of monitoring its luminous intensity to determine the end point of etching. As shown in Figure 1C, at 50 (TC or At a lower temperature, an oxide layer I 1 5 is formed on the end mark layer 112 and the silicon layer 113 by conventional CVD or PE-CVD. An impurity phosphorus or boron is implanted to form a BoroPhosphoSilicate Glass (BPSG). As shown in FIG. 1D, the oxide layer II 5 is etched back by an anisotropic dry etching method to form a silicon layer 11 3 The side wall 11 5 a on the side wall. As shown in FIG. 1E, the side wall 11 5a is used as an etching mask to etch the silicon layer 11 3, the end mark layer 11 2 and the silicon layer 111. After the silicon layer is etched, the ^, At any time to monitor the luminescence of the money carved in the plasma, according to the end point

V. Description of the invention (6) " The luminous intensity of the substance contained in the numbered layer 110 is used to determine whether the etching should be stopped. At the same time, the silicon layer i n, the end mark layer 丨 丨 0, and the Shi Xi layer 109 outside the side wall 1 15a are also removed by etching. As a result, a storage electrode i6 is formed, in which a silicon layer 109 is left at the bottom, so that the silicon layer 109 has a predetermined thickness. When the end mark layer 1 12 is oxidized stone, the luminous intensity of oxygen is monitored. Mass spectrometers can also be used to analyze the etched material instead of monitoring its luminous intensity to determine the etching end point. 1. As shown in FIG. 1F ', the side wall 1 1 5 a is selectively removed. If the oxide layer 107 is an undoped oxidized oxide layer and the sidewall 11 5 a is boron-filled glass, the hydrofluoric acid can be used to remove the sidewall 11 5 a. As shown in Figure 1G, 'remove the storage electrode with dilute hydrofluoric acid 丨] 6 after ^ natural oxide layer', at a temperature of 550 ~ 60 0 ° C and a pressure of imTorr or lower, pass Silica gas is introduced to deposit nucUi n7 on the surface of the storage electrode 116. As shown in Fig. 1H, when the core 1 1 7 is deposited on the surface of the storage electrode 1 1 6, the formed structure is annealed to form a protruded HSGsll7a. Then, a dielectric layer 118 and a unit plate electrode 11 9 'are formed to complete the cylindrical capacitor of the present invention. There is no need to grow HSGs here. Like the known technique, a dielectric layer and a cell plate electrode can be formed on the storage electrode without HSGs to complete a cylindrical valley device. In this example, the Shi Xi layer 'not _ θ is not a? ΑΛ- ^ A Τ- Ο T% ^ You Xi and Shi Xi Xi. Figures 2A to 2B show steps of a conductor device according to a second embodiment of the present invention. # 中 同 同 第 The same part in the H embodiment, in order to reduce the resistance or other ==

Page 9 V. Description of the invention (7) The qualitative ‘dream layer 109—II 111 and 丄 11 are doped-doped .. amorphous silicon. In addition, as shown in FIG. 2A, the 'undoped silicon layers 1220 and 1221 are formed on the interfaces of the end mark layers 1 10 and 1 12 and the silicon layer 1 11 respectively. The thickness of the stone evening layer 109 is 150 °, the thickness of the silicon layer hi is 49 nm, and the thickness of the stone evening layer 11 13 is 4 30 nm. The extent of the undoped amorphous silicon layers 1 2 0 and 1 2 1 is 30 nm. Once a heavily doped amorphous silicon layer is formed directly on an oxide layer, in the still-temperature process, such as the growth layer, the formation of HSG cores, and HSG tempering and other processes, the amorphous silicon layer will be removed from the oxide layer. Crystallization begins at the interface. More specifically, in Fig. 2A, the doped crystalline silicon layers 109, 丨 i, and 13 may be crystallized. When the HSG is to grow on the surface of the storage electrode, if the silicon layer reaches the surface of the storage electrode, it will prevent the growth of Hsg. Because, for example, C ′, it is particularly necessary to avoid the crystalline layer 1 1 1 which occupies the largest area in the storage electrode 丨 6. -The inventors of the present invention have discovered that the silicon layer can be avoided by forming undoped silicon layers 1 2 0 and 1 2 1 on the interface of the i-dot mark layers 110 and 112 and the silicon layer Uli, respectively. . Therefore, although the silicon layers 109 and 113 contacting the oxide layers 107 and 115 are crystallized into the polycrystalline silicon 122 ′ shown in FIG. 2B, the silicon layer Π1 is still undoped = silicon layers 1 2 0 and 1 2 1 Clamped and the osmium crystallized. Although the end mark layer 110 remains in the storage #electrode 116, its body is as thin as 2 nm. The thin end mark layer allows electrons to pass through it like a n-current (tunnel current), so no paraSltlC capacitor is generated. The thickness of the end mark layer is 10mm.

5. Description of the invention (8) lnm or larger, so it can be used as a reliable etching endpoint mark. It will be explained how to determine the thickness of the Fusong Zaxifei s & β Tochigi 4 Misaki ri sundial silicon layer 1 2 0 and 1 2 1. Figure 3 shows the relationship between the number of HSGs with poor shape in the undoped amorphous stone layer. As shown in Fig. 3, depending on the concentration of P-containing amorphous silicon-doped amorphous silicon layers, HSG's, depending on the layer below, and the material "HSG" will occur. The embodiment according to the present invention will be described in detail. The actual LP-CVD is used to form the silicon layers 109 and 113; the embodiment 4 is produced by pE-CVD deposition. The silicon layer 113 is formed by the material of each of the embodiments and The thickness is as follows: Silicon layer U 3: b-amorphous amorphous silicon layer (4 30 nm) end mark layer 1 1 2: silicon oxide layer (1 to 2 nm) non-amorphous amorphous silicon layer 1 2 1: Undoped amorphous lithium layer 121 (30nm) Silicon layer 111: 4 doped amorphous lithium layer (49 nm) Undoped amorphous crystalline silicon layer 120: Undoped Amorphous silicon layer 121 (30ηπ〇 end mark layer 1 1 〇:

Page 11 V. Description of the invention (9) Gasification stone layer (1 ~ 2nm) Silicon layer 1 0 9: Amorphous vermiculite layer (150nm) is used to detect the luminous intensity as follows. One of the methods (1) to (3) can be used to detect the end mark layers i ^ 0 and 1 12. (1) Detect the luminous intensity of oxygen. When the intensity increases, it can be regarded as the end point of etching. The wavelengths of the light measured by the debt are 437, 497, 502, 533, 544, 60 5 616, 646, 70 0, 725, and mnm. (2) Detecting the luminous intensity of silicon dioxide. When the intensity increases, it can be regarded as the end point of etching. The detected light wavelengths are 241, 234, and 249_. The difference between the p concentration in the 3rd p-doped layer and the doped layer. ® This detective ^ ^ again. § When the strength is increased, it can be regarded as the end of etching. The detection wavelength is 214 and 253nm. 1. The best price and advantage The following description uses the mass spectrometer Xiba # ancient, soil. The — all can be used to cook the M I instrument analysis method. Methods (1) ~ (4) Among them, 丨 』use layers of winter and winter marks! j 〇 and 丨 j 2. (1) The more the quality becomes, the more the 1 ', the more the β is, and the later is regarded as the end point of the etching. " 、 Measure the oxygen atom, when the intensity is enhanced, it is only necessary: see it. J 'point 6 °: to detect the silicon dioxide atom' as the intensity increases. Although the strength is enhanced, it can be regarded as the end of the etching. (4) The difference between the SiP concentration in the dopant layer and the dopant layer is calculated by using the undoped amount of "59" as the mass number. Causal detection of SiP atoms. Xing was born again,

Field strength can be regarded as eclipse. 5. End of Invention (IQ) engraving. <Example 2> The material and thickness of each layer are as follows: Silicon layer 11 3: Doped amorphous silicon layer (430 nm) End mark layer 丨 2: Oxide oxide layer (1 to 2 nm) Doped amorphous silicon layer 1 2 1: undoped amorphous silicon layer 1 2 1 (30 nm) silicon layer 111: doped amorphous silicon layer (90 nm) undoped non Crystalline silicon layer 1 2 0: Undoped amorphous silicon layer 121 (30nm) End mark layer 1 1 〇: Silicon oxide layer (1-2nm) Fragment layer 1 0 9: Doped amorphous system stone The method for detecting the luminous intensity by the evening layer (150 nm) is as follows. One of the methods (1) to (3) can be used for the end mark layer 丨 丨 〇 and 丨 丨 2. (1) Detect the luminous intensity of oxygen. When the intensity increases, it can be regarded as the end point of etching. The detected light wavelength is 4 3 7, 4, 9 7, 5 0 2, 5 3 3, 5 4 4, 6 0 5, 616, 646, 700, 725, * 777nm. (2) Detecting the luminous intensity of silicon dioxide. When the intensity increases, it can be regarded as the end point of rest. The detected light wavelengths are 241, 234, and 249 nm.

Page 13 V. Description of the invention (11) (3) The difference between the P concentration in the undoped layer and the doped layer is used. Therefore, by detecting the luminous intensity of P to detect the barrier layer 1 12, when the intensity is enhanced, it can be regarded as the end point of the etching. Therefore, by detecting the luminous intensity of P to detect the barrier layer 110, when the intensity is enhanced, it can be regarded as the end point of the etching. The detected light wavelengths are 2 1 4 and 2 5 3 nm. The analysis method using a mass spectrometer is described below. (1) Detecting the oxygen atom by the mass number "1 6", when the intensity is enhanced, it can be regarded as the end point of the etching. (2) Detecting the silicon dioxide atom with the mass number '' 60 &quot;, when the strength is enhanced, it can be regarded as the end point of the etching. (3) The difference between the P concentration in the undoped layer and the doped layer is used. Therefore, the mass layer "3 1" is used to detect the P atom to detect the barrier layer 1 1 2. When the strength is increased, it can be regarded as the end point of the money engraving. (4) The concentration of Si P in the undoped layer and the doped layer is used. The difference. Therefore, the mass layer &quot; 59 &quot; detects SiP atoms to detect the barrier layer 1 1 0. When the strength is enhanced, it can be regarded as the end point of the etching. <Example 3> The materials and thickness of each layer are as follows: Silicon layer 11 3: Doped amorphous amorphous silicon layer (430nm) End mark layer 11 2: Oxide oxide layer (1 ~ 2nm) undoped amorphous silicon layer 1 2 1: undoped amorphous silicon layer 121 (30nm)

Page 14

Shi Xi layer 11 1: Non-doped amorphous vermiculite layer (490 nm) Undoped amorphous silicon layer 1 2 0: Undoped amorphous silicon layer 121 (30 nm) End mark layer Layer 11 〇: Oxide oxide layer (1-2nm) Silicon layer 109: Doped amorphous stone layer (150nm) The method for detecting luminous intensity is as follows. ^ (1) Detect the luminous intensity of S 1 Ν. When the strength is increased, it can be regarded as etching. The detected light wavelengths are 4 41, 4 05, 4 0 9, 41 3, 4 2 0, and 424 nm. C2) The detection of the end mark layer 112 is performed by detecting the light emission ^ of the CD. When the intensity is enhanced, it can be regarded as the end of the etching. Lengths are 387, 418, 647, 709, and 78. Detect = 2 Photoresistance provided by 裎. The following describes the analytical method using a mass spectrometer. ::; s Nitrogen can be regarded as the end of the etch when the strength is increased. (3) Using j, when the intensity is increased, it can be regarded as the end point of money. U) The m column :: S1P atom in the undoped layer and the doped layer is used to detect the barrier layer 110, and when the strength is increased, the end point is g. * ¥ can be used as the remainder, then P it) t1 uses the m W atoms in the difference between the P concentration in the undoped layer and the doped layer to detect the I insulation layer 112. When the strength is increased: this is used to detect ____ Etched

P.15 5. Description of the invention (13) point. <Example 4> The material and thickness of each layer are as follows: Silicon layer 1 1 3: Plasma-CVD doped amorphous silicon layer (43 nm) End mark layer 11 2: Natural oxide stone Layer (native oxide film) (l ~ 2nm) undoped amorphous silicon layer 1 21: undoped amorphous silicon layer (30nm) silicon layer 1 1 1:

Doped amorphous silicon layer (490 nm) Undoped amorphous silicon layer 丨 2 〇: Undoped amorphous silicon layer 121 (30nm) End mark layer 1 1 〇: Silicon oxide layer (1 ~ 2_) Silicon layer 1 0 9: Doped amorphous silicon layer (丨 5 〇) The method for measuring the luminous intensity is as follows. Therefore, it is called (1 I to detect the luminous intensity of oxygen. When the intensity is increased, it can be regarded as an etch, ..., dot. The first wavelength of the detection of evening soil, crickets is 437, 497, 502, 533, 544, 605, 616, 646, 70 (2) detection and 777nm. ^ ^, Measure the luminous intensity of silicon dioxide. When the intensity is increased, it can be regarded as the end point of the etching. Find,, g ^ (3) The light wavelength measured by the price is 241 , 234, and 249rim ° 1 use the difference in P concentration between the undoped layer and the doped layer.

Page 16 1

Measure the luminous intensity of P to probe the end point of etching. By detecting p = ', and the layer 112, when the intensity is enhanced, it can be regarded as an enhancement. It can be regarded as the last name of the light intensity detection blocking layer 110'. When the intensity is described below, the light wavelength of the test is 214. And 25 3nm. ⑴ Mass Λ: Analysis method. Considered as the end of etching. To detect the oxygen atom, when the intensity is increased, (2) the mass age, β n &quot; + 谰 # can be counted as the number to detect the second atomic atom. 'When the intensity is enhanced, the day will be regarded as the end of the money. . Denbo: The difference between the p concentration in the f-doped layer and the doped layer for H. Therefore with quality

= Mody; tr 丨 Therefore, shoulder P atoms to detect the barrier layer 1 1 2. When the intensity increases, it can be regarded as the end point of silver engraving. Zindan (4 uses the difference between the S ip concentration in the undoped layer and the doped layer. Therefore, the barrier layer is detected by detecting the Sip atom with a Bailey number of 5 9. When the strength is increased, it can be regarded as the end of the etching. A In Example 4, "because the undoped amorphous silicon layer is grown by plasma", it is possible to use a lower growth temperature than Lp_CVD to form the stone layer 113 for the sacrificial stone layer. The thermal history "". Hysteresis) will be reduced, and crystallization of the storage electrode 丨 6 will not occur easily. The etching conditions of Examples 1 to 4 are as follows. Etching equipment Parallel plate reactive ion etching equipment (parallel plate reactive ion etching apparatus) pressure: 100 mTorr inter-electrode gap: 80 mm

Page 17 V. Description of the invention (15) C 12: 1 5 0 seem HBr -450 seem 〇 2: 5 seem top-side power: 5〇0 ψ bottom power (b〇tt〇m-side p 〇wer): 3〇〇 w

As described above, according to the present invention, since the G-number layer is located in the storage electrode, 仏 ^ ~ 5 points ^ π, so the etching is accurately controlled. When processing the storage electrode (· ,,,, ^ pr0Cessing the storage eecroe), the end point is recorded ^ ^ ^ ^ ^ and "extra removal steps are required. The layer is removed from the surface, so by using silicon The two parts of the layer are formed to avoid crystallization. The silicon layer that is mixed with the non-Japanese iron can be harmful to the HSG. The D layer prevents the formation of makeup.

Claims (1)

6. Scope of Patent Application 1. A method for manufacturing a semiconductor device is suitable for forming a capacitor with a storage electrode on a semiconductor substrate. The above manufacturing method includes the following steps: forming a plurality of layers on a semiconductor substrate The silicon layer, and the first and second end mark layers are formed by using materials different from the above silicon layer to divide the silicon layer into three; the engraved stone layer containing the first and second end mark layers is engraved; The material of the etched material controls the etching depth of the silicon layer, so the storage electrode is formed. 2. The method according to item 1 of the scope of patent application, wherein the step of controlling the etching depth of the silicon layer includes when the concentrations of the first and second end mark layers in the etched object reach a predetermined value, then Stop the etching step. 3. The method according to item 1 of the scope of patent application, wherein when the silicon layer is etched, both the first and second end mark layers have a thickness that does not have an etching stopper function. 4. The method as described in item 1 of the scope of patent application, wherein the first and second end mark layers are composed of an oxide stone layer having a thickness of 1 to 2 n m. 5. The method according to item 1 of the scope of patent application, wherein the step of controlling the etching depth further includes the following steps: monitoring the luminous intensity of the object to be etched; and determining the etching depth by the monitored result. 6. The method according to item 1 of the scope of patent application, wherein the step of controlling the etching depth further includes the following steps: Page 19 6. Scope of patent application Monitor the mass of the object to be etched; and determine the etching depth based on the monitored results. 7. The method according to item 1 of the scope of patent application, wherein the storage electrode is a polycrystalline silicon or an amorphous silicon. 8. A method of manufacturing a semiconductor device, the manufacturing method includes the following steps: forming a semiconductor element on a semiconductor substrate; forming an interlayer insulating layer on the semiconductor element; forming a contact window connection in the interlayer insulating layer To the semiconductor substrate; forming a first stone layer on the interlayer insulating layer, and filling the contact window with the first silicon layer;] forming a first end mark layer on the first silicon layer, the material Different from the first stone layer described above, a second end mark layer is formed on the second silicon layer, the material of which is different from that of the storage electrode; a third silicon layer is formed on the second end mark layer; the third silicon layer is etched to Forming a fourth stone layer having a predetermined width on the contact window, and controlling the silver engraving step according to a change in the type of the carved object; forming a silicon oxide side wall on the side wall of the fourth silicon layer; Using the spacer as a mask, the second and third silicon layers are etched, and an opening is formed in the second silicon layer to form a storage electrode. Change of kind to control the above etching step; Page 20 6. The scope of application for patents ... The method described in item 8 of the patent patent park further includes the following steps: after removing the spacers, storing the electricity and the dielectric layer on the above-mentioned dielectric layer; and A unit plate electrode is formed on the surface of the electrode on the dielectric layer. The method described in item 8 of the W-specific profit range when the Shi Xi layer is described, in which the thickness of the absolute function and the second end mark layer are both-without spare;-and the method described in item 1Q of the patent scope Fuzhong Budi's point mark layer consists of the 2nd-age oxygen-cut layer on the 2nd layer. The steps include when the above-mentioned object is etched: etching the material of the above-mentioned ring layer. # The third step at the moment, the heart; the layer * ^ Although the above-mentioned material in the to-be-etched material reaches a certain-predetermined value, the etching step is terminated. 、、; 点 记-, The method as described in item 8 of the patent scope, wherein the above-mentioned component. The third- and third-dreamer layers are replaced by an impurity-containing amorphous system 4; the quality is ^. The method described in item 13 of the scope of patent application, wherein the method described in item 8 of the above-mentioned Shi Xi range, wherein the above-mentioned ^^ is stored by the undoped amorphous $ M f d! The method described in claim 8 further includes the step of forming a plurality of hemispherical particles on the surface of the German electrode. Tapping Page 21 6. Scope of patent application 1 7. The method described in item 16 of the scope of patent application further includes the following steps: forming an interface with a predetermined value on the interface between the first end mark layer and the second stone layer. An undoped silicon layer having a thickness of one; and an undoped silicon layer having a predetermined thickness is formed on an interface between the second silicon layer and the second end mark layer. 1 8. The method according to item 16 of the scope of patent application, wherein the thickness of the above-mentioned undoped silicon layer is all above 30 nm. Page 22