TW391050B - The improved process method of the shallow trench isolation oxide - Google Patents

Abstract

The invention is about an improved process method of the shallow trench isolation oxide especially a method that can be used to solve the cornor problem and add the photoresist as mask to do the isotropic etching step such that the cornor is etched into rounding. The leakage current is then greatly reduced without the occurrence of double hump phenomena. In addition, after coating polymer, the polymer and silicon dioxide deposition layer is etched back to the height of silicon nitride layer by using the dry etching method. The planarization effect, which is better than the one known conventionally, is achieved from the use of chemical mechanical polishing (CMP) method to lap to the height of silicon nitride layer. Consequently, the improved process method of the shallow trench isolation oxide without the dishing effect is realized.

Description

Case No. 87103102 V. Description of the invention (1) The present invention relates to an improved manufacturing method of a shallow trench isolation oxide, especially a silicon nitride residue that can solve the problem of sharp corners and increase the photoresist as a mask to perform again The step of engraving is used to etch the sharp corners into rounding, which reduces the leakage current in a large amount, and no double peak phenomenon occurs. In addition, the polymer layer and the silicon dioxide deposited layer are etched back to the height of the silicon nitride layer by applying a polymer layer; the chemical mechanical polishing method (CMP) is used to grind to the nitride level The silicon layer height and other steps are achieved, and the planarization effect is better than those known, and an improved manufacturing method of a shallow trench isolation oxide that does not produce a disc effect. ^ In recent years, the development of the semiconductor industry has brought an indelible contribution to the improvement of the overall prosperity of Taiwan. After half of its growth, it has also strengthened its research and development, hoping that it can crowd out with greater roads. "International" is constantly innovating and improving various industrial technologies, and the present invention is one of them. Dizzy, ί ΐ ΐ Individual pad components and integrated circuits will use several thin, seed, dielectric, polycrystalline silicon, and metal layers, among which there is isolation between electronic components == moxide), It is one of the main manufacturing steps of each piece. The horizontal isolation of the thermal oxidation layer can not only make the element (LOCOS ^ solatization layer method is a bird's beak protruding from the local stone oxidization isolation technology), but because of its Figure 1E will be formed at the edge of the field oxide layer, which is generally a shallow trench :: The technique is gradually replaced, please refer to Figure 1-8; , First on the wafer

(K = k), which affects the flatness and reduces the limit of wafer density, because the manufacturing design of the device is reported when the groove size is small.

A thin first oxide layer (pad 〇xide) 912 is grown on top of = 0 on top of the extremely thin telecrystalline film 911; then, an oxygen oxide layer 913 is deposited, as shown in FIG. 1A: No 'connector' $ 成 光Resist pattern 914, as shown in Figure 1B; then use photoresist pattern 914 as a mask to perform non-uniform etching of oxygen cut 913 and the first oxide layer 912 and part of epitaxial layer 911 below it, & The first oxide layer 912 and the oxide stone layer 913 will form a slight undercut as shown in FIG. Κ and FIG. 1E, and a shallow trench 915 is etched on the wafer 91 () belonging to the isolation region. At this time, Undercuts will have sharp corners (Corno) 9152, and then grow on the second oxide layers 9153, 9154. The first oxide layers 9153, 9154 are formed using thermal oxidation. Due to the sharp corners 9152, When the silicon is thermally oxidized, the oxidant is difficult to enter because it is covered with a first oxide 912. After the thermal oxidation is completed, a sharp angle 9152 shape is formed as shown in FIG. 1E. Structure, this kind of sharp corners will leak (leakage), and the device will have the adverse effect of douMe hump, which will seriously affect the shallow trench. Isolation isolation oxide. The photoresist 914 was removed, and a CVD method was applied to fill the shallow trenches with a dioxide-based deposition to form a silicon dioxide layer deposition layer 9 [6]. In order to increase the flatness of the silicon dioxide deposition layer, there are two conventionally known methods: (A) The silicon dioxide deposition layer is directly flattened by chemical mechanical polishing (CMp). This method will cause a disc effect. (Dishing effect) The flattening effect is still not good. (B) Fill the interior of the deposition shallow trench 915 with the dichroic silicon and continue to grow up to the entire surface of the wafer 91; and then cover it with SOG (spin on glass) 917, as shown in FIG. 1E, and then perform s 〇G curing (SOG curing), followed by chemical mechanical polishing (CMp) to polish SOG 917 and the silicon dioxide at the bottom of SOG91 7 is connected to the ®

Page 5 _ cable number 87103102__ year, month, day, and article ___; 5. Description of the invention (3) 916 is ground to the same level as silicon nitride 913 to form a silicon dioxide deposition layer 916 ', as shown in FIG. 1F The final removal of gas> fossil evening 913 and oxide layer 912 is completed, as shown in FIG. 1G, but the above planarization effect is still not good. Based on the inventor's continuous research and development tests, he has proposed a process method that has never been seen before, which can effectively improve the shortcomings of the conventional process. The main purpose of the present invention is to provide a method to solve the problem of sharp corners. The photoresist mask is etched isotropically to engrav the sharp corners into rounding, which reduces the leakage current to a large extent, and does not cause double peaks. A secondary object of the present invention is to provide a method for solving the poor planarization effect, mainly by coating a polymer layer; and using a dry etching method to etchback the polymer layer and the dioxide dioxide deposited layer to nitride. Evening degree; the chemical mechanical polishing method (CMP) is used to achieve the silicon nitride layer t, and the planarization effect is better than those known. The gate is also briefly explained in the drawings: FIG. 1A to FIG. 1H are conventional shallow trench isolation oxidations. FIG. 1E is a partial enlarged view of FIG. 1C. Figure d, which is a cross-sectional view of the isolation oxide process. 2A to 2H are shallow image grooves of the present invention.

Brief description of the drawing number: The shallow trench isolation oxide 10 silicon substrate 12 13 silicon nitride layer 14 15 trench 1 53 of the present invention-case number 87103102_year 5th, description of the invention (4) 154 second oxidation Layer 16 17 polymer layer 16 '161 bumps conventional shallow trench isolation oxide layer 910 wafer 911 912 first oxide layer 913 914 photoresist pattern 9151 9152 sharp corner 9153 9154 second oxide layer 916 917 S0G layer Θ _____ Dioxide emission; Redundant layer Dioxide # Deposition layer Brilliant crystal film Silicon nitride layer The corner of the second oxide layer at the corner of the bottom of the silicon dioxide layer The formula is described as follows: An improved manufacturing process of a shallow trench isolation oxide of the present invention includes the following steps: '' (A) a first oxide layer 12 is formed on a silicon substrate 10;) is formed on the first oxide layer 12 The silicon nitride layer 13 is shown in FIG. 2A; C) A photoresist pattern 14 is formed on the degraded silicon layer 13 as shown in FIG. 2A; 'D1) The silicon nitride layer is formed by using the photoresist 14 as a mask. 1 3 is etched away; | D2) Use the photoresist 1 4 as a mask to cover the first oxide layer 丨2 etch away; (D3) etch silicon 10 with the photoresist 14 as a mask; D4) etch silicon nitride again with the photoresist 14 as a mask to etch the sharp corners into Rounding, as shown in FIG. 2C; U) long isolation oxide layers 153, 154; wide I ?, / --- ^ implanted impurities (field i mp 1 anta ti on) to increase silicon base

Board isolation effect; (G) deposition of silicon dioxide deposition layer 16 as shown in FIG. 2D; (H) densify the monoxide deposition layer; (1) coating polymer layer 1 7 As shown in FIG. 2E; (J) The polymer layer 丨 7 and the silicon dioxide deposition layer 丨 6 times of money are etched back to the height of the silicon nitride layer by dry etching, as shown in FIG. 2F It can be seen that the protrusions 161 remain after being etched away; (κ) is ground to the degree of the silicon nitride layer 13 by chemical mechanical polishing (CMp); (L) the silicon nitride layer 13 is removed; ( M) The oxide layer 12 is removed. The improved manufacturing method of the present invention is characterized by using steps (M) (D4), (I), and (j). The polymer is a flowable spin-sputter polymer (fiowable). spin-on Polymer), such as the trademark Accufiow of Aliied Signai, is a commodity. Step (A) A. The thickness of the first oxide layer 12 is 100 angstroms to 20 angstroms. Step (B) ), The thickness of the hafnium silicon nitride layer 13 is 1000 Angstroms to 2000 Angstroms. Step (C) The step of forming the photoresist pattern 14 is a conventional step. Steps (D1) to (D4) Tied in the same furnace tube When the step (D1) to (D 4) of the engraved name conditions were as follows: power of 200-500 watts 50_200ιπΤ force it CHF 5-35 seem CF5-35 seem

Ar 50-150 seem 05-15 seem magnetic field 0_30 chans. In step (E), the isolation oxide layers 153 and 154 are thermally oxidized dioxide layers formed at a temperature ranging from 1 to 100 degrees Celsius. In step (G), the silicon dioxide deposition layer 6 The height of the topography must be higher than the first oxide layer 2 and lower than the silicon nitride layer 13. The silicon dioxide deposition layer 6 is a 0 3 / silicon dioxide deposition layer or a HDP silicon dioxide Depositing the layer. In step (H), the silicon dioxide densification is completed by heating in a furnace tube at a temperature of 900 to 1100 ° C for 10 to 60 minutes. The conditions of the back-etching of step (J) are as follows:

Pressure 150-250 mT Power 150-900 W CHF10-20 seem CF110-160 seem 010-40 seem

Ar 100-175 seem N 5-15 seem

Page 9 Polymers vs. silica

Claims (1)

1. A reshuffle step of a shallow trench isolation oxide: a good process method, comprising (A) forming a first oxide layer on a stone substrate; (B) forming a nitride stone layer on the oxide layer; ( C) forming a photoresist pattern on the nitrided layer; (D1) etching the silicon nitride layer with the light J as a mask; (D2 ―) etching the oxide layer with the photoresist as a mask; D3) using the photoresist as a mask to etch away silicon; CD4) using the photoresist as a mask to etch silicon nitride again to engrav the sharp-cornered rice into a round custom (roui ^ di ng); ( E) a long isolation oxide layer; (F.) field implanted impurities' to increase the isolation effect of the silicon crystal plate; (G) deposition of a silicon dioxide deposition layer; (Η) densification of a dream oxide deposition layer; (I) Coated polymer layer; (J) etch back (tchback) the polymer layer and the silicon dioxide deposition layer to the height of the silicon nitride layer by dry etching; (K,) use chemical machinery Polishing method (CMP) grinding to the height of the silicon nitride layer; (L) removing the nitride cutting layer; (M 丨 〇 removing a first oxide layer. 2 described in the first scope of the patent application An improved and process method for a shallow trench isolation oxide, wherein the thickness of the first oxide layer is 100 angstroms to 200 angstroms. / 3. > The shallow trench isolation described in item 1 of the scope of patent application Improvement of oxides ---- Case No. 87〗 031⑽ 6. Scope of patent application and process method, wherein the thickness of the silicon nitride layer is 1000 Angstroms to 2000 Angstroms. 4. The method of improving the lean range of the shallow trench isolation oxide according to item 1 of the scope of the patent application, wherein the etching conditions of the steps (D1) to (D4) are as follows: · Pressure 50-200 mT Power 200-500 Watts. C HF 5-3 5 seem CF 5-3 5 seem Ar 50-150 seem 05-15 seem Magnetic field 0-30 Gauss. 5. The improved process method for shallow trench isolation oxide as described in item 1 of the scope of patent application, wherein 'the isolation oxide layer is a thermally oxidized dioxide formed at a temperature of 95 ° to 100 ° C Silicon layer. 6 · The improved calculation method for shallow trench isolation oxides described in item 1 of the scope of the patent application, wherein the topography of the silicon dioxide deposition layer must be higher than the oxide layer and lower than the atmosphere Layer · »7. An improved process method for a shallow trench isolation oxide as described in item 6 of the scope of patent application, wherein the 'the silicon dioxide deposition layer is a 0 // TE0s deposition' layer. — 8. The improvement of shallow trench isolation oxide as described in item 6 of the scope of patent application-Chlorine range method, wherein ‘the silicon dioxide deposition layer is HDP sand dioxide = --- ~ _ Case No. 871031 ⑽ ___ ^^ _ 6. Patent application group 9. The improved manufacturing method of shallow trench isolation oxide as described in item i of the patent application scope, wherein the paper densification is performed at Heat in a ^ V 'furnace tube below 900 to 1100 ° C for 10 to 60 minutes. 1 0 · As described in the improved process method of the shallow trench isolation oxide described in item 1 of the scope of the patent application, the conditions of the back step of the step (J) are as follows: pressure 150-250 mT power 500-900 watts CHF10 -20 seem Fork 6 0 seem 010-40 seem Ar 100-175 seem N 5-15 seem Magnetic field 0-30 Gauss e 11 · Improved manufacturing process of shallow trench isolation oxide as described in the patent application No. 10 Method, in which the rate of the polymer in Bu Cong I (J) relative to the oxidized oxide is between 1: 1 and 1: 6. 1 2. The improved process method for shallow / slotted trench isolation oxide as described in item 10 of the scope of patent application, wherein the compound is Accuf iow. 12th K