TW390038B - Method for fabricating poly-Si thin film transistors - Google Patents

Abstract

This invention proposes a simple method to fabricate self-aligned offset T-gate structure and self-aligned inverse-T gate LDD structure by anodicoxidation. These structures are mainly applied to Al-gate poly-Si TFTs. Utilizing different anodic oxidation rate of Al and other conductive materials (such as Ta,Cr or N+ a-Si) in specific electrolytes, different anodic oxide thickness can be obtained simultaneously. Putting Al in the lower layer with other materials in the upper one and anodizing in the same electrolyte, we can fabricate offset T-gate structure. Inverse-T gate structure can be formed with upper and lower layer materials interchanged. Offset T-gate structure has lower leakage current and excellent drive current ability whereas inverse-T gate LDD one has the merits of high-speed operation, higher transconductance and higher reliability. Because of the advantages mentioned above with low resistivity of Al, these technologies are very potential for future AMLCDs applications.

Description

The 5th 4 '-^ β.τ consumer cooperation shirt printed by the central part of the M Department 1: 1 A7 ------- Γ "-~ ---- V. Description of the invention Manufacturing method of complex thin film transistor H "proposes to form an auto-aligned offset τ-type gate (seifajjgjjed 〇ffset τ_ 5 gate) structure by anodization and automatically align the inverted τ-type gate with low doped drain (self aligned inverse-T gate LDD) structure, mainly used in aluminum gate complex silicon thin film transistors. BACKGROUND The polycrystalline silicon thin film transistor has the characteristics of high carrier mobility and driving current. The process allows peripheral driving circuits to be integrated on the same glass substrate, so it has been widely used in active matrix liquid crystal displays; Polycrystalline thin film transistors, especially gate materials, use metal inscriptions because of the low resistance of aluminum gates. FuHy-Seifajigned Polysilicon TFT LCD Driver Circuits, 1993, edited by E. Ohno et al., Page 425, is the future for large-scale I5 and high-resolution Essential choices for flat panel displays. Prior art In addition, the problem of high off-state leakage eutrent of the conventional multi-crystalline silicon thin film transistor still needs to be overcome. So far in 1988, K. Tanaka Yumada Yutian EE Electron Device Lett. Volume 9, page 23 proposed 20 Hfe (offset-gate), as shown in Figure 2 K. Tanaka et al. 1992

Electron Dev. Vol. 39, p. 916 proposed the electric field reading and drawing paper size China National Standard (CNS) A4 specification (210X297 mm) (read the notes on the back of the poem before filling this page), installed. 1T 3 A7 B7 V. Description of the Invention (2) Research on the device structure of Field-Induted-Drain (FID) and other elements, the main purpose is to reduce the lateral electric field of the drain extreme in order to reduce the leakage current ^ However, the bias gate structure has The low leakage current will reduce the ON-current 5; the FID structure improves the shortcomings of the low conduction f current while maintaining a low leakage current. There are already documents such as Y. Yafliamoto et al., Asia Display, p. 941 in 1995, M. Itoh et al., SID 96 Digest, p. 17, 10, and U.S. Patent Nos. 5,672,900 and 5,508,209, which advocate the use of anodized aluminum. The technology forms an auto-aligned bias gate structure. In addition, U.S. Patent No. 5,583,366 advocates anodizing Ta205 to form this structure. Although these bias gate structures can effectively reduce leakage current, they also have the advantage of low metal resistance. However, it also relatively reduces the on-state current; the 15 auto-aligned offset T-gates proposed by the present invention have a structure as shown in circle 3, and the T-shaped extended gates are used to achieve the electric field induced bow (drain effect; traditional FID The structure shown in Figure 2 requires an additional photomask before the attracting drain structure can be completed. Compared to the τ-type closed-pole extension structure of the present invention, aluminum and its advanced materials (such as Ta, Cr, n + a_Si) are used. The characteristics of different oxidation rates in a specific electrolyte, simultaneous oxidation, 20 to different thicknesses of oxides, and the function of automatic alignment-so T-gate paper size is suitable for National Standards (CNS) of the fiscal country (2) 1GX297mm) (Please read the notes on the back before filling in this page) Π. The bookkeeping service center and only -T consumer cooperation 乜 卬 鬈 A7 ___________ V. Description of the invention (3) Number range than HD It is simpler, and there is no inisalignment at all. In addition, the insulation layer of the T-type M pole used to generate the spine-drain is

The higher dielectric constant (K ~ 9.0) is higher than Si〇2 (K $ ~ 3.9) or SiNx (K ~ 7.5) used in FID structure, and the distance between α and the closer insulating layer (by The thickness of the gate is determined (approximately 100nm ~ 300nm), which can obtain a higher driving current than the traditional FID structure; meanwhile, the T-gate has the characteristics of low resistance value of aluminum metal, and forms an offset with the use of anodized aluminum. Compared with the gate structure, 1 such as 2 years K. Tanaka et al. In IE: Trans. Electron Dev. Vol. 39, 10, p. 916 reported the advantages of higher on-current.

Stanley »olf reported in Silicon Processing for the VLSIEha Vol. 3, p. 623. Inverse-T open LDD 'iTLDD' is a kind of gate and low-doped wave electrode full overlap (Gate is Overlapped LDD, GOLD). For the application of complex silicon thin film transistor elements, M. Hatano et al., 1997, IE1M 97 Digest, page 523 reported that this structure has the advantages of high-speed operation, large conductive conductance values, and good reliability. The latest manufacturing method of this structure, as described by Stanley ffolf, 'requires two ion implantation techniques and dry etching techniques to form poly-Si sidewalls (poly-Si sidewalls); generally in order to overcome the uneven thickness of polycrystalline silicon Paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) -Product — 0 (Please read the precautions on the back before filling out this page). Packing., Ιτ 5. Description of the invention (4) ~~~ Problem, over-etching is necessary. However, this will cause serious damage to the lower gate insulation layer. Invention and Warehouse 丨 Purpose 5 The present invention provides an anodic oxidation method for forming a self-aligned inverse-T gate LDD structure of a polycrystalline silicon thin film transistor using an anodization method: Wet etching solution (H3po4-based solution) Etch loose alumina (porous AIA), US Patent No. 5,508,209 claims to leave dense alumina (barrier Ai203), and apply different oxygen ionization rates, lower gate The insulating layer does not have the effect of etching at all, and at the same time, the doping action of automatically aligning the low-doped drain electrode can be completed with only one ion implantation. Therefore, compared with the current manufacturing method of the latest gold structure and the compound crystal gate used by the present invention, the present invention has a fully automatic alignment function, simple steps, less damage to the gate insulating layer and A1. 15 characteristics such as low resistance. Tabular description Table 1 Etching rate and selection ratio of loose alumina and dense alumina in pure acetic acid solution at 50 ° C. Explanation of the circle diagram 〇 Figure 1 Anodizing facility wind. The size of this paper is suitable for the Chinese country. A4 · (6 A7 B7 V. Description of the invention (5) 'Figure ^ Schematic diagram of the electric field induced drain 3. Figure 3 Schematic diagram of the auto-aligned offset T-gate structure. Figure 4 A graph of the oxidation current density versus time for anodization of aluminum (AD and group (Ta)).

Electrolyte: 5% (wt) oxalic acid Anodizing voltage: 30V A. Gasification (A1203) B. Oxidation la (Ta203) Kitchen 5 Loose alumina at 5% (wt) oxalic acid solution and constant voltage (30 volts) ) Under the conditions of ο 'the oxidation current density and alumina thickness versus oxidation time plot.

Anodizing voltage = 30V Α · Oxidation Rate ~ 0.98 nm / sec Figure 6 The thickness of Ta205 oxide film grown under different anodizing voltage. 15 Anodizing Time = 20 min A. Slope = 1.462 nm / V Figure 7 Relationship between the applied oxidation voltage and the thickness of dense oxygen ft aluminum in a non-solvent reactive solution. The time of oxidation is 10 minutes, and the solution formula is: [3% (wt) wine 20 lithamine]: [ethylene glycol] = 2: 8 (vol).

^ The paper size applies to the national CNS > A4 size (210X297 mm) I (谙 read the notes on the back before filling out this page) 'Binding A7 B7 Crystal 5. Description of the invention (A • Anode anode conversion rate (Aodmng Ratio) = 1.27nm / Y Figure 8 (a)-(d) Example of process steps for automatic alignment bias n + a_si / A 丨 gate structure process. Figure Ka)-(e) Automatic alignment bias τ An embodiment of the electrical steps of a Ta / M complex crystalline silicon thin film. Fig. 10 (a)-(e) An embodiment of the process steps of the automatic alignment inverted T-type Al / Ta gate selective low-doped drain complex silicon thin film transistor. Description of Drawing Numbers 1 · Power supply (Power ^ jpp ly) 2. Multi-meter (TEK2732) 3. Electrolyte 4. Substrate 5. Anode, tantalum, aluminum, etc. Metal (Ta or A1, ect.) Ι | 6. Cathode (Gold) (Pt) 7. Wiring, aluminum (AI) 8. Main gate (Main-Gate), n + -shaped polycrystalline stone, (n + poly-Si) 9. Sub-Gate, IS (A1) * 10. Insulator (Interlayer Insulator), about 400nm: · _ 11. Source (Source) This paper applies the Chinese National Standard (CNS) ) 8 4 specifications (210X297 male) ^ ^. Binding I line (please read the precautions on the back page first) 丨 Via the Central Bureau of Standards and Technology X. Consumer Cooperatives 8 A7 B7 V. Invention Description 7 () 12. None Drain 13 · Polycrystalline Si active area (poly-Si) (please read the precautions on the back page) 14-Gate Insulator 15. Quartz Substrate 16 Sub-gate Length (Ls) 17. Gate, Al 18. Barrier Al2O3 19. Porous Al2O3 20 . Upper electrode, tantalum or other materials ( Ta or other materials) 21. T-Gate 22. Offset length ((^ 丨 3 € 1; 1611§1: 11) 23.η + Amorphous stone evening (n + a-Si) 24. Buffer Layer ο Printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 2 25. Si Substrate 26. Photoresistance (PR) 27. Anodized Oxide Oxide (Sio2) 28 · Tantalum (Ta) 29. Tantalum oxide (Ta205) 30 · Glass Substrate (Glass Substrate) This paper size applies to Chinese National Standard (CNS) A4 specification (210 X 297 mm) V. Description of the invention (8) 31. Phosphorus ( p) 32.it Low parasitic drain (ifLpD) I Detailed description of the invention The "manufacturing method of the thin film transistor" of the present invention includes the provision of an anodic oxidation method to form a self-oscillating quasi-biased τ coffee pole and an inverted τ type The manufacturing method of the thin-film transistor of the heterodrain polycrystalline spar is changed. By using the two-layer structure of indium and other conductive materials such as rhenium, chromium (Cr), η + amorphous + a-⑷, different anodic oxidation rates and mechanisms in specific electrolytes can simultaneously obtain thicker oxidized inscriptions and Very thin oxide button (TaA) or other oxides. As shown in FIG. 1, the device for the anodic oxidation is configured with the lower layer of the two-layer electrode as _, and the upper layer as other conductive materials and anodized to form a biased T-gate structure; otherwise, the upper and lower electrode materials are arranged. After being reversed, an inverted T-gate structure β can be formed. Below, the relationship between the oxidation current and the rate of tritium, the thickness of the oxide film, and the different growth mechanisms will be described with aluminum (A1) and tantalum (乜) _pole oxidation. Using the concept of this mechanism, the use of aluminum and other materials n + amorphous silicon (n + a-Si) to further demonstrate the manufacture of auto-aligned offset τ-type poles' is used to verify the novelty of the present invention ^ Finally, these two structures are proposed Process steps applied to aluminum gate complex silicon thin film transistors. In the present invention, Kr is 5% (wt), and the technology uses a constant voltage (30 volts) for the anode. This paper is from Conglin (210x297 mm), which is suitable for China National Standards (CNS).

V. Description of the invention (Oxidation. A7 B7 10 thin-film transistor " ..., dynamic alignment bias D-type _ complex crystal silicon} Oxides; and put the prostitutes on the lower electrode, other materials on the upper electrode, and apply anodization to form "automatically aligned offset τ plane pole π structure. Or for the upper electrode, Wei The material is placed on the lower electrode and anodized at the same time to form the "automatically aligned inverted T-shaped interpolar" structure. 15 Pass the spear · central center ^ 挲 and only · τconsuming cooperative β purple 20 where the upper electrode material Can choose doped _ spar eve (n + a_si), tantalum (Ta) 'chromium (cr), sister (Mo), titanium (Ti) or pin alloy (MoTa), molybdenum-town alloy (Mo ~ W). Formed, 1 auto-aligned offset τ gate " structure, the thickness of the upper electrode is 50nm ~ 450, and the thickness of the lower electrode is 50nm ~ 450η. Impurity n + amorphous silicon (n + a-Si), tantalum (Ta), chromium (Cr), molybdenum (Mo), titanium (Ti) or molybdenum-button alloy (Mo-Ta), molybdenum-tungsten alloy ( Mo-W). "Automatic alignment of inverted τ gate" structure, the thickness of the upper electrode is 100 ~ 500, and the thickness of the lower electrode is 10nm ~ 200nm. The above solvent-reactive solution has a concentration of 0%. Standards are applicable to China National Standard (CNS) A4 specifications (2 丨 0X297 mm)

ή -L (Please read the notes on the back before filling this page)

A7 _____ B7 V. Description of the invention ('~ 20% oxalic acid, phosphoric acid, citric acid, sulfuric acid < electrolytic solution and the temperature of the electrolytic solution is between 10 ° C and 50 ° C; anodization is a constant voltage mode, Between 40 and 100 volts; the oxidation time is 10 to 50 minutes. 5 As shown in Figure 4 'is the current density of aluminum (A1) and button (Ta) anodizing versus time circle' anodizing mode The preparation of the β test piece is after the silicon wafer is processed by the ECA standard cleaning process, 'a thick oxide layer (along the 仏 layer) is grown in the high temperature furnace as the bottom layer (5 € 0 nm), and then the aluminum and the anti-plating group are respectively evaporated. Next, put the test piece into the electrolytic solution, connect the anode (A1) or the town (Ta) to the anode, and apply a voltage (30 volts) in a 5% (wt) oxalic acid solution to make A! The oxidation reaction produces thiopine oxide (p0rolls w203), while the button is oxidized to tantalum oxide (Ta205). The oxidation current density is an indicator of the growth rate of the oxide film, and the integral value of the oxidation current density can be used to judge The film is thick and long. As shown in circle 4, after 50 seconds of anodizing, the The la (Ta) phenomenon is engraved, so the current density of the oxide film oxygen group (Ta205) approaches zero, that is, the thickness of the oxide film tantalum oxide approaches a fixed value; this fixed value is self-limiting ) Growth phenomenon; the opposite current density of porous Al2O3 has a minimum value of 20 at ~ 20 seconds, and then the current density increases due to a slight etching phenomenon. This paper scale is in line with Chinese national standards (CNS) A4 specification (210 × 297 mm) (锖 Please read the notes on the back before filling in this page). ·· τ 浐 The central sample of the Ministry of Industry and Consumer Cooperation and Cooperative Seal A7 B7 V. Description of the invention (ii) '一 " --- ~ The thickness of the oxide inscription increases; the increase in current density represents an increase in the oxidation rate, and the increase in thickness of the oxide inscription represents a non-self limiting growth phenomenon. 5 For the loose alumina produced below, the thickness of hafnium oxide can be determined by the time of saponification; Figure 5 shows the condition of the alumina at 5% (wt) oxalic acid mash and a voltage of 30 volts. The oxidation current density And oxidation thickness Degree vs. time. The growth rate under this condition can be found from 1. H) is about 9 · 8 / sec, and after the film is oxidized for 4 minutes, it is about 3400 A. In an oxalic acid solution, for the formation of a anodic oxidation button (Private 205) at a constant voltage, the thickness of the oxide film is determined by the applied voltage. Prolonging the oxidation time does not effectively increase the thickness of the oxide film (self-limiting effect). Figure 5 is the thickness of the oxide film grown in the oxidation group at different anodizing voltages for 20 minutes. From this figure, it can be seen that tantalum oxide can grow by 14.6 A per volt applied voltage, and oxidized for 20 minutes at the same voltage of 30 volts. After that, the thickness of tantalum oxide (TagOs) is about 450 A. 2〇 Therefore, under constant voltage and solvent-reactive solution (solvent-action, the paper size is suitable for China National Standard (CNS) A4 specifications (210X297 mm) 13-Γ (Please read the precautions on the back before filling this page ) Order A7 __B7 printed by Shelley Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs V. Invention Description (12) — ~~ — Solution) For aluminum, use oxidation group 0¾) 5) Self-limiting (limiting) The growth phenomenon can obtain a fixed thickness of the oxidation medium; at the same time, the thickness of the loose alumina can be controlled by changing the oxidation time. Based on this characteristic, materials such as chromium (Cr), n + amorphous silicon (n + a-si) that are not etched by oxalic acid can be used as the upper electrode of the T-gate structure. As shown in FIG. 7, the relationship between the applied oxidation voltage of A1 in a non-solvent reaction solution (non-soivent action solution) and the thickness of a dense oxide (barHer Α1ζ〇3) is shown. The oxidation time was 10 minutes. The formula of the solution was: [3% (wt) tartaric acid]: [ethylene glycol] = 2: 8 (v〇1) The same, dense alumina (barrier Αΐβ3) can also be observed To the self-limiting growth phenomenon, a dense oxidized oxide of 12.7A can be grown per voltage applied, and after oxidizing at 40 volts for 10 minutes, the film thickness is about 550A. The main purpose of the production of dense alumina is to grow a layer of high-quality oxide on the inner layer of the loose alumina near the aluminum; the high-quality oxide inscription refers to better electrical properties and better Chemical resistance. This layer of dense oxide can have better electrical properties in the τ-type closed-pole structure; while in the inverted τ-type gate structure, the dense oxygen inscription "makes a better anti-chemical name engraving layer. In the inverted τ Pure gate acid solution will be used in the fabrication process of the gate-type junction structure to remove the annoying oxidized saurian ^ paper suitable for the Chinese country) from the pole (210χTearly published--m IIII! ';'-— IIII order --- I__Ά '___ II__Γ _____ c L · (Please read the note + ^ on the back before filling out this page) Printed by the Shellfish Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs «. A7 B7 V. Description of the invention (13) Secret oxidation The selectivity is as high as 12.33, as shown in Table 1. The selectivity refers to the ratio of the etching rate of etched loose alumina to the rate of dense alumina. 5 Next, in the embodiment of the present invention, n + amorphous silicon is used. / Aluminum (n + a „Si / Al) double-layer film illustrates the manufacturing process of the auto-aligned offset T-gate structure; Figure 8 (a)-(d) are schematic diagrams of the process steps, and the detailed process contents are as follows: 1. The silicon substrate is processed by a standard cleaning process. Ο 2 · Grow a bottom oxide layer (Si0 2) with a thickness of about 500 nm. 3. The vapor-deposited aluminum (A1) is used as the lower electrode: the thickness of aluminum at 300nm can be determined from 50 ~ 400nm 'by the electrons to be attracted. The thinner the thickness, the stronger the ability to attract. Crystalline silicon (n + a-Si) was used as the upper electrode: 100 nm, using IS slurry enhanced chemical vapor deposition (PECVD), grown at 250t; the structure is shown in Figure 8 (a). Photoresistance, which defines the gate region: n + amorphous silicon (n + a-Si) is defined by reactive ion etching (RIE). Because of the use of a mixed gas of carbon tetrafluoride (CF4) and oxygen (02), the A high selectivity of 20 between silicon and A1. Aluminum is etched by dry etching, so the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -------- -ο 装-(Please read the precautions on the back before filling this page) Order printed by the Central Sample Rate Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, printed A7 B7 — ΤΎΓ \ " " V. Description of the invention () Can effectively control the line Wide. The photoresist is removed after etching; the structure is shown in Figure 8 (b). 6. The first anodization ·· Place the test piece in a 5% (wt) oxalic acid solution, 5 at a constant voltage of 30 In particular, the oxidation time is 30 minutes, so that A1 undergoes an oxidation reaction to form loose alumina and n + amorphous silicon (n + a_Si) is oxidized to silicon dioxide (Si02); therefore, an auto-aligned biased τ-type gate structure is formed. The width of alumina is 400 nm; the structure is shown in Figure 8 (c). 10 7 · Second anodizing: Put the test piece with [3% (wt) amine tartrate] and [ethylene glycol] The electrolytic solution prepared at a 2: 8 (vol) ratio was oxidized for 30 minutes at a specific voltage of 40 volts; the inner layer of the loose alumina was grown into a layer of dense alumina; the structure is shown in Figure 8 (d). 15 Bi-layered thin films of Al / Ta can also be used to fabricate offset T-gate structures as described in step 7 above. Due to the requirement of resistance value, the upper electrode of the biased τ gate structure is preferably metal tantalum (Ta) or chromium (Cr). The inverted τ-type closed-electrode uses an aluminum / tantalum double-layer thin film, which can be achieved by performing anodic oxidation in accordance with the steps described above. This paper size applies Chinese National Standard (CNS) M specification (2 （〇χ297mm > ----- -------------- installation ------ order --- ---_ Jl (锖 Please read the precautions on the back before filling this page) Consumer Co-operation by the Central Bureau of Procurement, Ministry of Economic Affairs, Printed Kl B7 V. Description of the Invention (These two structures are applied to aluminum gate polycrystalline silicon thin film electricity The process steps on the crystal, as shown in Figure 9 (a)-(e), are auto-aligned offset τ-type tantalum / aluminum (Ta / Al) gate complex crystal thin film transistors, such as circle 10 (a )-(e) shows an embodiment of an inverted Td. type | g / 5 tantalum (Al / Ta) gate low-doped drain polycrystalline silicon thin film transistor. First, the T-type tantalum / Example of Ta (Al) gate polycrystalline spar thin film transistor process: 1. First deposit a layer of silicon dioxide (Si02) on the glass substrate as an isolation oxide; thickness of about 100nm ~ 300nm. 2. Amorphous dream (a-Si) film deposition: 50nm ~ 200nm deposited by low pressure chemical vapor deposition (lpqyd) or plasma enhanced chemical vapor deposition (PECVD). Recrystallized into polycrystalline silicon (p〇 ly-Si) thin film: using solid phase crystallization (sol id-phase-crystal 1 ization) Recrystallize β with quasi-is molecular laser annealing. 3. The first photomask: define the aquive element working area (°). 4. Deposit the gate insulating layer and grow silicon dioxide (Si. 2): The use of Qianjian or plasma enhanced chemical vapor deposition (PECVD) to grow the thickness of about 2050 ~ 150nm of the dioxide dioxide. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the notes on the back before filling out this page): Binding η

Description of the invention () 5. The deposition inscription (A1) is used as the lower electrode ... The thickness of aluminum can be printed from 50 ～ 30 ^ 5 5 _m ^ _§ Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 6. Deposit tantalum (Ta) as the upper electrode: the thickness of the button can vary from 35 to 100 nm. 7. The second photoresistor defines the gate area: Tantalum is defined by reactive ion etching (RIE). Because of the use of carbon tetrafluoride (ατ4) and oxygen (〇2), or chlorine (Cy gas), it can be etched in tantalum. High selectivity is obtained between aluminum and aluminum (A1). Aluminum is defined by dry etching, and the structure at this time is shown in Figure 9 (a). 8. First anodization: the test piece is placed in a solvent to react Anodizing in a solution with constant voltage. At a constant voltage of 10 to 50 volts, the oxidation time is 10 to 50 minutes. The thickness of loose alumina is 2000 nm to 2 / zm; tantalum oxide (TaA) The thickness is determined by the voltage, and the applied voltage per volt can grow approximately 20 planes to 80 nm of tantalum oxide with a voltage of 14.6 A. At this time, the structure is shown in Figure 9 (b). 9. Second anodization: Put the test piece in In a non-solvent reaction type solution, anodization is performed at a constant voltage. The constant voltage may be 4 (H00 volts, the oxidation time is 20 to 40 minutes, and the applied voltage per volt may grow to 12.7A of dense alumina, at this time The structure is shown in Figure 9 (c). (Read the precautions on the back before filling in this page) Γ The size of the paper for binding and binding is applicable to China Home Standards (CMS) A4 specifications (210x297) 部 In the middle of the M section |?. ^ · ^ ·. ^ Suppression of combined bamboo · ^ .sr Ji A7 B7 V. Description of the invention (17) 10. After removing the photoresist , And doped the source and electrode with ion cloth value technology: the doping amount is lxlO14 ~ 5xl015 / cm2, the energy is 30keV ~ 50keV; the auto-aligned offset T-gate structure has been formed here, and the structure is蔺 5 shown in 9 (d). 12. Excimer laser activation: Excimer laser is used to activate the polar and source impurities. Deposition of the insulating layer: 300 by chemical vapor deposition (CVD) ~ 500nm thick silicon dioxide (Si〇2). 〇 12. The second photoresist, open the contact hole (Contact hole). 13. Deposition metal: using sputtering or evaporation method, the thickness can be from 300 ~ 500nm. 14. The fourth photoresistor defines the wiring, and the structure at this time is shown in Figure 9 (e). 5 Next, the inverted T-shaped aluminum / neum (Al / Ta) gate low-doped drain complex is described. The manufacturing process of the silicon thin film transistor is described as follows: 1. A layer of silicon dioxide (Si02) is deposited on the glass substrate as a barrier layer with a thickness of about 100 nm to 300 nm. 2. Amorphous silicon (a-Si) film Deposition: Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD) (Please read the precautions on the back before filling this page) * \ s °

This paper is suitable for National Standards (CNS) of Laozhou, Λ4 specifications (210X 297 mm: 9 printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperatives) A7 __B7 V. Description of the invention (18) 50nm ~ 200nm 〇3 · Recrystallization For polycrystalline silicon (poly-Si) thin film: use solid-phase crystallization (sol id-phase'Tcrystal 1 izat ion) or recrystallize with excimer laser 5. 4. The first photomask: define the polycrystalline Working area of silicon (polly-Si) device. 5. Deposit gate insulation layer: grow silicon dioxide (SiO2) with a thickness of about 5 (H50nm.) 6. Deposit tantalum (Ta) as the lower electrode: The thickness of tantalum deposited by the coin bond method can vary from 30 to 150 nm. 7. Deposition of aluminum (A1) as the upper electrode: the thickness of aluminum can range from 25D to 400 ·. 8. The second photoresist, defines the gate Polar region: Tantalum is defined by reactive ion etching. Aluminum is defined by dry etching, and the structure at this time is shown in Figure 10 (a). 9. · First anodization: Put the test piece in a solvent-reactive solution. Anodizing with constant voltage. Oxidation time is 10 ~ 50 minutes. Thickness of loose alumina is 200nm ~ 2ym; tantalum oxide (Ta205) The degree is determined by the voltage, and the voltage applied per volt can grow approximately 14.6 A. The thickness of the 20 oxidizing button is 20 to 80 coffee. At this time, the structure is shown in Figure 10 (b). The paper size applies the Chinese National Standard (CNS) A4. Specifications (210X29 * 7mm) • 11 In j V nf— 1 ^ 1 ^ 1 HI c (Please read the notes on the back before filling this page)-,-— ^ 1 1 ^ 1 ^^^ 1. ^ 1 ^ 1 n ^ i ϋ ^ ί ____ _ _ »,-&. In n-n 'nuu-^^ 1 ^^ 1 ·-u I-20 The Central Industry Bureau of the Ministry of Economic Affairs, the monthly consumer cooperatives A7 _B7 5. Description of the invention (19), shown. 10. Remove the photoresist and perform the second anodic oxidation: put the test piece into a non-solvent reaction type solution to pass the electrical waste for anodizing. The constant voltage can be 5 to 40 ~ 100 The Volt's oxidation time is 20 ~ 40 minutes, and the voltage applied per volt can grow a dense alumina of 12.7A, and the structure at this time is shown in Figure 10 (c). 11. Remove the loose alumina to leave the dense alumina. 12 Ion doping and source doping with ionic layout technique: doping amount is 1X1Q14 ~ 10 5xl015 / cm2, energy ranges from 30keV ~ 80keV 'At this time the structure is shown in Figure 10 (d). 13. Excimer Thunder Shoot live : Molecular laser (Excimer the drain and the source of impurities deposited insulating layer 14 to be activated: depositing a thick oxide 3〇〇nm~500nm stone Xi (Si〇2). 15 15. The third photoresistor: open the contact opening. 16. Deposited aluminum metal: thickness can range from 300 to 500 nm. 17. The fourth photoresistor defines the wiring. At this time, the structure is shown as circle 10 (e). The size of this paper is applicable to Zhongguguoge (210X297 mm) ~ '~~ " ~~~ 21 (Please read the note f on the back before filling out this page), π Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs Printing. A 7 B7 V. Description of the invention (20) Table 1 Film thickness of the etching solution (A) Etching time (sec) Etching rate (A / sec) H3PO4 @ 50lC Dense alumina ||||| _: ' ; :: |; 丨 | 3 Negotiation IIIII 3416 37 Optional 12.33 (Please read the precautions on the back before filling out this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)

Claims (1)

h — A method of forming an auto-aligned offset τ-type polarized polycrystalline silicon thin film transistor by anodic oxidation, which uses different oxidation rates of Ming and other conductive materials in a solvent-reactive solution to simultaneously obtain different thicknesses of oxidation. Putting aluminum on the lower electrode and other conductive materials on the upper electrode, and applying anodizing at the same time, can form an auto-aligned offset T-gate structure. 2 · —A method for automatically aligning an inverted 7-type gate with a low doped drain complex crystal dream thin dielectric transistor by anodization, which uses different oxidation rates of Ming and other conductive materials in a solvent-reactive solution. At the same time, oxides of different thicknesses are obtained; aluminum is placed on the upper electrode, other conductive materials are placed on the lower electrode, and anodic oxidation is performed at the same time, which can form an auto-aligned inverted T gate structure. 3. The process method according to item 1 or 2 of the scope of the patent application, wherein the solvent-reactive solution is an electrolytic solution of oxalic acid, phosphonic acid, citric acid, and sulfuric acid having a concentration between 0.01% and 20%, and The temperature of the electrolyte is between 10 degrees Celsius and 50 degrees Celsius; the anodic oxygen is also in a constant electric dust mode between ΗΗ00 volts; and the oxidation time is 10 to 50 minutes. The size of this paper is Chinese National Liangfeng (CNS) A4 specification (210X297 mm) Printed on the A8 B8 C8 --------- D8 in the Consumers' Cooperatives of the Central Procurement Bureau of the Ministry of Lithuania --- 4 The method as described in item j of the patent application, where the upper electrode and material are: doped amorphous bite (n + a-Si), group (Ta), chromium (Cr), key (Mo) Chin (Ti) or Pin-Zhao alloys), molybdenum ~ mineral alloy (Mo-W) «5 · The method described in the second item of the patent application, wherein the lower electrode material is: doped Amorphous silicon (n + a_Si), tantalum (Ta), chromium (Cr), molybdenum (Mo), titanium (Ti) or molybdenum button alloy (M〇_Ta), molybdenum-tungsten alloy (Mo-W ). 6. According to the method described in the item of the scope of the patent application, the thickness of the upper electrode is 50nnH50nm, and the thickness of the lower electrode is 50nm ~ 450nm. 7. The method as described in item 2 of the scope of patent application, the upper electrode is deposited to have a thickness of 100 nm to 50 nm, and the thickness of the lower f electrode is 10 nnh, 2Q0 nm. The size of this paper is in Chinese National Standard (CNS) A4 (210X297mm) 24 (Please read the note on the back before reading this page) r $