A 7 B7____ 發明説明（） 5-1發明領域： 本發明係有關於一種形成隔離區域的方法’特別 是有關於一種改良區域氧化隔離法（L〇C〇S)之方法。 5-2發明背景: 當數十萬以上之元件被製造於單—晶片內時，隔 離方法變成當今金屬氧化半導體（metal-oxide-semiconductor, MOS) 及雙載子 （bipolar) 積體電路的一個 重要技術。不妥當的隔離會導致漏電流，而數十萬個元件 之漏電流的總和將會使整個晶片的功率消耗變得非常可 觀。另外，不妥當的隔離還會連帶產生閉鎖（latch up)現 象，以致於暫時或永久的損害到電路的功能。此外，不妥 當的隔離將會降低電路抗雜訊的能力，且產生電位移 (voltage shift)或串擾訊號（crosstalk)。 於互補式金屬氧化半導體（complementary MOS， CMOS)的製程技術中，不同型的元件之間更需要一妥當 的隔離方法以確保電路的正常功能。在金屬氧化半導體的 技術中，元件的隔離通常是在主動元件之間形成隔離區域 來達成。此隔離區域的形成一般是先使用和源、汲極電性 相反的離子植入，以形成通道阻絕（channel stop)層，再 於其上長一厚氧化層之場氧化區（field oxide, FOX”此 通道阻絕層和場氧化區可以使得隔離區的起始電壓 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐_) #裝丨丨 Ί.- (請先¾讀背面之注意事項再填寫本頁) -----訂-----r--Λ 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 A7 B7___ ~~ —----------------— 五、發明説明（） (threshold voltage)高於相鄰之主動兀件區.，以避免隔離 區的電性導通。 區域氧化隔離法（local oxidation of silicon, LOCOS)是一種用於積體電路製程上形成主動元件之間 橫向隔離區域的傳統作法。在此隔離方法中’形成氮化矽 層以避免其底下之矽表面被氧化。再者’氮化矽層之氧化 速率較矽小很多。然而，如果直接以氮化矽層來遮蓋砍表 面，則在高溫之氧化環境下，將會產生應力並造成晶體缺 陷。因此，於傳統作法當中，另外形成一薄（大約100-500 埃）之墊氧化層於矽表面及氮化矽層之間，作爲緩衝層以 妤緩上層應力，以減少晶體缺陷。 不幸的是，區域氧化隔離法存在有一些缺點，例 如氧化時基底的矽會向兩側氮化矽層下方擴散而形成鳥 喙效應（bird‘s beak effect)，且所植入之離子會向主動元 件區域產生旁側離子擴散效應。這些效應會使得主動元件 區域面積減少，也使得元件的通道寬度減小。當積體電路 之元件尺寸不斷的縮小時，將會使得情況更嚴重，並會提 高元件的起始電壓及降低電流的驅動能力。鳥椽效應可以 藉由減少墊氧化層厚度來減輕。但是，愈薄墊氧化層卻會 造成較嚴重的晶體缺陷。因此，必須控制墊氧化層及氮化 矽層之厚度，以達到形成隔離區之最佳化。 除了鳥喙效應以外，當積體電路之元件規格不斷 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -------裝！I-'.^1—丨"”~~2 -·*· (請先閲讀背面之注意事項再填寫本頁) A7 _^B7_^____五、發明説明（） 的縮小，尤其是當隔離區域之間隔小於一微米時，會使得 隔離氧化區域之厚度變薄，一般稱此爲場氧化薄化效應 (field oxide thinning effect)，此場氧化薄化效應對於次 微米元件的影響更大。上述鳥喙效應、場氧化薄化效應及 晶體缺陷等問題之討論，請參考A. Bryant等人提出之 "'Characteristics of CMOS device isolation for the VLSI age/\ p.67 1 -674, IEDM, 1 994。 經 濟 部 智 慧 財 產 局 員 工 消 合 作 社 印 製 傳統隔離技術中存在有許多方法用以改良區域 氧化隔離法，例如氮化物覆蓋區域氧化隔離法（NCL)，請 參閱 J_ R. Pfiester 等人所提出之 “Nitride-Clad LOCOS Isolation for 0.25 m CMOS" VLSI Tech. Symp. Dig., 1 993,頁，1 39- 140。.上述之氮化物覆蓋區域氧化隔離法 (NCL)會在場氧化區之邊緣造成一些缺陷。另有一種類似 區域氧化隔離法之緩衝多晶矽區域氧化隔離法（PBL)，其 作法是使用一墊氧化層於矽基板上，再於其上沈積多晶矽 層及氮化矽層作爲離子植入及氧化時的遮罩，請參閱J. Nag'el 等人所提出之 “S'tres's-induced Void Formation in Interlevel Polysilicon. Films during Poly buffered Local Oxidation of Silicon” J. Electrochem. Soc.，vol..140，199.3, 頁23 56-2359。緩衝多晶矽區域氧化隔離法（PBL)的缺點 之一係爲其所形成的孔洞（voids或pits)問題。其他傳統隔離技術，例如界面密封區域 (sealed-interface local oxidation, S.ILO)之氧北法，其 (諳先閱讀背面之注意事項再填寫本頁) 一裝_ 訂 -----^ 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 A7 B7____ 五、發明説明（） 係形成氮化砍蓋層/氧化層/氮化砂層之三層結構於基底 之隔離區上。此法可以減少鳥喙效應，但是會產生較多晶 體應力、晶體缺陷及漏電流。此外，還有一種掩埋氧化層 法（buried oxide)是使用鋁罩幕以蝕刻成矽溝槽 (groove)，再除去以電漿法沈積之氧化矽層，此法可以減 少鳥喙效應，但是其製程過於繁複。 β-3發明目的及槪述： 鑒於上述之發明背景中，傳統的區域氧化隔離法所造 成的諸多缺點，本發明提供一種形成區域氧化隔離區之方 法，用以改善鳥喙效應、場氧化薄化效應及晶體缺陷。在 本發明實施例中，首先形成一墊氧化層於半導體基板上， 並形成一氮化矽層於墊氧化層上。接著，蝕刻部分氮化矽 層及氮化砂層，因而露出部分基板，再橫向除去部份塾氧 化層，以形成凹陷於氮化矽層及基板之間。形成一氮摻雜 層於氧化遮罩層,、墊氧化層及基板上，因而包圍住凹陷， 其中氮摻雜層之抗氧化程度大於墊氧化層。最後，非等向 性蝕刻氮摻雜層以形成側壁間隙於氮化矽層之側壁，及氧 化基板以形成一場隔離區域於基板上，其中氮摻雜層之摻 雜氮原子會擴散至基板內。 δ-4圖式簡單說明： 第一圖顯示半導體基底之剖面圖，其上具有氧化 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)A 7 B7____ Description of the invention () 5-1 Field of the invention: The present invention relates to a method for forming an isolation region ', and particularly to a method for improving an area oxidation isolation method (LOCOS). 5-2 Background of the Invention: When hundreds of thousands of components are manufactured in a single wafer, the isolation method becomes one of today's metal-oxide-semiconductor (MOS) and bipolar integrated circuit Important technology. Improper isolation will cause leakage current, and the sum of the leakage currents of hundreds of thousands of components will make the power consumption of the entire chip very considerable. In addition, improper isolation can also cause a latch-up phenomenon, which can temporarily or permanently damage the function of the circuit. In addition, improper isolation will reduce the ability of the circuit to resist noise and cause voltage shift or crosstalk. In complementary MOS (CMOS) process technology, a proper isolation method is needed between different types of components to ensure the normal function of the circuit. In metal oxide semiconductor technology, the isolation of components is usually achieved by forming isolation regions between active components. This isolation region is generally formed by first implanting ions with opposite electrical source and drain electrical properties to form a channel stop layer, and then growing a field oxide (FOX) layer with a thick oxide layer thereon. "This channel barrier layer and field oxidation zone can make the initial voltage of the isolation zone. The paper size is applicable to China National Standard (CNS) A4 specifications (210X297 mm_) # 装 丨 丨 Ί.- (Please read the note on the back first (Please fill in this page for matters) ----- Order ----- r--Λ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7___ ~~ ------ ------------— V. Description of the invention () (threshold voltage) is higher than the adjacent active element area to avoid electrical conduction in the isolation area. Local oxidation isolation method of silicon (LOCOS) is a traditional method used to form lateral isolation areas between active components in integrated circuit manufacturing processes. In this isolation method, 'a silicon nitride layer is formed to prevent the silicon surface underneath from being oxidized. Moreover' The silicon nitride layer has a much lower oxidation rate than silicon. However, if A silicon nitride layer is used to cover the cut surface. In a high-temperature oxidizing environment, stress and crystal defects will occur. Therefore, in the traditional method, a thin (about 100-500 Angstrom) pad oxide layer is formed on the Between the silicon surface and the silicon nitride layer, it acts as a buffer layer to mitigate the upper layer stress to reduce crystal defects. Unfortunately, there are some disadvantages to the regional oxidation isolation method, such as the substrate silicon will be silicon nitride on both sides during oxidation. Diffusion under the layer forms the bird's beak effect, and the implanted ions will cause side ion diffusion effects to the active device area. These effects will reduce the area of the active device area and also make the channel width of the device Decrease. When the size of the integrated circuit components is continuously reduced, the situation will be worsened, and the initial voltage of the components will be increased, and the driving ability of the current will be reduced. The birdfowl effect can be reduced by reducing the thickness of the pad oxide layer. However, the thinner the pad oxide layer will cause more serious crystal defects. Therefore, the thickness of the pad oxide layer and the silicon nitride layer must be controlled to achieve the shape The optimization of the isolation zone. In addition to the bird's beak effect, when the component specifications of the integrated circuit are constantly adjusted, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ------- install! I- '. ^ 1— 丨 " ”~~ 2-· * · (Please read the precautions on the back before filling in this page) A7 _ ^ B7 _ ^ ____ V. Reduction of the description of the invention (), especially when the isolation area When the interval is less than one micron, the thickness of the isolation oxidation region becomes thinner, which is generally called a field oxide thinning effect. This field oxidation thinning effect has a greater impact on sub-micron devices. For the discussion of the aforementioned beak effect, field oxide thinning effect, and crystal defects, please refer to "Characteristics of CMOS device isolation for the VLSI age / \ p.67 1 -674, IEDM, proposed by A. Bryant et al." 1 994. There are many methods to improve the traditional isolation technology in the printing of traditional isolation technology by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, such as the nitride-covered area oxidation isolation method (NCL). Nitride-Clad LOCOS Isolation for 0.25 m CMOS " VLSI Tech. Symp. Dig., 1 993, pp. 1 39-140. The above-mentioned nitride-covered area oxidation isolation method (NCL) will cause some at the edges of the field oxidation area. Defects. Another buffered polycrystalline silicon area oxidation isolation (PBL) method similar to the area oxidation isolation method uses a pad of oxide layer on a silicon substrate, and then deposits a polycrystalline silicon layer and a silicon nitride layer thereon as ion implantation. And mask during oxidation, please refer to "S'tres's-induced Void Formation in Interlevel Polysilicon. Films during Poly buffered Local Oxidation of Silicon" proposed by J. Nag'el et al. J. Electrochem. Soc., Vol .. 140, 199.3, pages 23 56-2359. One of the disadvantages of the buffered polysilicon area oxidation isolation (PBL) method is the problem of voids or pits formed by it. Traditional isolation technology, such as the oxygen-north method of sealed-interface local oxidation (S.ILO), (谙 Please read the precautions on the back before filling this page) Standards are applicable to China National Standard (CNS) A4 (210X297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7____ 5. Description of the invention () Forming nitrided capping layer / oxide layer / nitrided sand layer The layer structure is on the isolation area of the substrate. This method can reduce the bird's beak effect, but it will generate more crystal stress, crystal defects and leakage current. In addition, a buried oxide method uses an aluminum mask to Etching into silicon grooves, and then removing the silicon oxide layer deposited by the plasma method, this method can reduce the bird's beak effect, but the process is too complicated. Β-3 Purpose and description of the invention: In view of the above background of the invention Due to the many disadvantages caused by the traditional regional oxidation isolation method, the present invention provides a method for forming a regional oxidation isolation region to improve the bird's beak effect, field oxidation thinning effect, and crystal defects. Ming embodiment, a pad oxide layer is first formed on the semiconductor substrate, and forming a silicon nitride layer on the pad oxide layer. Next, a part of the silicon nitride layer and the nitrided sand layer are etched, thereby exposing part of the substrate, and then removing part of the hafnium oxide layer laterally to form a recess between the silicon nitride layer and the substrate. A nitrogen-doped layer is formed on the oxide mask layer, the pad oxide layer, and the substrate, thereby surrounding the depression, wherein the nitrogen-doped layer has a higher degree of oxidation resistance than the pad oxide layer. Finally, the nitrogen-doped layer is anisotropically etched to form a sidewall gap between the silicon nitride layer and the substrate is oxidized to form a field isolation region on the substrate. The doped nitrogen atoms of the nitrogen-doped layer will diffuse into the substrate. . δ-4 diagram brief description: The first figure shows a cross-sectional view of a semiconductor substrate with an oxidized paper on it. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). (Please read the precautions on the back before filling in this. page)
A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 矽層及氮化矽層。 第二圖之剖面圖顯示以光阻層爲遮罩，除去部份 氮化矽層及氧化矽層後之結構。 第三圖之剖面圖顯示以等向性蝕刻方法，除去部 份墊氧化層以形成底切。 第四圖顯示形成一氮摻雜抗氧化層。 第五圖顯示形成氮摻雜側壁間隙於氮化矽層之 側壁上。 第六圖顯示形成場氧化區域。 第七圖顯示除去氮摻雜側壁間隙、氮化矽層及氧 化矽層所形成之剖面結構。 第八圖顯示以高濃度植入以形成雙井區。 第九圖顯示形成金屬氧化半導體場效應電晶體 於基底上。 5-5發明詳細說明： 第一圖顯示半導體基底1 0之剖面圖。首先以傳 統爐管，於溫度約1 000 °C之下，形成厚約50-350埃之氧 化砍層1 2。接著，以低壓化學氣相沈_積法（L P C V D)形成 氮化矽層1 4於氧化矽層1 2上。在本實施例中，氮化矽 層14之厚度大約爲1000-3000埃。上述之氧化矽層12 通常稱之爲墊氧化層，係用以妤緩氮化矽層1 4對於半導 體基底1 〇之應力。氮化矽層1 4則是用以作爲氧化遮罩， 用以避免氧化步驟時，氮化矽層1 4底下之矽表面受到氧 本紙張尺度適用中國國家標準（CNS ) Μ規格（210Χ'·297公釐） (諳先聞讀背面之注意事項再填寫本頁) ©裝 --訂 ___；---*}冰-----_----- A7 B7 五、發明説明（） 化影響。接著，形成一具有主動區圖樣（pattern)之光阻層 8於氮化矽層1 4上面’並以傳統之微影技術以形成主動 區域於氮化矽層1 4內。 第二圖之剖面圖顯示以光阻層爲遮罩，以非等向 性蝕刻方法（例如乾蝕刻法）除去部份氮化矽層1 4及氧化 矽層1 2後形成之結構。 於第三圖中，以等向性蝕刻方法，除去部份墊氧 化層12以形成底切或凹陷（undercut)於氮化矽層14及半 導體基板10之間。底切之橫向深度大約介於1〇〇至1〇〇〇 埃之間。墊氧化層1 2之底切係以濕蝕刻液（例如稀釋氟化 氫溶液）所完成，此稀釋氟化氫溶液會蝕刻氧化矽材質， 但不會影響到矽及氮化矽材質。此步驟主要係爲了在場氧 化時減少鳥喙效應。 於第四圖中，形成一氮摻雜抗氧化層1 6 (例如氮+ 摻雜多晶矽層或非晶矽（Amorphous Silicon)層）於氧化 砂層12及氮化矽層14上，其厚度大約50-5 00埃，並包 圍住氧化矽層1 2。在本實施例中，係以低壓化學氣相沈 積法（LPCVD)形成氮摻雜抗氧化層18。其中，氮摻雜抗 氧化層1 6之抗氧化程度較氧化矽層12大，且此抗氧化 程度係由氮摻雜濃度所控制。再者，氮摻雜抗氧化層1 6 之壓力較氮化矽層1 4來得小。値得注意的是，氮摻雜以 外的原子也可以作爲抗氧化層1 6 .之摻雜，只要是其抗氧 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 X》97公釐） 衣 (請先閲讀背面之注意事項再填寫本頁) \ V I -g- nn as …· n 、言..5 .·" 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 化程度大於純氧化物，且/或其壓力小於氮化矽即可。 接著，以傳統回蝕刻方法（例如反應氧蝕刻法， RIE)蝕去氮摻雜抗氧化層16之一部份，因而形成氮摻雜 側壁間隙16A於氮化矽層14之側壁上，如第五圖所示。 以傳統爐管並於溫度大約爲950-1 150°C之環境 下，形成厚約3000-10000埃之場氧化區域18,如第六 圖所示。藉由傳統之區域氧化隔離法（LOCOS)及本發明中 利用氮摻雜側壁間隙1 6A之技術，因而形成大幅降低鳥 喙效應（bird's beak effect)之場氧化區域18。其中，.氮 摻雜多晶矽層或非晶矽之氧化速率遠小於非摻雜多晶 砂。再者，於場氧化期間，位於氮摻雜側壁間隙16A之 氮原子會擴散至基底1 〇中場氧化區1 8之邊緣，因而更 加改善了鳥喙效應及晶體缺陷。 (諳先κ讀背面之注意事項再填寫本盲 Ο 裝. 訂— 經 濟 部 智 慧 財 產 局 資 工 消 費 合 作 社 印 製 於形成場氧化區域18之後，以傳統蝕刻方法除 去氮摻雜側壁間隙16A'氮化矽層14及氧化矽層12，因 而ΐ形成第七圖所示之剖面結構。接著，以高濃度（大約爲 1〇12-1014)離子植入以形成雙井區20，如第八圖所示。 最後’以傳統方法形成金屬氧化半導體場效應電晶體22 於基底10上，如第九圖所示。 以上所述僅爲本發明之較佳實施例而已，並非用 &限定本發明之申請專利範圍；凡其它未脫離本發明所揭 本紙張尺度適.用中國國家標隼（CNS ) Μ規格Ul〇xi97公釐） s —^—n ml— β 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 示之精神下所完成之等效改變或修飾，均應包含在下述之 申請專利範圍內。 9 (請先閱讀背面之注意事項再填寫本頁)A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Silicon layer and silicon nitride layer. The cross-sectional view of the second figure shows the structure after using a photoresist layer as a mask and removing a part of the silicon nitride layer and the silicon oxide layer. The cross-sectional view of the third figure shows that an isotropic etching method is used to remove a part of the pad oxide layer to form an undercut. The fourth figure shows the formation of a nitrogen-doped antioxidant layer. The fifth figure shows the formation of nitrogen-doped sidewall gaps on the sidewalls of the silicon nitride layer. The sixth figure shows the formation of field oxidation regions. The seventh figure shows the cross-sectional structure formed by removing the nitrogen-doped sidewall gap, the silicon nitride layer, and the silicon oxide layer. The eighth figure shows implantation at a high concentration to form a dual well region. The ninth figure shows the formation of a metal oxide semiconductor field effect transistor on a substrate. 5-5 Detailed Description of the Invention: The first figure shows a cross-sectional view of a semiconductor substrate 10. First, the traditional furnace tube is formed at a temperature of about 1 000 ° C to form an oxide cutting layer with a thickness of about 50-350 angstroms 12. Next, a low-pressure chemical vapor deposition (LPC V D) method is used to form a silicon nitride layer 14 on the silicon oxide layer 12. In this embodiment, the thickness of the silicon nitride layer 14 is about 1000-3000 Angstroms. The above-mentioned silicon oxide layer 12 is generally referred to as a pad oxide layer, and is used to relieve the stress of the silicon nitride layer 14 on the semiconductor substrate 10. The silicon nitride layer 14 is used as an oxidation mask to prevent the silicon surface under the silicon nitride layer 14 from being subjected to oxygen during the oxidation step. The paper size is in accordance with the Chinese National Standard (CNS) M specification (210 × '·· 297 mm) (谙 First read the notes on the back and then fill out this page) © Binding--Booking ___; --- *} Bing -----_----- A7 B7 V. Description of the invention ( ) Impact. Next, a photoresist layer 8 having an active area pattern is formed on the silicon nitride layer 14 'and a conventional photolithography technique is used to form an active area in the silicon nitride layer 14. The cross-sectional view of the second figure shows a structure formed by removing a part of the silicon nitride layer 14 and the silicon oxide layer 12 with an anisotropic etching method (such as a dry etching method) using the photoresist layer as a mask. In the third figure, a part of the pad oxide layer 12 is removed by an isotropic etching method to form an undercut or undercut between the silicon nitride layer 14 and the semiconductor substrate 10. The undercut has a lateral depth of approximately 100 to 10,000 Angstroms. The undercut of the pad oxide layer 12 is completed with a wet etching solution (such as a diluted hydrogen fluoride solution). This diluted hydrogen fluoride solution will etch the silicon oxide material, but it will not affect the silicon and silicon nitride materials. This step is mainly to reduce the beak effect during field oxidation. In the fourth figure, a nitrogen-doped anti-oxidation layer 16 (such as a nitrogen + doped polycrystalline silicon layer or an amorphous silicon layer) is formed on the sand oxide layer 12 and the silicon nitride layer 14 with a thickness of about 50 -5 00 angstroms, and surrounds the silicon oxide layer 1 2. In this embodiment, the nitrogen-doped anti-oxidation layer 18 is formed by a low pressure chemical vapor deposition (LPCVD) method. Among them, the degree of oxidation resistance of the nitrogen-doped anti-oxidation layer 16 is greater than that of the silicon oxide layer 12, and the degree of anti-oxidation is controlled by the nitrogen doping concentration. Furthermore, the pressure of the nitrogen-doped anti-oxidation layer 16 is lower than that of the silicon nitride layer 14. It should be noted that atoms other than nitrogen can also be used as the anti-oxidation layer 16. As long as it is anti-oxidant, the paper size applies the Chinese National Standard (CNS) A4 specification (2 丨 0 X >> 97) Li) Clothing (please read the precautions on the back before filling this page) \ VI -g- nn as… · n 、 .. 5. · &Quot; Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Note that the degree of chemical conversion is greater than pure oxide, and / or its pressure is less than that of silicon nitride. Next, a portion of the nitrogen-doped anti-oxidation layer 16 is etched away by a conventional etch-back method (such as reactive oxygen etching, RIE), thereby forming a nitrogen-doped sidewall gap 16A on the sidewall of the silicon nitride layer 14, as described in the first paragraph. Five pictures are shown. A conventional furnace tube is used to form a field oxidation region 18 with a thickness of about 3000-10000 angstroms in an environment with a temperature of about 950-1150 ° C, as shown in the sixth figure. By the traditional LOCOS method and the technology of 16A using nitrogen-doped sidewall gaps in the present invention, a field oxide region 18 that substantially reduces the bird's beak effect is formed. Among them, the nitrogen-doped polycrystalline silicon layer or amorphous silicon has a much lower oxidation rate than the undoped polycrystalline sand. Furthermore, during field oxidation, nitrogen atoms located in the nitrogen-doped sidewall gap 16A will diffuse to the edges of the field oxidation region 18 in the substrate 10, thereby further improving the bird's beak effect and crystal defects. (谙 Please read the notes on the back before filling in the blank. Ordering—Printed after the field oxide region 18 was formed by the Intellectual Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the traditional etching method was used to remove the nitrogen-doped sidewall gap 16A 'nitrogen. The siliconized layer 14 and the silicon oxide layer 12 form a cross-sectional structure as shown in Fig. 7. Then, a high-concentration (approximately 1012-1014) ion is implanted to form a double-well region 20, as shown in Fig. 8. Finally, the metal oxide semiconductor field effect transistor 22 is formed on the substrate 10 by a conventional method, as shown in FIG. 9. The above description is only a preferred embodiment of the present invention, and the invention is not limited by & The scope of the patent application; all other papers that do not depart from the present invention are of suitable paper size. Use Chinese National Standard (CNS) M specifications Ulxi 97mm) s — ^ —n ml — β Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economy Printing A7 B7 5. Equivalent changes or modifications made under the spirit of the invention description () should be included in the scope of patent application described below. 9 (Please read the notes on the back before filling this page)
本紙張尺度適用中國國家標準（CNS ) Μ規格（210X597公釐）This paper size applies to China National Standard (CNS) M specifications (210X597 mm)