A7 B7 五、發明説明（ I明領· 本發明與一種電性裝置有關，特别是—種 晶片，且提供該晶片與^^载 置。 ％成畦氐逦结炙電性測試裝 隨著半導體工業朝著超大型積體電路以 =的各：元件的尺寸也不斷縮小，而如此密集的電2 縮小的疋件往往也造成半導體製程變得更加複雜。一般而 ^當晶圓（wafer)上之積體電路完成製作後，將晶圓進 仃为釗，再加以包裝成構裝（package)元件的型式。然而 在上述過程中，所形成之晶片尚需經歷各種不同的測試， 以確保最後製作完成的構裝元件可符合所需之功能规 範，且具備足夠要求之良率。 在故障性分析技術中對晶片進行分析（failure analyS1S)時’往往先對晶片進行封裝（Package)，再將該 構装晶片置放於合適的測試承接器（T]EST SOCKET)上以 進灯電性連結。然後在該構裝晶片電性導通的狀態下，使 用影像感應器（Image Sensor)對該構裝晶片之上表面進 行偵測°當中當該構裝晶片中積體電路具有如斷路或短路 爭缺Po時往往會在該缺陷處造成額外的發熱。是以在使 用影像感應器進行偵測時，可經由該構裝晶片上表面之紅 木紙乐尺度说川屮因[’"^'標/?((，阳）八4说招（2丨0'/ 297公楚 (請先閎讀背面之注意事項再填寫本頁) 裝. A7 B7 五、發明説明（ 外線影像，得知位於積體電路中 崎干疋疋件是否發生故障而造 成缺陷。 ] 然而如同上述，隨著半導體製程進展至超大型積體 電路，高積禁度及較小尺寸元件之設計要求使得位於 上金屬層之數量及密度與曰俱增。例如在目前的半導體製 程中，往往需要使用3~4層的金 ,y^ J &屬層，才能使繁複且精細 之元件彼此間產生適當的電性遙 性連接。但是對於此種具有多 重金屬層之構裝晶片而言，L 1 便用上述之影像感應器，將無 法有效的偵測到位於該構装晶珐 * _ a 衣明片上展部金屬層之電路及 元件缺陷。 發明目的及概 本發明 < 目的在提供一種晶片測試分析装置，用以 直接測試該晶片之正面及背面。 本發明I另一目的在提供一種晶片測試裝置，以便 對晶片進行故障性分析。 本發明艾再一目的在提供—種晶片測試装置，闱以 測試各種尺寸之晶片。 本發明之再一目的在提供—種測試晶片之方法，以 對晶片進行故障性分析測試。 本紙银尺及诚州中闽阀家#彳（（’NS ) Λ4规格（210Χ297公潑） (請先閲讀背面之注意事項再填寫本頁) 裝— ! I : 11訂 ir 輕"•部中"tt卑局π-τ消抡合竹社印 A 7 . B7 五、發明説明（） 本發明之再一目的在提供一種測試方法，直接對該 晶片之正面與背面進行偵測。 本發明提供了一種晶片之測試分析裝置，可直接對 晶片的正面及背面進行故障性分析測試。其中該測試裝置 包含了 一基板，該基板具有一開口槽與複數個貫穿孔，分 别位於基板之中央區域與週圍區域，貫穿基板之上表面及 下表面。該開口槽用以放置晶片，而該複數個貫穿孔之内 壁上具有導電性材料，以作爲電性連結之用。此外，複數 個焊接墊位於該基板之表面，且鄰接於該開口槽，其中該 複數個焊接墊分别連接於該複數個貫穿孔，以提供該晶片 作爲電性連接之用。 另外該測試裝置包含一承載板貼附於該基板之下 表面，覆蓋該開口槽，其中該承載板之上表面具有黏著材 料，用以固定晶片。該測試裝置更包括連接該晶片與該焊 接墊之導線，用以提供該晶片作爲電性連結之用。該測試 裝置更包含一密封層，覆蓋於該晶片與導線之上，用以保 護該晶片與導線。 此外，本發明亦提供一種測試晶片之方法，用以對 晶片進行故障性分析。該方法至少包含下列步骤：首先， 連結晶片於一測試裝置上，其中該測試裝置具有一開口槽 與複數個貫穿孔，且該開口槽用以放置晶片，而該貫穿孔 之内壁上具有導電性材料，分别與該晶片茗生電性耦合。 本紙張尺度鸿州中國囤家標彳（（'NS ) ΛΊ現格（210X 297公f ) (請先閲讀背而之汰意事項再填寫本頁) 分衣-I-- 訂 A7 五、發明説明（ 另外，該測試裝置尚包括一承載板，貼附於該測試裝置下 表面，以覆蓋該開口槽，且用以固定、承載該晶片。接著， 放置，測試裝置於—測試機台上，其中該晶片之第一表面 朝向該測試機台，且該測試機台經由該複數.個貫穿孔上之 導電材料，與該晶片發生電性導通，以傳迭電子信號。然 後，使用偵測儀器對該晶片之第二表面進行偵測以便進行 ，生分析。在對該晶片之第二表面進行偵測後，可將測 減裝置顚倒放置於該測試機台上，使該晶片之第二表面朝 向孩測試機台，再使用债測儀器對該晶片之第一表面進行 偵測。 單说明： ”藉由以下詳細之描述結合所附圖示，將可輕易的了 解上述内容及此項發明之諸多優點，其中： (請先閲讀背面之注意事項再填寫本莨) ^ 装- 訂 截面圖 第一圖所顯示爲根據本發明提供之絶緣基板其 —結構之. 第二圖所顯示爲根據本發明將所測試之晶片連結至該 基板上其結構之截面圖。 第三圖所顯示爲根據本發明在該羞皇及晶片上形成密 封物質之步驟V — 第四圖改-觀示爲使用本發明所提供之測試裝置對該晶 片之下表面進行故障性測試之步驟。 ί五圖所顯示爲使用本發明所提供…之測試裝置對該晶-片之上表面進行故障性測試之步骤。 本紙乐尺度i.Sj用中國囤家;m ( (，NS ) Λ4现松（2丨〇x 297公漦） 五 發明説明（ Α7 Β7 經 部 中 央 準 第六A圖所顯示爲根據本發明所形 表面之俯視圖。 則試装置其上 第ί六B圖所翁示备根據本 表面之俯視圖。 I見^成〈測試裝置其下 細説昍 根據本發明所提供之測試裝置，可針 片進杆ϊ··#·ιϊή75ΠΓ*τ« 野所製造的时 後，可將二片二:广拿分析測試。待測試程序完成 提件二i;置Γ 試裝置分離。使用本發明所 各種不但可大幅縮短測試時間，更可適用於 尺寸（曰曰片。關於本發明之詳細説明如下所 、.、首先請參照第一圖，該圖所顯示爲根據本發明所形 成之絶緣基板100,用以提供晶片暫時固定於其上，並方 便對該晶片進行分析。在—較佳實施例中，該绝緣基板 wo之材料可使用一般的印刷電路板（print circuit board, PCB)，此外也可選擇適合的陶瓷材料，如氧化 銘、珍酸鹽、氮化矽等等；或適當的塑膠材料，如環氧樹 脂（FR-4)、BT 材料（Cyanate ester)、聚醯胺材料、Aramid 環氧、與陶瓷蕊材料（Ceracom)等等。該基板包括了一開 口槽區.域（drilled open a.rea) 1 1 0與複數個貫穿孔 (through hole) 120。其中該開口槽區域11〇位於該基板 1 0 0之中央區域，而複數個貫穿孔1 2 0則，分别位於該基板 (請先閲讀背面_之注意事項再填寫本頁)A7 B7 V. Description of the invention (I) The invention relates to an electrical device, in particular, a wafer, and provides the wafer and the mounting.% Cheng Junjun electrogenicity test equipment The industry is moving towards very large integrated circuits: the size of components is also shrinking, and such dense electrical components are often making semiconductor processes more complicated. Generally, wafers After the fabrication of the integrated circuit is completed, the wafer is converted into a package, and then packaged into a package component type. However, in the above process, the formed wafer needs to undergo various tests to ensure the final The fabricated component can meet the required functional specifications and have sufficient required yield. When analyzing the wafer in failure analysis technology (failure analyS1S), the wafer is often packaged first, and then packaged. The structured chip is placed on a suitable test socket (T) EST SOCKET to be electrically connected to the lamp. Then, in the state where the structured chip is electrically conductive, an image sensor is used During the detection of the upper surface of the structured chip, when the integrated circuit in the structured chip has, for example, an open circuit or a short circuit for Po, it often causes additional heat to the defect. Therefore, when using an image sensor for detection According to the mahogany paper music scale on the top surface of the structured wafer, Chuan Liyin said ['" ^' 标 /? ((， 阳) 八四 说 招 （2 丨 0 '/ 297 公 楚 (Please read the back first Note: Please fill in this page again.) Installation. A7 B7 V. Description of the invention (External line image, I know whether the sintered parts in the integrated circuit have malfunctioned and caused defects.] However, as mentioned above, as the semiconductor process progresses to super The design requirements of large integrated circuits, high product densities, and smaller size components make the number and density of upper metal layers increase. For example, in current semiconductor processes, 3 to 4 layers of gold are often used. ^ J & belongs to the layer, in order to make the complex and delicate components have proper electrical remote connection with each other. However, for such a structured wafer with multiple metal layers, L 1 uses the above-mentioned image sensor, Will not be able to detect Defects in the circuits and components of the metal layer of the exhibition part on the structured crystal enamel * _ a garment are detected. OBJECT AND SUMMARY OF THE INVENTION The object of the present invention is to provide a wafer test analysis device for directly testing the front and back of the wafer. Another object of the present invention is to provide a wafer testing device for failure analysis of the wafer. Another object of the present invention is to provide a wafer testing device for testing wafers of various sizes. Another object of the present invention We are providing a method for testing wafers for failure analysis and testing of the wafers. This paper silver ruler and Chengzhou Zhongmin Valve House # 彳 (('NS) Λ4 specifications (210 × 297)) (Please read the precautions on the back first (Fill in this page again.) Packing!! I: 11th order ir light " • Ministry " tt low bureau π-τ elimination 抡 合 竹 社 印 A 7. B7 5. Description of the invention () Another object of the present invention is to Provide a test method to directly detect the front and back of the chip. The invention provides a test and analysis device for a wafer, which can directly perform a failure analysis test on the front and back of the wafer. The test device includes a substrate. The substrate has an open slot and a plurality of through holes, which are respectively located in a central region and a peripheral region of the substrate, and penetrate the upper surface and the lower surface of the substrate. The opening groove is used for placing a chip, and an inner wall of the plurality of through holes is provided with a conductive material for electrical connection. In addition, a plurality of solder pads are located on the surface of the substrate and adjacent to the open slot, wherein the plurality of solder pads are respectively connected to the plurality of through holes to provide the chip for electrical connection. In addition, the test device includes a carrier board attached to the lower surface of the substrate and covering the open slot, wherein the upper surface of the carrier board has an adhesive material for fixing the wafer. The test device further includes a wire connecting the chip and the bonding pad to provide the chip as an electrical connection. The test device further includes a sealing layer covering the chip and the wires for protecting the chip and the wires. In addition, the present invention also provides a method for testing a wafer for failure analysis of the wafer. The method includes at least the following steps: First, the wafer is connected to a test device, wherein the test device has an open slot and a plurality of through holes, and the open slot is used for placing the wafer, and the inner wall of the through hole is conductive. The materials are electrically coupled to the wafer. The standard of this paper is Hongzhou China Storehouse Mark (('NS) ΛΊ is present (210X 297 male f) (please read the intent matters before filling out this page) Division-I-- Order A7 V. Invention Explanation (In addition, the test device also includes a carrier board attached to the lower surface of the test device to cover the open slot and used to fix and carry the wafer. Then, place the test device on a test machine, The first surface of the wafer faces the test machine, and the test machine is electrically connected to the wafer through the conductive material on the plurality of through holes to transfer electronic signals. Then, a detection instrument is used. The second surface of the wafer is detected for analysis, and after the second surface of the wafer is detected, the measuring and reducing device can be placed upside down on the test machine to make the second surface of the wafer The surface is facing the testing machine, and then the first surface of the chip is detected by the debt measuring instrument. Single note: "By the following detailed description combined with the attached diagram, the above content and this invention can be easily understood. Many advantages, its ： (Please read the precautions on the back before filling in this note) ^ Binding-ordering cross-section view The first picture shows the insulating substrate provided by the present invention and its structure. The second picture shows the test according to the present invention. A cross-sectional view of the structure of the wafer attached to the substrate. The third diagram shows the step V of forming a sealing material on the shame and the wafer according to the present invention. The fourth diagram is modified to show the view provided by using the present invention. The test device performs a fault test step on the lower surface of the wafer. The figure 5 shows the steps of performing a fault test on the upper surface of the wafer by using the test device provided by the present invention. The paper scale i. Sj uses Chinese storehouses; m ((, NS) Λ4 is now loose (2 丨 0x 297 cm). 5 Description of the invention (A7 B7 Figure 6A in the center of the warp section shows the top view of the surface shaped according to the present invention. The test device shown in Figure 6B above is prepared according to the top view of this surface. I see ^ Cheng <The test device is detailed below. According to the test device provided by the present invention, the needle can be inserted into the rod ϊ ·· # · Ιϊή75ΠΓ * τ «Made by Ye After that, two pieces of two: Canna analysis and test can be completed. The test procedure completes the second piece of i; the test device is separated. Using the invention can not only greatly reduce the test time, but also can be applied to the size (say The detailed description of the present invention is as follows. First, please refer to the first figure, which shows an insulating substrate 100 formed according to the present invention, which is used to temporarily fix a wafer thereon, and to facilitate the wafer. Analysis. In a preferred embodiment, the material of the insulating substrate wo can be a general printed circuit board (PCB), in addition, suitable ceramic materials can be selected, such as oxidized oxide, rare acid salt, Silicon nitride, etc .; or appropriate plastic materials, such as epoxy resin (FR-4), BT material (Cyanate ester), polyamide material, Aramid epoxy, and ceramic materials (Ceracom) and so on. The substrate includes a drilled open a.rea 1 1 0 and a plurality of through holes 120. The open slot area 11 is located in the central area of the substrate 100, and a plurality of through holes 1 2 0 are respectively located on the substrate (please read the precautions on the back _ before filling this page)
訂 線 消 合 本紙張尺度滴./ΐΐ^Γρί!家標彳((’NS ) /\44見格（210X297公漦〉 ΑΊ Β7 五、發明説明（ 100足週園區域，且環繞該開口槽區域丄i〇。此外 σ槽:域110貫穿該基板100之上表面八及下表面8，用 放置鬲片於其中。至於該複數個貫穿孔12〇亦貫穿該基板 100(上表面A與下表面B，且於該複數個貫穿孔12〇之内 壁上，具有導電性物質，以作爲電性連結之用。在一較佳 實施例中，位於該複數個貫穿孔12〇内壁上之導電性物 質，可使用電鍍程序（electroplating process)將適當的 金屬材料，例如鋼、錫、鉛等等，電鍍於該複數個貫穿孔 120的内壁上。另外’在該複數個貫穿孔12〇與該基板1〇〇 上表面A與下表面B之接合處，即該複數個貫穿孔12〇之 兩端開口，則形成複數個焊墊（pad) i 2 5，以提供該基板 100與後續製程之測試機台產生電性連結作用。 接著在該基板100的邊緣部份形成工具帶（tool bar) 1 30，以作爲該基板之特定記號，並用以在後績製程 及測試程序中，精確的固定及對準該基板]_ 〇 〇，而方便生 產、組裝、及測試程序之進行。再於該基板100之下表面 B黏貼一承載板（carrier) 1_4〇，用以覆蓋該開口槽區域 1 1 〇，並承載進行測試之晶片。値得注意的是該承載板 1 4 0之材料需滿足測試儀器之要求，以便在後續測試程序 中，可以透過該承載板1 60偵測到該晶片之缺陷所在。在 一較佳實施例中，該承載板160可選擇玻璃材料加以形 成。其中該承载板140之上表面具有黏著物質（adhesive material)，用以貼附於基板100之下表.面B;J·可用以固 本紙張尺度垧川中®囤家棍呤（（'NS ) Λ4規掊（210X 297公釐〉 (請先閎讀背面之注意事項再填寫本頁)The binding line is combined with the paper scale. / Ϊ́ΐ ^ Γρί! 家 标 彳 (('NS) / \ 44 见 格 （210X297 公 漦> ΑΊ Β7) V. Description of the invention (100 feet around the park area, and surrounding the open slot Area 丄 i〇. In addition, the σ groove: the domain 110 penetrates the upper surface 8 and the lower surface 8 of the substrate 100, and a cymbal is placed therein. As for the plurality of through holes 120, the substrate 100 (the upper surface A and the lower surface) Surface B, and a conductive substance is provided on the inner walls of the plurality of through holes 120 for electrical connection. In a preferred embodiment, the conductive material is located on the inner walls of the plurality of through holes 120. For the substance, an appropriate metal material such as steel, tin, lead, etc. can be electroplated on the inner wall of the plurality of through holes 120 using an electroplating process. In addition, the plurality of through holes 120 and the substrate are electroplated. The joint between the upper surface A and the lower surface B, that is, the two ends of the plurality of through-holes 120 are opened, then a plurality of pads i 2 5 are formed to provide the substrate 100 and subsequent process tests. The machine generates an electrical connection effect. The edge part forms a tool bar 1 30 as a specific mark of the substrate, and is used to accurately fix and align the substrate in subsequent performance and testing procedures] _ 〇〇, which is convenient for production and assembly And the test procedure is carried out. A carrier 1_40 is pasted on the lower surface B of the substrate 100 to cover the open slot area 1 1 0 and carry the test wafer. It should be noted that The material of the carrier plate 140 needs to meet the requirements of the testing instrument, so that in the subsequent test procedure, the defect of the wafer can be detected through the carrier plate 160. In a preferred embodiment, the carrier plate 160 can A glass material is selected for formation. The upper surface of the carrier plate 140 has an adhesive material for attaching to the lower surface of the substrate 100. Surface B; J. Can be used as a solid paper scale. (('NS) Λ4 Regulations (210X 297mm) (Please read the notes on the back before filling out this page)
W -裝- 訂 A7 '^_ B7 -—-— I —--—----~一-— 五、發明説明（） _定所承.載之晶片。以一較佳實施例而言，可使用環氧樹脂 (Ep〇xy Resin)作爲該黏著材料。然後，形成複數個烊接 墊（评46 13〇11(1^11邑6]*)150於該基板100之上表面八，且該 複數個焊接墊150鄰接於該開口槽區域ι10。其中該複數 個焊接墊1 50分别對應於該複數個貫穿孔1 20，且分别電 性連結於該複數個貫穿孔1 2 0。如此，则可得到如第—圖 中所顯示之測試裝置101。 請參照.第二圖’將晶片1 6 0放置於該承载板1 4 〇之 上表面。如同上述，由於該承载板140之上表面具有黏著 物質，是以可使晶片160適當的固定於承載板140上。隨 後使用導線（wire) 155連接該晶片160與焊接墊150，以 作爲電性連結之用》在一較佳實施例中，該導..線可使用 金、鋁等金屬線，以焊接之方式連接該晶片1 6〇與焊接墊 150。接著請參照第三.圖，形成密.封層（encapsuiati〇n layer) 1 70於該測試裝置i χ之上，以覆蓋並密封該晶片 160與導線155。其中該密封層17〇之功用除了提供該導 線1 55適當的保護與固定外，更可用以避免該晶片1 6〇之 表面支到其匕/亏染微粒附著、或在生產.、測試製程中受到 不奂外力的損壞。至於該密封層170之材料則可選擇一般 的封膠材料，如塗膠、球型表面封膠、鑄模膠材、及環氧 樹脂等等。在一較佳實施例中，可使用高分子聚合物 (Polymer)來作爲密封層17〇之材料。 (請先閲讀背面之注意事項再填寫本頁) #!丨 裝.W-equipment-order A7 '^ _ B7----I------------5. Description of the invention () _ contract of the wafer. In a preferred embodiment, epoxy resin (Epoxy Resin) can be used as the adhesive material. Then, a plurality of bonding pads (e.g., 46, 13, 11 (1 ^ 11) 6) * are formed on the upper surface of the substrate 100, and the plurality of soldering pads 150 are adjacent to the open slot area ι10. Among them The plurality of soldering pads 150 respectively correspond to the plurality of through-holes 120 and are electrically connected to the plurality of through-holes 120 respectively. In this way, the test device 101 shown in the first figure can be obtained. Please Referring to the second figure, 'the wafer 160 is placed on the upper surface of the carrier plate 140. As mentioned above, since the upper surface of the carrier plate 140 has an adhesive substance, the wafer 160 can be appropriately fixed on the carrier plate. 140. Then, a wire 155 is used to connect the chip 160 and the solder pad 150 for electrical connection. In a preferred embodiment, the wire can be a metal wire such as gold, aluminum, etc. The wafer is connected to the soldering pad 160 and the bonding pad 150 by soldering. Then, referring to the third figure, an encapsuiation layer 1 70 is formed on the test device i χ to cover and seal the wafer. 160 and wire 155. The function of the sealing layer 17 is in addition to providing the wire 1 5 5 In addition to proper protection and fixing, it can also be used to prevent the surface of the wafer from supporting the dagger / defective particles or being damaged by external forces during the production and testing processes. As for the sealing layer 170, The material can be selected from general sealing materials, such as rubber coating, spherical surface sealant, molding compound, epoxy resin, etc. In a preferred embodiment, a polymer can be used as the polymer. Material of sealing layer 17〇 (Please read the precautions on the back before filling this page) #! 丨 装.
Ja \線 五 發明説明( A7 B7 Mπ τ- ή.An 然後，請參照第四圖，將測試装置1 〇 1之上表面A 朝下放置於一固定架（fixture)2〇〇上。其中該固定架200 上具有複數枝測試探針（testirig pr〇be)210,其中每一枝 探針210皆具有與其相對應之貫穿孔120，且該探針210 經由焊墊125與貫穿孔12〇相接，用以支撐該測試裝置 1 0 1，且提供位於測試裝置〗〇 i上之晶片1 6 〇作爲電性連 結t用。其中該複數枝探針2 i 〇可經由測試機台傳送直流 電（DC P〇wer)，以便對晶片進行故障測試（failure analysis)。如同上述，在該測試裝置ι〇1之表面b的上 方’使用一紅外線影像感應器（Image sens〇r)22〇，以便 對該晶片160進行測試。由於在該晶片16〇的積體電路 中，當兀件及電路有缺陷，如斷路、短路等等，會產生發 熱現象。是以使用熱影像感應器22〇，可有效自該晶片 160背面（back-side)偵測到熱斑點（h〇t sp〇t)，而得知該 積體電路之缺陷位置。接著，請參照第五圖，將該測試裝 置1 0 1反轉，亦即將該測試裝置工〇 i之表面B朝下放置於 該固足架2 0 0义探針2 1 〇上。此時，該測試裝置工〇 i之表 面A朝向影像感應器22Q。進行測試時可有效自該晶片 I60之正面（front-side)彳貞測積體電路之缺陷。如此，則 儘管該晶片1 60上具有多重金屬層，然而由於根據本發明 所提供之測試裝置，可分别對該晶片16〇之正面及背面進 行偵測，是以可有效的進行該晶片i 6〇之故障分析。 叫參…、第^ A圖，孩圖所顯示爲根據本發明所提供 請 先 閲， 讀 背 ιδ 意 事 再^9 本 頁 裝 訂 :線 本紙张尺度诵川屮闽搜家標彳（（'NS )八4現柢（210Χ297^1~ Α7 Β7 五、發明説明（） 之測試裝置。其中在一較佳實施例中，更可在開口槽區域 1 10與焊接墊150間、該測試裝置1〇1表面a之上，形成電源環（Power ring)6 10以及接地環（Ground ring)620 ,以 降低電性聯結之複雜性。其中該接地環620鄰接於該開口 槽區域110與電源環61〇，以作爲該晶片160上元件及電 路接地之用；而該電源環6 1 0則位於該複數個焊接塾1 5 〇 與接地環6 2 0之間，可劃分爲至少一個區段，以提供至少 一組電壓。例如在第六A圖中，該電源環610可區分爲四 個區段’是以可同時提供四種不同電壓，提供該晶片1 6〇 上欲進行連結之元件及電路選擇。當該晶片16〇上之元件 或電路所需電壓相同於該四種電壓中之任一種時，可就近 連結於該電源環610中具有同樣電壓之區段。由此可降低 進行導線155連結時之複雜性與因難度。至於第六B圖所 顯示則爲該測試裝置1 0 1之表面B其結構。其中該開口槽 區域1 10被承截板140所覆蓋。 本發明所提供之測試裝置相對於傳統技術，具有極 多的好處。首先，藉著使用本發明所提供之測試裝置，可 直接對積體電路晶片之正面（front_side)與背面（back_ side)進行故障分析，由此可避免因爲多重金屬層數目的 增加，所導致因缺陷產生的熱斑點（h〇t sp〇t)，難以爲影 像感應器所偵測。並且，對於更精密之高積集度晶片而 言，使用本發明所提供之測試裝置，可以有效的债測到極 細微π件4發熱現象，因此可以協助預先嘀沃可能發生故 (锖先閱讀背面之注意事項再填寫本頁) ©! 裝· -β Λ ----：-------- B7 —__ 五、發明説明（） 障、且操作壽命較低之晶片。.並且，由於在該 之開口槽區域其尺寸略大於晶片，是以對各種 而言，：皆可輕易的使用本發明所提供之測試 試。不需隨著晶片尺寸改變，設計规格不同之 置，因此可節省製程所耗費之成本。另外，藉 烊墊之貫穿孔設計與測試機台之探針進行電七 易的進行晶片測試，是以相較於傳統技術，可 的對大量的晶片進行標準功能測試 functional, test)’從而.降低產.品自生產線 間’減低時間成__.本。 本發明雖以一較佳實例闡明如上，然其 疋本發明精神與發明實體，僅止於此一實施例 本發明中，所列舉之實施例爲使用該測試较 杆。然而對熟悉此領域技藝者，當可運用該測 式測試程序中，是以在不脱離本發明之精神與 之修改，均應包含在下述之申請專利範圍内。 11 測試裝置中 尺寸之晶片 裝置進行測 測試承載裝 著使用具有 t連結，可輕 直接且迅速 (prototype 至市場之時 並非用以限 爾。例如在 置於故障分 試裝置於各 範圍内所作Ja \ 线 五 发明 说明 (A7 B7 Mπ τ-ή.An Then, referring to the fourth figure, place the upper surface A of the testing device 1 〇 down on a fixture 200. Among them The fixing frame 200 has a plurality of test probes 210 (testirig pr0be), each of which has a corresponding through-hole 120, and the probe 210 is connected to the through-hole 12 through a solder pad 125. To support the test device 101, and to provide a chip 160 on the test device 〇i as an electrical connection t. The plurality of probes 2 i 〇 can transmit direct current (DC Power) to perform failure analysis on the wafer. As described above, an infrared image sensor (Image Sensor) 22o is used above the surface b of the test device ι〇1 to The test is performed on the chip 160. Because in the integrated circuit of the chip 160, when components and circuits are defective, such as open circuits, short circuits, etc., heat generation will occur. The thermal image sensor 22 is used, which can effectively Back-side of the chip 160 detects heat Point (h〇t sp〇t) to know the defect location of the integrated circuit. Then, referring to the fifth figure, reverse the test device 101, that is, the surface B of the test device 〇i It is placed face down on the pedestal 2 0 0 probe 2 10. At this time, the surface A of the test device is oriented toward the image sensor 22Q. It can be effectively from the front of the chip I60 (front -side) The defect of the integrated circuit is measured. Thus, although the wafer 160 has multiple metal layers, the front and back of the wafer 160 can be detected separately due to the test device provided by the present invention. The test is to effectively analyze the failure of the chip i 60. It is called the reference ..., Figure ^ A, the picture shown by the present invention is provided according to the present invention. Binding: Scroll, paper, scale, Sichuan, Fujian, Soujia standard (('NS) 8 4 current (210 × 297 ^ 1 ~ Α7 Β7) 5. Test device for invention description (). Among them, in a preferred embodiment, more It can be between the open slot area 110 and the solder pad 150, on the surface a of the test device 101, A power ring 6 10 and a ground ring 620 are formed to reduce the complexity of the electrical connection. The ground ring 620 is adjacent to the open slot area 110 and the power ring 61 and serves as the chip 160. The upper component and the circuit are used for grounding; and the power ring 6 10 is located between the plurality of welding rings 150 and the ground ring 6 2 0 and can be divided into at least one section to provide at least one set of voltage. For example, in the sixth diagram A, the power ring 610 can be divided into four sections, so as to provide four different voltages at the same time, and provide components and circuits to be connected on the chip 160. When the voltage required by the component or circuit on the chip 160 is the same as any one of the four voltages, it can be connected to the section of the power ring 610 with the same voltage nearby. This can reduce the complexity and difficulty of connecting the wires 155. As for the sixth diagram B, the structure of the surface B of the test device 101 is shown. The open slot area 1 10 is covered by the supporting plate 140. Compared with the conventional technology, the test device provided by the present invention has many advantages. First, by using the test device provided by the present invention, the front side and back side of the integrated circuit wafer can be directly analyzed for failure, thereby avoiding the cause of the increase in the number of multiple metal layers. Hot spots (hot spots) generated by defects are difficult to detect by image sensors. In addition, for more precise high-integration wafers, using the test device provided by the present invention can effectively detect the extremely small π-piece 4 heating phenomenon, so it can assist in pre-empting possible failures (read first) Note on the back, please fill in this page again) ©! Installation · -β Λ ----: -------- B7 —__ 5. Description of the invention () A chip with a low operating life. In addition, since the size of the open slot area is slightly larger than that of the wafer, the test provided by the present invention can be easily used for various purposes. There is no need to change the design specifications with the size of the chip, so the cost of the process can be saved. In addition, by using the through-hole design of the pad and the probes of the testing machine to perform the electric chip test, compared to the traditional technology, a large number of chips can be subjected to standard functional tests (functional, test) '. Reduce the production of products from the production line 'reducing time into __. This. Although the present invention is explained as above with a preferred example, the spirit and the inventive substance of the present invention are limited to this embodiment. In the present invention, the listed embodiments are compared using this test. However, for those skilled in this field, when using this test procedure, the modifications without departing from the spirit of the present invention should be included in the scope of patent application described below. 11 The size of the test device in the test device. The test load is equipped with a t-connection, which can be light and direct (prototype is not limited to the market when it is prototyped. For example, when it is placed in a fault test device in each range.