TW379404B - Manufacturing method of shallow trench isolation - Google Patents
Manufacturing method of shallow trench isolation Download PDFInfo
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- TW379404B TW379404B TW086120045A TW86120045A TW379404B TW 379404 B TW379404 B TW 379404B TW 086120045 A TW086120045 A TW 086120045A TW 86120045 A TW86120045 A TW 86120045A TW 379404 B TW379404 B TW 379404B
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- 238000002955 isolation Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000008021 deposition Effects 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- 239000004576 sand Substances 0.000 claims description 2
- 230000002079 cooperative effect Effects 0.000 claims 2
- 229910052770 Uranium Inorganic materials 0.000 claims 1
- 229910052797 bismuth Inorganic materials 0.000 claims 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims 1
- 239000003245 coal Substances 0.000 claims 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 claims 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 235000015170 shellfish Nutrition 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
- H01L21/31612—Deposition of SiO2 on a silicon body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Description
1958TWF.DOC/005 A7 B7 _ 五、發明説明(ί ) ~~ 本發明是有關於一種積體電路中元件隔離之製造方 法’且特別是有關於一種可形成高縫隙塡補能力與避免頸 結(Kink)現象發生之淺槽溝隔離(STI)之製造方法。 淺槽溝隔離之技術已經廣泛的應用在目前積體電路之 製程上,利用非等向性蝕刻在基底中挖出一條槽溝,再塡 « 入絕緣材料,即可達到元件隔離之效果。 習知淺槽溝隔離的製造方法中,一般均以常壓化學氣 相沈積法(APCVD)或是次麾化學氣相沈積法(sACVD)來塡 補縫隙中的絕緣材料或是以高密度電漿(HDP)來進行沈 積。其方法如下:請參照第1A-1D圖,爲習知淺槽溝隔離 的製造方法。 首先請參照第1A圖,提供一基底1〇,在基底1〇表面 形成一氮化矽層12。接著定義氮化矽層12與基底10的圖 案’形成~槽溝14。 接著,請參照第1B圖,在氮化矽層12表面形成一絕 緣層16 ’並使絕緣層16塡滿槽溝丨4,例如使用常壓化學 氣^目沈積法或是次壓化學氣相沈積法形成氧化層或者是以 高密度電漿沈積氧化層。由於以常壓化學氣相沈積法或是 次壓化學氣相沈積法形成氧化層,其氧化層之密度不夠緊 密’因此需再經過高溫步驟,使絕緣層16密化,但經過 密化後之絕緣層16,其密度還是無法達到以熱氧化所形成 之氧化層之密度。同樣的,由高密度電漿沈積形成之絕緣 層16,其密度也是無法達到以熱氧化所形成之氧化層之密 度。 4 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) —-----------裝------訂------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 1 958TWF.DOC/005 A7 1 958TWF.DOC/005 A7 經濟部中央標隼局員工消費合作杜印製 B7 _ 五、發明説明( > ) 〜^^ 然後,請參照第1C圖,以化學機械硏磨法去除表 之絕緣層16,並以氮化矽層12爲硏磨終點。隨後,'將® 化矽層12去除,使部分絕緣層16凸出於基底1〇表面i氮 最後,請參照第1D圖,以等向性蝕刻,例如是^ 之HF溶液,去除凸出於基底10表面之絕緣層16, ^ 等向性蝕刻會對凸出於基底10表面絕緣層16之< <上方與側 面均會進行相同蝕刻速率之蝕刻,因此,會在淺; 造成頸結18,使元件的特件隆低。 上述習知之方法,無論使用常壓化學氣相沈_ 壓化學氣相沈積法或者是以高密度電漿沈積絕緣胃丨6 ^ # 無法避免最後在淺槽溝兩側造成頸結18的現象 以高密度電漿沈積絕緣層16時,其中Ar氣體爲触刻 ’ 用,因此當Ar氣體的流速越大,雖縫隙塡補能力&佳乍 也會容易造成削角(Clipping)的現象,而破壞元件; 流速小之Ar氣體,雖可避免削角的現象,也會 匕徵囚縫隙塡 補能力差,而在淺槽溝隔離中形成孔洞(Void)。 因此本發明的主要目的就是在提供一種淺槽___ 製造方法,利用多重步驟(Multi-step)之高密度電駿沈^之 可避免淺槽溝隔離中頸結現象之發生。 $ * 本發明的另一目的就是在提供一種淺槽溝隔離之製& 方法’利用多重步驟之高密度電漿沈積,可得到縫隙塡^ 能力較佳的淺槽溝隔離,且不會因削角的產生而破壞元 件。 本發明一種淺槽溝隔離之製造方法,包括: 5 n —ί — 製 I I 訂 I I 線 i請先閱讀背面之注意事項再填寫本頁j 本紙張尺度適用中國國家標準(CNS ) μ規格(210X297公釐) 1 958TWF.DOC/005 A7 1 958TWF.DOC/005 A7 經濟部中央標準局員工消費合作社印裝 五、發明説明(3 ) 提烘一基底,在該基底表面形成一罩幕層; 定義該罩幕層與該基底之圖案,在該基底中形成一槽 溝; 以高密度電漿沈積,並使用低Ar流速與低RF偏壓功 率,在該罩幕層與該槽溝表面形成一第一絕緣層; 以高密度電漿沈積,並使用离Ar流速與高RF偏壓功 率,在該第一絕緣層表面形成一第二絕緣層並使該第二絕 緣層塡滿該槽溝; 去除該第一絕緣層與該第二絕緣層,並以該罩幕層爲 終點; 去除該罩幕層,造成部分該第一絕緣層與部分該第二 絕緣層凸出該基底表面;以及 以等向性蝕刻去除凸出該基底表面之該第一絕緣層與 該第二絕緣層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特'舉一較佳實施例,並配合所附圖式,作詳 細說明如下= 圖式之簡單說明: 第1A-1D圖爲習知一種淺槽溝隔離之製造剖面流程 圖;以及 第2A-2E圖是依照本發明一較佳實施例,一種淺槽溝 隔離之製造剖面流程圖。 圖式中標示之簡單說明: 10, 20 基底 ----F-----裝-----^----------線 (請先閱讀背面之注意事項再填寫本頁) 1 958TWF.DOC/005 A7 B7 五、發明説明(f) 12 氮化矽層 14, 24 槽溝 16, 26, 28 絕緣層 18 頸結 22 罩幕層 27 凸出部分 實施例 經濟部中央標準局貝工消費合作社印裝 請參照第2A-2E圖,爲依照本發明一較佳實施例,— 種淺槽溝隔離之製造剖面流程圖。首先請參照第2A圖, 提供一基底20,在基底20表面形成一罩幕層22,例如是 一氮化砂層。接著定義罩幕層22與基底20之圖案,在基 底20中形成一槽溝24。 接著,請參照第2B圖,利用高密度電漿沈積,並使 用低Ar流谏與低RF偏壓功率,可在罩幕層22與槽溝24 表面形成一高密度之絕緣層26,並在絕緣層26靠近槽溝 24中間部分形成突出部分(Overhang)27。絕緣層26例如爲 一高密度之二氧化矽層,其相對於10:1 HF溶液之蝕刻速 率與熱氧化法形成之氧化層相同,約爲300-350 A/min。 之後,請參照第2C圖,再利用高密度電漿沈積,並 使用高Ar流速與高RF偏壓功率,可在絕緣層26表面形 成一絕緣層28,並使絕緣層28塡滿槽溝24,絕緣層28例 如爲一低密度之二氧化矽層,其相對於10:1 HF溶液之蝕 刻速率約爲430-470 A/min。由於使用高Ar流速與高RF 偏壓功率,可使絕緣層28的溝塡能力增加,以避免孔洞 7 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公楚) - ----------裝-----^---------^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印裝 1 958TWF.DOC/005 A7 B7 _ 五、發明説明(f) 發生,並可將絕緣層26的凸出部分27削去。 然後,請參照第2D圖,去除表面之絕緣層26與28 ’ 例如是使用化學機械硏磨法,並以罩幕層22爲硏磨終點。 隨後,將罩幕層22去除,例如使用濕蝕刻,使部分絕緣 層26與28凸出於基底20表面。 最後,請參照第2E圖,以等向性蝕刻,例如是1〇:1 之HF溶液,去除凸出於基底20表面之絕緣層26與28 ’ 由於絕緣層26的蝕刻速率小於絕緣層28的蝕刻速率,使 絕緣層26是雖受到上方與側面之蝕刻,其所侵蝕之絕緣 層26與僅受到上方之蝕刻之絕緣層28相當。如此一來可 使淺槽溝隔離形成平整之表面,且不會有頸結現象之發 生。 利用本發明之最大特點就是利用槽溝中兩層蝕刻速率 不同之絕緣層,利用外層絕緣層蝕刻速率較小,內層之蝕 刻速率較大,_當淮行等向性蝕刻時,可使內外兩層蝕刻的 厚度相當,造成平整無頸結現象之淺槽溝隔離表面。此外, 在內層絕緣層使用高Ar流速與高RF偏壓功率之高密度電 漿沈積,可得到溝塡能力良好之絕緣層。 雖然本明已以一較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍內,當可作各種之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。
K 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁) .裝·
*1T
Claims (1)
1 958TWF.DOC/005 A8 B8 C8 D8 六、申請專利範圍 1. 一種淺槽溝隔離之製造方法,包括: 提供一基底,在該基底表面形成一罩幕層; 定義該罩幕層與該基底之圖案,在該基底中形成一槽 溝; 以高密度電漿沈積,並使用低Ar流速與低RF偏壓功 率,在該罩幕層與該槽溝表面形成一第一絕緣層; 以高密度電漿沈積,並使用高Ar流速與高RF偏壓功 率,在該第一絕緣層表面形成一第二絕緣層並使該第二絕 緣層塡滿該槽溝; 去除該第一絕緣層輿該第二絕緣層,並以該罩幕層爲 終點; 去除該罩幕層,造成部分該第一絕緣層與部分該第二 絕緣層凸出該基底表面;以及 以等向性蝕刻去除凸出該基底表面之該第一絕緣層與 該第二絕緣層。 2. 如申請專利範圍第1項所述之製造方法,其中該罩 幕層爲一氮化矽層。 3. 如申請專利範圍第1項所述之製造方法,其中該第 一絕緣層爲一高密度之二氧化矽層。 4. 如申請專利範圍第1項所述之製造方法,其中該第 二絕緣層爲一低密度之二氧化矽層。 5. 如申請專利範圍第1項所述之製造方法,其中去除 該第一絕緣層與該第二絕緣層之方法爲化學機械硏磨法。 6. 如申請專利範圍第1項所述之製造方法,其中該等 9 ^ 裝 訂 線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標率局員工消費合作社印裝 太紙張尺唐ΐΛ用伞圃困裳垅?fe f CNS ) A4说格(210X297公嫠) 〇 / V ^ .,糊 5|’TWF.DOC/0 0 5 A8 B8 C8 D8 經濟部中央標準局員工消費合作社印策 申請專利範圍 向性蝕刻係使用10:1之HF溶液。 7. 如申請專利範圍第6項所述之製造方法,其中該第 一氧化層對該10:1之HF溶液之蝕刻速率約爲300-350 A/min。 8. 如申請專利範圍第6項所述之製造方法,其中該第 二氧化層對該10:1之HF溶液之蝕刻速率約爲430-470 A/min。 9. 一種淺槽溝隔離之製造方法,包括: 提供一基底,在該基底表面形成一罩幕層; 定義該罩幕層與該基底之圖案,在該基底中形成一槽 溝; 在該罩幕層與該槽溝表面形成一第一絕緣層; 在該第一絕緣層表面形成一第二絕緣層並使該第二絕 緣層塡滿該槽溝,該第二絕緣層之蝕刻速率大於該第一絕 緣層之鈾刻速率; 去除該第一絕緣層與該第二絕緣層,並以該罩幕層爲 終點; 去除該罩幕層,造成部分該第一絕緣層與部分該第二 絕緣層凸出該基底表面;以及 以等向性蝕刻去除凸出該基底表面之該第一絕緣層與 該第二絕緣層。 10. 如申請專利範圍第9項所述之製造方法,其中該罩 幕層爲一氮化砂層。 11. 如申請專利範圍第9項所述之製造方法,其中該第 1 二(l·— I- n 1· m n In Hr----- Γ II - -I I 条 、νφ 崩 (請先閲讀背面之注意事項再填寫本頁) 太板误尺飱捕珀Φ困困定块?fe f rNS、A4说格f 210X297公螫) * ^..I 958JWF.DOC/005 A8 B8 C8 D8 申請專利範圍 一絕緣層係以高密度電漿沈積,並使用低Ar流速與低RF 偏壓功率形成之高密度二氧化矽層。 12. 如申請專利範圍第9項所述之製造方法,其中該第 二絕緣層係以高密度電漿沈積,並使用高Ar流速與高RF 偏壓功率形成之低密度二氧化矽層。 13. 如申請專利範圍第9項所述之製造方法,其中去除 該第一絕緣層與該第二絕緣層之方法爲化學機械硏磨法。 14. 如申請專利範圍第9項所述之製造方法,其中該等 向性蝕刻係使用10:1之HF溶液。 15. 如申請專利範圍第14項所述之製造方法,其中該 第一氧化層對該10:1之HF溶液之蝕刻速率約爲300-350 A/min。 16. 如申請專利範圍第14項所述之製造方法,其中該 第二氧化層對該10:1之HF溶液之蝕刻速率約爲430-470 A/min 〇 I I I I I I I 華,—裝— II I 訂— 線 {請先閲讀背面之注$項再填寫本頁) 經濟部中央標準局員工消費合作社印製 太铋煤I?癆徤田Φ团因定後电f rMS、A4拔此f 川7公螫)
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TW086120045A TW379404B (en) | 1997-12-31 | 1997-12-31 | Manufacturing method of shallow trench isolation |
US09/040,912 US5981402A (en) | 1997-12-31 | 1998-03-18 | Method of fabricating shallow trench isolation |
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TW086120045A TW379404B (en) | 1997-12-31 | 1997-12-31 | Manufacturing method of shallow trench isolation |
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TW086120045A TW379404B (en) | 1997-12-31 | 1997-12-31 | Manufacturing method of shallow trench isolation |
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Families Citing this family (17)
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US6190995B1 (en) * | 1998-12-08 | 2001-02-20 | United Microelectronics Corp. | Method of fabricating shallow trench isolation structure |
US6479394B1 (en) * | 2000-05-03 | 2002-11-12 | Maxim Integrated Products, Inc. | Method of low-selective etching of dissimilar materials having interfaces at non-perpendicular angles to the etch propagation direction |
KR100500923B1 (ko) | 2000-05-23 | 2005-07-14 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
US6524929B1 (en) | 2001-02-26 | 2003-02-25 | Advanced Micro Devices, Inc. | Method for shallow trench isolation using passivation material for trench bottom liner |
US6486038B1 (en) | 2001-03-12 | 2002-11-26 | Advanced Micro Devices | Method for and device having STI using partial etch trench bottom liner |
US6521510B1 (en) | 2001-03-23 | 2003-02-18 | Advanced Micro Devices, Inc. | Method for shallow trench isolation with removal of strained island edges |
US6534379B1 (en) | 2001-03-26 | 2003-03-18 | Advanced Micro Devices, Inc. | Linerless shallow trench isolation method |
DE10131237B8 (de) * | 2001-06-28 | 2006-08-10 | Infineon Technologies Ag | Feldeffekttransistor und Verfahren zu seiner Herstellung |
US7026899B2 (en) * | 2001-12-18 | 2006-04-11 | Kionix, Inc. | Push/pull actuator for microstructures |
US6797589B2 (en) | 2001-12-18 | 2004-09-28 | Kionix, Inc. | Insulating micro-structure and method of manufacturing same |
TW554472B (en) * | 2002-09-23 | 2003-09-21 | Nanya Technology Corp | A method for forming shallow trench isolation |
US6653204B1 (en) * | 2003-02-14 | 2003-11-25 | United Microelectronics Corp. | Method of forming a shallow trench isolation structure |
KR100532503B1 (ko) * | 2004-02-03 | 2005-11-30 | 삼성전자주식회사 | 쉘로우 트렌치 소자 분리막의 형성 방법 |
US7033945B2 (en) * | 2004-06-01 | 2006-04-25 | Applied Materials | Gap filling with a composite layer |
US20060244095A1 (en) * | 2005-04-29 | 2006-11-02 | Barry Timothy M | Method of forming a shallow trench isolation structure with reduced leakage current in a semiconductor device |
US20070059900A1 (en) * | 2005-09-14 | 2007-03-15 | Chien-Hsing Lai | Multi-step depositing process |
KR100790296B1 (ko) * | 2006-12-04 | 2008-01-02 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조방법 |
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US4714520A (en) * | 1985-07-25 | 1987-12-22 | Advanced Micro Devices, Inc. | Method for filling a trench in an integrated circuit structure without producing voids |
US5328559A (en) * | 1992-09-08 | 1994-07-12 | Ic Sensors, Inc. | Groove width trimming |
US5350492A (en) * | 1992-09-18 | 1994-09-27 | Advanced Micro Devices, Inc. | Oxide removal method for improvement of subsequently grown oxides |
US5767017A (en) * | 1995-12-21 | 1998-06-16 | International Business Machines Corporation | Selective removal of vertical portions of a film |
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