TW508725B - Manufacturing method of shallow trench isolation structure - Google Patents

Manufacturing method of shallow trench isolation structure Download PDF

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Publication number
TW508725B
TW508725B TW090115051A TW90115051A TW508725B TW 508725 B TW508725 B TW 508725B TW 090115051 A TW090115051 A TW 090115051A TW 90115051 A TW90115051 A TW 90115051A TW 508725 B TW508725 B TW 508725B
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Taiwan
Prior art keywords
isolation structure
shallow trench
trench isolation
substrate
manufacturing
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TW090115051A
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Chinese (zh)
Inventor
Wan-Yi Liou
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Macronix Int Co Ltd
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Application filed by Macronix Int Co Ltd filed Critical Macronix Int Co Ltd
Priority to TW090115051A priority Critical patent/TW508725B/en
Priority to US09/900,056 priority patent/US20020197821A1/en
Priority to US10/176,969 priority patent/US20030008474A1/en
Application granted granted Critical
Publication of TW508725B publication Critical patent/TW508725B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

There is provided a manufacturing method of shallow trench isolation structure. The method comprises: providing a substrate; first, sequentially forming a pad oxide layer and a mask layer on the substrate, and defining the substrate thereby forming a trench in the substrate; next, using a high density plasma chemical vapor deposition process with a high etching/depositing ratio to form an insulating layer on the substrate for covering the substrate and filling up the trench, in which the high etching/depositing ratio of the high density plasma chemical vapor deposition process is about 0.15 to 0.6; then, removing the insulating layer outside the trench, and sequentially removing the mask layer and pad oxide layer, thereby forming a shallow trench isolation structure.

Description

7419twf.doc/006 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（/ ) 本發明是有關於一種電性絕緣(Electrically insulating)結 構的製造方法，且特別是有關於一種淺溝渠隔離（Shallow Trench Isolation，STI)結構的製造方法。 隨著半導體元件積集度的日益提高，元件的設計規則 曰益縮小，對於元件中的電性絕緣結構例如是氧化矽絕緣 層’已經無法使用區域氧化法（Local Oxidation，LOCOS)來 製造，現今應用最廣泛的方法之一，即是利用形成淺溝渠 隔離結構的方法以製造電性絕緣結構。 由於高密度電漿化學氣相沈積（High Density Plasma Chemical Vapor Deposition，HDPCVD)法具備有「蝕刻」與 「沈積」兩個機制，因此在進行沈積的同時，亦會進行將 沈積物削落的蝕刻反應，而使得高密度電漿化學氣相沈積 法具有良好的溝塡(Gap fnimg)能力，也因此將之應用於形 成淺溝渠隔離結構中的氧化矽絕緣層。 習知形成淺溝渠隔離的方法如下所述，請參照第1A 圖，首先提供一個基底100，再於基底100上依次形成墊 氧化層102、氮化矽罩幕層104。接著，以非等向性蝕刻 法去除部份的氮化矽罩幕層104、墊氧化層102以及基底 100，以形成溝渠106。 而且，在溝渠106的頂角處形成圓角結構108。形成 圓角結構108的原因係因爲習知的尖角結構在後續形成閘 氧化層時，於尖角部位的閘氧化層厚度將會不足，而造成 漏電流由此處產生。而圓角結構108可避免後續形成的閘 氧化層發生厚度不均導致漏電流的情形。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項寫本頁) Μ 裝 . 線· 508725 7 4 1 9 11 doc/006 五 ______ 經濟部智慧財產局員工消費合作社印製 B7 發明說明（2) 、 接著，請參照第1B _，以高密度電截化學氣相沈積 法於基底100上形成一層氧化矽絕緣廢U〇以覆蓋整個基 底100，並塡滿溝渠106。雖然氧化矽絕緣層110的形成係 採用溝塡能力較佳的高密度電漿化學熟相沈積法，由h在 非等向性之蝕刻步驟中，爲了達到頂角處之圓弧化(corner rcmndmg)，使得位於基底I00上之墊氧化層102會有內縮 的現象，此時氮化矽罩幕層104會如同屋簷般有了遮蔽效 應，使得後續沈積的氧化矽無法塡入而造成了缺陷點 (Weak spot)112 的形成。 接著，請參照第1C圖’以氮化矽罩幕層104爲硏磨 終止層，以化學機械硏磨（Chemical Mechanical Polishing， CMP)法去除溝渠106之外的氧化矽絕緣層110 ° 接著，請參照第1D圖’以濕式蝕刻法依序去除氮化 矽罩幕層104以及墊氧化層1〇2,以形成淺溝渠隔離結構 114。然而，在沈積氧化絕緣層110時所形成的缺陷點112 係爲無法塡入氧化矽所產生的空洞，在經由化學機械硏 磨、溼蝕刻等製程後，由於氧化絕緣層11〇在缺陷點112 位置的流失，因此所形成的淺溝渠隔離結構114在原先缺 陷點112的位置將會形成暴露出基底100頂角的凹陷116。 而且，在上述製程中，所形成的凹陷116會在淺溝渠 隔離結構的邊角部位暴露出基底100,而使得基底所 暴露的部份極易受到後續製程的傷害。 此外，後續製程所形成的元件在凹陷116處會累積電 荷，繼之在積體電路中造成元件的次臨限漏電流（sub- 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） (請先閱讀背面之注音？事填寫本頁) 裝 訂·- 508725 7419twf.doc/006 A7 五、發明說明（>) threshold leakage cuirent)現象，而使得閘氧化層的臨界啓 始電壓値降低。 因此，本發明提供一種淺溝渠隔離結構的製造方法， 能夠避免在沈積絕緣層時產生缺陷點。 本發明提供一種淺溝渠隔離結構的製造方法，能夠避 免在淺溝渠絕緣結構的邊角形成暴露出部份矽基底的凹 陷，以防止暴露的矽基底受到後續製程的傷害。 本發明提供一種淺溝渠隔離結構的製造方法，能夠避 免在淺溝渠絕緣結構的邊角形成凹陷，以避免由凹陷處產 生漏電流。 經濟部智慧財產局員工消費合作社印製 --------------裝--- (請先閱讀背面之注意事寫本頁) -丨線· 本發明提出一種淺溝渠隔離結構的製造方法，此方法 係提供一個基底，再於基底上形成墊氧化層。接著，在墊 氧化層上形成罩幕層後，定義此基底，以於基底中形成溝 渠。然後，以具有高蝕刻/沈積比的高密度電漿化學氣相沈 積製程，在基底上形成塡滿溝渠且覆蓋基底的絕緣層，其 中高密度電漿化學氣相沈積製程的蝕刻/沈積比爲0.15至 〇·6左右。由於高密度電漿化學氣相沈積製程具有高蝕刻/ 沈積比，並具有十分良好的溝塡能力，因此能夠在沈積絕 緣層時避免缺陷點的產生。其後，去除溝渠之外的絕緣層， 再依序去除罩幕層以及墊氧化層，以形成淺溝渠隔離結 構。 依照本發明的較佳實施例所述，本發明的特徵爲使用 高蝕刻/沈積比的高密度電漿化學氣相沈積法形成絕緣層， 由於高蝕刻/沈積比的高密度電漿化學氣相沈積法具有十分 5 本紙張尺度適ϋ國國家標準（CNS)A4規格（210 X 297公釐） ' 5087257419twf.doc / 006 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (/) The present invention relates to a method for manufacturing an electrically insulating structure, and in particular to a shallow trench isolation (Shallow Trench Isolation, STI) structure manufacturing method. With the increasing accumulation of semiconductor elements, the design rules of the elements have been reduced. For the electrical insulation structure in the element, such as a silicon oxide insulation layer, it is no longer possible to use local oxidation (LOCOS) to manufacture. One of the most widely used methods is to use the method of forming a shallow trench isolation structure to manufacture an electrically insulating structure. Since the High Density Plasma Chemical Vapor Deposition (HDPCVD) method has two mechanisms, "etching" and "depositing", it will also perform etching to remove the deposit while depositing The reaction makes the high-density plasma chemical vapor deposition method have good Gap fnimg capability, and therefore it is also used to form a silicon oxide insulating layer in a shallow trench isolation structure. The conventional method for forming shallow trench isolation is as follows. Referring to FIG. 1A, a substrate 100 is first provided, and then a pad oxide layer 102 and a silicon nitride mask layer 104 are formed on the substrate 100 in this order. Next, a part of the silicon nitride mask layer 104, the pad oxide layer 102, and the substrate 100 are removed by anisotropic etching to form a trench 106. Moreover, a fillet structure 108 is formed at the top corner of the trench 106. The reason for forming the rounded corner structure 108 is because the conventional sharp cornered structure will have insufficient thickness of the gate oxide layer at the sharp corner portion when the gate oxide layer is subsequently formed, and a leakage current is generated there. The rounded-corner structure 108 can prevent the leakage current caused by the uneven thickness of the gate oxide layer formed later. This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back to write this page first) Μ Packing. Line · 508725 7 4 1 9 11 doc / 006 5 ______ Ministry of Economic Affairs The Intellectual Property Bureau employee consumer cooperative printed B7 Invention Description (2). Then, please refer to Section 1B_ to form a layer of silicon oxide insulation waste U0 on the substrate 100 by high-density electrical intercept chemical vapor deposition to cover the entire substrate 100. , And filled the ditch 106. Although the silicon oxide insulating layer 110 is formed by a high-density plasma chemically mature phase deposition method with better trenching ability, in order to achieve a circular arc at the top corner in the anisotropic etching step (corner rcmndmg ), So that the pad oxide layer 102 on the substrate I00 will have a shrinkage phenomenon. At this time, the silicon nitride mask layer 104 will have a shielding effect like an eaves, so that the subsequently deposited silicon oxide cannot penetrate and cause defects. Formation of Weak spot 112. Next, referring to FIG. 1C, using the silicon nitride masking layer 104 as a honing stop layer, a chemical mechanical polishing (CMP) method is used to remove the silicon oxide insulating layer 110 outside the trench 106 °. Next, please Referring to FIG. 1D ′, the silicon nitride masking layer 104 and the pad oxide layer 102 are sequentially removed by a wet etching method to form a shallow trench isolation structure 114. However, the defect point 112 formed when the oxide insulating layer 110 is deposited is a void generated by the inability to penetrate silicon oxide. After undergoing processes such as chemical mechanical honing and wet etching, the oxide insulating layer 110 is at the defect point 112. Loss of position, so the shallow trench isolation structure 114 formed at the original defect point 112 will form a depression 116 that exposes the top corner of the substrate 100. In addition, in the above process, the formed recess 116 will expose the substrate 100 at the corners of the shallow trench isolation structure, so that the exposed portion of the substrate is extremely vulnerable to subsequent processes. In addition, the components formed in subsequent processes will accumulate charges at the recess 116, which will then cause the component's sub-threshold leakage current in the integrated circuit (sub- 4 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 χ 297 mm) (Please read the phonetic on the back? Fill in this page first) Binding ·-508725 7419twf.doc / 006 A7 V. Explanation of the invention (>) threshold leakage cuirent phenomenon, which makes the threshold of the gate oxide layer start The voltage 値 decreases. Therefore, the present invention provides a method for manufacturing a shallow trench isolation structure, which can avoid the occurrence of defect points when the insulating layer is deposited. The invention provides a method for manufacturing a shallow trench isolation structure, which can avoid the formation of depressions at the corners of the shallow trench insulation structure that expose a part of the silicon substrate, so as to prevent the exposed silicon substrate from being damaged by subsequent processes. The invention provides a method for manufacturing a shallow trench isolation structure, which can avoid the formation of depressions at the edges and corners of the shallow trench insulation structure, so as to avoid leakage current from being generated at the depressions. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -------------- Installation --- (Please read the note on the back first to write this page)-丨 Line · This invention proposes a shallow trench A method for manufacturing an isolation structure. This method provides a substrate, and then forms a pad oxide layer on the substrate. Next, after a mask layer is formed on the pad oxide layer, the substrate is defined to form a channel in the substrate. Then, a high-density plasma chemical vapor deposition process with a high etching / deposition ratio is used to form a trench-filled insulating layer on the substrate. The etching / deposition ratio of the high-density plasma chemical vapor deposition process is 0.15 to about 0.6. Since the high-density plasma chemical vapor deposition process has a high etching / deposition ratio and a very good trenching ability, it is possible to avoid the occurrence of defect points when the insulating layer is deposited. After that, the insulating layer outside the trench is removed, and then the mask layer and the pad oxide layer are sequentially removed to form a shallow trench isolation structure. According to a preferred embodiment of the present invention, the present invention is characterized in that an insulating layer is formed using a high-density plasma chemical vapor deposition method with a high etching / deposition ratio. Deposition method has 10 papers in accordance with the national standard (CNS) A4 specification (210 X 297 mm) '508725

7419twf. doc/ΟΟβ JSJ 經濟部智慧財產局員工消費合作社印製 五、發明說明（分） 良好的溝塡能力，因此即使在溝渠中的基底頂角處呈圓角 結構，亦能將絕緣材質完全塡入溝渠內而不會形成缺陷 點。 而且，由於在形成絕緣層時不會產生缺陷點，因此後 續形成淺溝渠隔離結構的製程不會形成曝露出部份基底的 凹陷處，而能夠避免凹陷處所暴露出的部份基底受到後續 製程的傷害。 更加的，由於後續形成的淺溝渠結構能夠避免形成凹 陷而能夠保持完整，因此在後續形成閘氧化層的製程中， 能夠避免在凹陷處因產生電荷的累積而從凹陷處產生漏電 流現象，進而避免閘氧化層的臨界啓始電壓値的降低。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1D圖係繪示習知一種淺溝渠隔離結構之 製造流程的剖面示意圖；以及 第2A圖至第2E圖係繪示依照本發明一較佳實施例之 一種淺溝渠隔離結構之製造流程的剖面示意圖。 圖式之標示說明： 100、200 :基底 102、202 :墊氧化層 6 (請先閱讀背面之注咅？事e -I ' I I Θ寫本頁) . 線」 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 508725 74l9twf.doc/006 pj B7 五、發明說明（f) 1〇4、204 :罩幕層 106、206 ··溝渠 108、208 :圓角結構 110、210 :絕緣層 112 :缺陷點 114、212 ··淺溝渠隔離結構 116 :凹陷 210a :氧化塡充物 實施例 第2A圖至第2E圖係繪示依照本發明一較佳實施例之 一種淺溝渠隔離結構之製造流程的剖面示意圖。 首先，請參照第2A圖，提供一基底200，並於基底200 上形成墊氧化層202,其中墊氧化層202的材質例如是氧 化矽，形成的方法例如是以熱氧化法。接著，在墊氧化層 202上形成罩幕層204。其中輩幕層2〇4的材質例如是氮化 矽，形成罩幕層204的方法例如是化學氣相沈積法。 接著，請參照第2B圖，去除部份的罩幕層204、墊氧 化層202以及基底200以形成溝渠206。其中形成溝渠206 的方法例如是在罩幕層204上形成圖案化之光阻層（未圖 示）。再以光阻層爲罩幕，以非等向性蝕刻法去除罩幕層 204、墊氧化層202，以及基底200，以形成溝渠206。且 在溝渠206的頂角處形成圓角結構208。 接著，請參照第2C圖，以具有高蝕刻/沈積比的高密 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝—— (請先閱讀背面之注意事^^!^寫本頁) H-T· ;線· 經濟部智慧財產局員工洎費合竹社矸靠 508725 7419twf.doc/006 jsj B7 五、發明說明（<) 度電漿化學氣相沈積製程，在基底200上形成一層完全塡 滿溝渠206的絕緣層210。其中絕緣層210的材質例如是 氧化矽，施行此具有高蝕刻/沈積比的高密度電漿化學氣相 沈積製程的方法，例如是以降低反應氣體中矽甲烷以及氧 氣的流量比率以及提高高頻射頻（High Frequency Radio Frequency，HFRF)的操作功率，以使高密度電槳化學氣相沈 積法方法的蝕刻/沈積比爲0.15至0.6左右來達成。其操作 條件例如是在攝氏550度至700度左右的溫度，以2700W 至 4500W 左右的低頻射頻（Low Frequency Radio Frequency， LFRF)，2700W至4000W左右的高頻射頻，通入流量爲 80sccm至150 seem左右的砂甲院、流量爲120 seem至210 seem左右的氧氣以及流量爲180 seem至280 seem左右的 氦氣作爲反應氣體源。 由於在此步驟中，形成絕緣層210所使用的高蝕刻/沈 積比的高密度電漿化學氣相沈積製程具有較高的蝕刻/沈積 比，亦即是具有較高的蝕刻能力，因此在進行絕緣層210 的沈積時，能夠將形成於溝渠206側壁頂端的沈積物削落， 而不會因側壁沈積物的存在而妨礙沈積。所以，此高蝕刻/ 沈積比的高密度電漿化學氣相沈積製程具有十分良好的溝 塡能力，所形成的絕緣層能夠將溝渠206完全塡滿。 接著，請參照第2D圖，去除溝渠206之外的絕緣層 210，以於溝渠206中形成氧化塡塞物210a。其中去除絕 緣層210的方法例如是以罩幕層204爲硏磨終止層，以化 學機械硏磨法對絕緣層210進行硏磨，直至露出罩幕層204 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） (請先閱讀背面之注意事填寫本頁) 言 r 經濟邹智慧財產局員工消費合作社印製 508725 7419twf.d〇c/〇〇e A7 B7 五、發明說明（q) 的表面。 _ 接著，請參照第2E圖，依序去除罩幕層204以及墊 氧化層202 ’以形成淺溝渠隔離結構212。其中，去除罩 幕層104的方法例如是使用熱磷酸浸蝕的濕式蝕刻法。去 除墊氧化餍102的方法例如是以氫氟酸(HF)浸蝕的濕式蝕 刻法。由於在沈積絕緣層210時，能夠完全的將溝渠206 塡滿，因此，在去除罩幕層204以及墊氧化層202以形成 淺溝渠隔離結構212時’並不會因缺陷點的存在而形成凹 陷，而能夠避免漏電流現象的產生。 綜上所述，本發明的重要特徵爲係爲使用高蝕刻/沈 積比的高密度電漿化學氣相沈積法形成絕緣層，由於高蝕 刻/沈積比的高密度電漿化學氣相沈積法，具有十分良好的 溝塡能力，因此即使溝渠具有圓角結構，亦能將絕緣材質 完全塡入溝渠內而不會形成缺陷點。 而且，由於在形成絕緣層時不會產生缺陷點，因此後 續形成淺溝渠隔離結構的製程不會形成曝露出部份基底的 凹陷處，而能夠避免凹陷處所暴露出的部份基底受到後續 製程的傷害。 更加的，由於後續形成的淺溝渠結構能夠避免形成凹 陷而能夠保持完整，因此在後續形成閘氧化層的製程中， 能夠避免在凹陷處因產生電荷的累積而從凹陷處產生漏電 流現象，進而避免閘氧化層的臨界啓始電壓値的降低。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝--- (請先閱讀背面之注意事寫本頁) . 線· 經濟部智慧財產局員工消費合作社印製 508725 7419twf.doc/006 A7 _B7 _五、發明說明（β )神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。7419twf. Doc / ΟΟβ JSJ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (min) Good gully ability, so even if the corners of the base in the trench are rounded, the insulation material can be completely Run into the trench without forming a defect. In addition, since no defect point is generated when the insulating layer is formed, the subsequent process of forming a shallow trench isolation structure will not form a recess that exposes a part of the substrate, and can prevent part of the substrate exposed from the recess from being subjected to subsequent processes. hurt. Furthermore, since the shallow trench structure formed later can avoid the formation of the depression and can be kept intact, in the subsequent process of forming the gate oxide layer, the phenomenon of leakage current from the depression due to the accumulation of charge in the depression can be avoided, and Avoid a decrease in the threshold start voltage 値 of the gate oxide. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A Figures 1 to 1D are schematic cross-sectional views showing the manufacturing process of a conventional shallow trench isolation structure; and Figures 2A to 2E are schematic views of the manufacturing process of a shallow trench isolation structure according to a preferred embodiment of the present invention. Schematic cross-section. Description of the drawing: 100, 200: substrate 102, 202: pad oxide layer 6 (please read the note on the back first? E-I 'II Θ write this page). Line "This paper's standard applies to Chinese national standards ( CNS) A4 specification (210 X 297 mm) 508725 74l9twf.doc / 006 pj B7 V. Description of the invention (f) 104, 204: Canopy layer 106, 206 ·· Ditch 108, 208: Fillet structure 110, 210: Insulating layer 112: Defect points 114, 212. · Shallow trench isolation structure 116: Depression 210a: Hafnium oxide filling. Figures 2A to 2E show a shallow trench according to a preferred embodiment of the present invention. Schematic sectional view of the manufacturing process of the isolation structure. First, referring to FIG. 2A, a substrate 200 is provided, and a pad oxide layer 202 is formed on the substrate 200. The material of the pad oxide layer 202 is, for example, silicon oxide, and the formation method is, for example, a thermal oxidation method. Next, a mask layer 204 is formed on the pad oxide layer 202. The material of the secondary curtain layer 204 is, for example, silicon nitride, and a method of forming the mask layer 204 is, for example, a chemical vapor deposition method. Next, referring to FIG. 2B, a part of the mask layer 204, the pad oxidation layer 202, and the substrate 200 are removed to form a trench 206. The method for forming the trench 206 is, for example, forming a patterned photoresist layer (not shown) on the mask layer 204. The photoresist layer is used as a mask, and the mask layer 204, the pad oxide layer 202, and the substrate 200 are removed by anisotropic etching to form a trench 206. A fillet structure 208 is formed at the top corner of the trench 206. Next, please refer to Figure 2C for the high density with high etch / deposition ratio. 7 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------- -Install—— (Please read the notes on the back ^^! ^ Write this page first) HT ·; Line · Staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, Feihe Bamboo Society, 508725 7419twf.doc / 006 jsj B7 V. Description of the invention (≪) A plasma chemical vapor deposition process forms an insulating layer 210 on the substrate 200 which completely fills the trenches 206. The material of the insulating layer 210 is, for example, silicon oxide, and a method for performing the high-density plasma chemical vapor deposition process with a high etching / deposition ratio is to reduce the flow rate of silicon methane and oxygen in the reaction gas and increase the high frequency The operating power of radio frequency (High Frequency Radio Frequency, HFRF) is achieved so that the etching / deposition ratio of the high-density electric paddle chemical vapor deposition method is about 0.15 to 0.6. The operating conditions are, for example, at a temperature of about 550 to 700 degrees Celsius, a low frequency radio frequency (LFRF) of about 2700W to 4500W, a high frequency radio frequency of about 2700W to 4000W, and an inflow of 80 sccm to 150 seem The left and right sand armored courtyards, the oxygen flow rate of 120 seem to 210 seem and the helium flow rate of 180 seem to 280 seem as the reaction gas source. In this step, the high-density plasma chemical vapor deposition process with a high etching / depositing ratio used to form the insulating layer 210 has a higher etching / depositing ratio, that is, has a higher etching ability. During the deposition of the insulating layer 210, the deposit formed on the top of the sidewall of the trench 206 can be shaved off without the presence of the sidewall deposit preventing the deposition. Therefore, the high-density plasma chemical vapor deposition process with a high etching / deposition ratio has a very good trenching capability, and the formed insulating layer can completely fill the trenches 206. Next, referring to FIG. 2D, the insulating layer 210 outside the trench 206 is removed to form a hafnium oxide plug 210a in the trench 206. The method for removing the insulating layer 210 is, for example, using the cover layer 204 as a honing end layer, and honing the insulating layer 210 by a chemical mechanical honing method until the cover layer 204 is exposed. 8 This paper size applies Chinese national standards (CNS ) A4 specification (210 x 297 mm) (please read the notes on the back to fill in this page first) Word r Economy Zou Intellectual Property Bureau employee consumer cooperative printed 508725 7419twf.d〇c / 〇〇e A7 B7 V. Description of the invention (Q) surface. _ Next, referring to FIG. 2E, the mask layer 204 and the pad oxide layer 202 'are sequentially removed to form a shallow trench isolation structure 212. The method for removing the mask layer 104 is, for example, a wet etching method using hot phosphoric acid etching. A method of removing the osmium oxide 102 is, for example, a wet etching method using a hydrofluoric acid (HF) etching method. Since the trench 206 can be completely filled when the insulating layer 210 is deposited, when the mask layer 204 and the pad oxide layer 202 are removed to form the shallow trench isolation structure 212, no depressions are formed due to the existence of defect points. , And can avoid the occurrence of leakage current phenomenon. In summary, an important feature of the present invention is that the insulating layer is formed using a high-density plasma chemical vapor deposition method with a high etching / deposition ratio. Due to the high-density plasma chemical vapor deposition method with a high etching / deposition ratio, Has a very good trenching ability, so even if the trench has a rounded structure, the insulating material can be fully inserted into the trench without forming defect points. In addition, since no defect point is generated when the insulating layer is formed, the subsequent process of forming a shallow trench isolation structure will not form a recess that exposes a part of the substrate, and can prevent part of the substrate exposed from the recess from being subjected to subsequent processes. hurt. Furthermore, since the shallow trench structure formed later can avoid the formation of the depression and can be kept intact, in the subsequent process of forming the gate oxide layer, the phenomenon of leakage current from the depression due to the accumulation of charge in the depression can be avoided, and Avoid a decrease in the threshold start voltage 値 of the gate oxide. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can apply the Chinese National Standard (CNS) A4 specification (210 X without departing from the fine paper size of the present invention). 297 mm) -------------- install --- (please read the note on the back to write this page). Printed by the Consumers Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 508725 7419twf. doc / 006 A7 _B7 _V. In the scope of the invention (β), there can be some changes and retouching. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

(請先閱讀背面之注意事X 裝—— Γ填寫本頁) · 線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）(Please read the Caution on the back first X Pack-Γ to fill in this page) · Thread · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

508725 7419twf.d〇c/〇06 六、申請專利範圍 1. 一種淺溝渠隔離結構的製造方法，該方法包括下列 步驟： 提供一基底； 在該基底上形成一墊氧化層； 在該墊氧化層上形成一罩幕層； 定義該基底，於該基底中形成〜溝渠，該溝渠之一頂 角已被圓角化；； . 以一高密度電漿化學氣相沈積製程，在該基底上形成 一絕緣層以覆蓋該基底並塡滿該溝渠，其中該高密度電漿 化學氣相沈積製程的蝕刻/沈積比爲0.15至0.6左右； 去除該溝渠之外之該絕緣層； 去除該覃幕層，以及 去除該墊氧化層，以形成淺溝渠隔離結構。 2. 如申請專利範圍第1項所述之淺溝渠隔離結構的製 造方法，其中該高密度電漿化學氣相沈積製程的操作溫度 爲攝氏550度至7〇〇度左右。 3. 如申請專利範圍第1項所述之淺溝渠隔離結構的製 造方法，其中於該高密度電漿化學氣相沈積製程中’低頻 射頻的操作功率爲2700W至4500W左右。 4. 如申請專利範圍第1項所述之淺溝渠隔離結構的製 造方法，其中於該高密度電漿化學氣相沈積製程中’高頻 射頻的操作功率爲2700W至4000W左右。 5·如申請專利範圍第1項所述之淺溝渠隔離結構的製 造方法，其中於該高密度電漿化學氣相沈積製程所使用的 -------------裝--- (請先閱讀背面之注意事寫本頁) · 線· 經濟部智慧財產局員Η消費合作社印製 本紙張尺度適用中國國家禕率（CNS)A4規格（210 X 297公釐） 508725 A8 B8 7419twf.doc/006 C8 _ D8 _ 六、申請專利範圍 一反應氣體源包括矽甲烷、氧氣以及氮氣。 6. 如申請專利範圍第5項所述之淺溝渠隔離結構的製 造方法，其中該反應氣體源的矽甲烷流量爲80 seem至150 seem左右，氧氣流量爲120 seem至210 seem左右，以及 氨氣流量爲180 seem至280 seem左右。 7. 如申請專利範圍第1項所述之淺溝渠隔離結構的製 造方法，其中該絕緣層的材質包括氧化矽。 8. —種淺溝渠隔離結構的製造方法’該方法包括下列 步驟： 提供一基底，且該基底中具有一溝渠； 以一高密度電漿化學氣相沈積製程，在該基底上形成 一絕緣層以覆蓋該基底並塡滿該溝渠，其中該高密度電漿 化學氣相沈積製程的蝕刻/沈積比爲〇·15至0.6左右；以及 去除該溝渠之外之該絕緣層，以形成淺溝渠隔離結 構。 9·如申請專利範圍第8項所述之淺溝渠隔離結構的製 造方法，在進行該高密度電漿化學氣相沈積製程之前更包 括一將該溝渠之頂角圓角化的步驟。 經濟部智慧財產局員工消費合作社印製 -------------I R i I (請先閱讀背面之注意事寫本頁) --線. 10·如申請專利範圍第8項所述之淺溝渠隔離結構的製 造方法，其中該高密度電漿化學氣相沈積製程的操作溫度 爲攝氏550度至700度左右。 11·如申請專利範圍第8項所述之淺溝渠隔離結構的製 造方法，其中於該高密度電漿化學氣相沈積製程中，低頻 射頻的操作功率爲2700W至4500W左右。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 508725 A8 B8 7419twf.doc/006 C8 D8 六、申請專利範圍 12. 如申請專利範圍第8項所述之淺溝渠隔離結構的製 造方法，其中於該高密度電漿化學氣相沈積製程中，高頻 射頻的操作功率爲2700W至4000W左右。 13. 如申請專利範圍第8項所述之淺溝渠隔離結構的製 造方法，其中於該高密度電漿化學氣相沈積製程所使用的 一反應氣體源包括砂甲院、氧氣以及氮氣。 14. 如申請專利範圍第13項所述之淺溝渠隔離結構的 製造方法，其中該反應氣體源的矽甲烷流量爲80 seem至 150 seem左右，氧氣流量爲120 seem至210 seem左右，以 及氦氣流量爲180 seem至280 seem左右。 15. 如申請專利範圍第8項所述之淺溝渠隔離結構的製 造方法，其中該絕緣層的材質包括氧化矽。 --------------裝--- (請先閱讀背面之注意事¥5^^寫本頁) •線- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）508725 7419twf.d〇c / 〇06 6. Application scope 1. A method for manufacturing a shallow trench isolation structure, the method includes the following steps: providing a substrate; forming a pad oxide layer on the substrate; and forming an oxide layer on the pad A cover layer is formed on the substrate; a substrate is defined in the substrate, a trench is formed in the substrate, and a vertex of the trench has been rounded; and a high-density plasma chemical vapor deposition process is formed on the substrate An insulating layer covers the substrate and fills the trench, wherein the etching / deposition ratio of the high-density plasma chemical vapor deposition process is about 0.15 to 0.6; removing the insulating layer outside the trench; removing the Qin curtain layer And removing the pad oxide layer to form a shallow trench isolation structure. 2. The method for manufacturing a shallow trench isolation structure as described in item 1 of the patent application scope, wherein the operating temperature of the high-density plasma chemical vapor deposition process is about 550 ° C to about 700 ° C. 3. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of patent application, wherein in the high-density plasma chemical vapor deposition process, the operating power of the 'low-frequency RF' is about 2700W to 4500W. 4. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of patent application, wherein in the high-density plasma chemical vapor deposition process, the operating power of the high-frequency radio frequency is about 2700W to 4000W. 5. The manufacturing method of a shallow trench isolation structure as described in item 1 of the scope of patent application, wherein the ------------- equipment used in the high-density plasma chemical vapor deposition process is- -(Please read the note on the back first and write this page) · Thread · Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives This paper is printed in accordance with China's National Standard (CNS) A4 (210 X 297 mm) 508725 A8 B8 7419twf.doc / 006 C8 _ D8 _ 6. Scope of patent application-The source of the reaction gas includes silicon methane, oxygen and nitrogen. 6. The method for manufacturing a shallow trench isolation structure as described in item 5 of the scope of the patent application, wherein the flow rate of the silicon gas of the reactive gas source is about 80 seem to 150 seem, the oxygen flow rate is about 120 seem to 210 seem, and ammonia The flow is around 180 seem to 280 seem. 7. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of patent application, wherein the material of the insulating layer includes silicon oxide. 8. —A manufacturing method of a shallow trench isolation structure 'The method includes the following steps: providing a substrate with a trench in the substrate; and forming an insulating layer on the substrate by a high-density plasma chemical vapor deposition process. To cover the substrate and fill the trench, wherein the etching / deposition ratio of the high-density plasma chemical vapor deposition process is about 0.15 to 0.6; and removing the insulating layer outside the trench to form a shallow trench isolation structure. 9. According to the method for manufacturing a shallow trench isolation structure described in item 8 of the scope of the patent application, before the high-density plasma chemical vapor deposition process is performed, a step of rounding the top corners of the trench is further included. Printed by the Intellectual Property Bureau's Consumer Cooperatives of the Ministry of Economic Affairs ------------- IR i I (Please read the note on the back first to write this page)-Line. 10 · If the scope of patent application is the 8th The method for manufacturing a shallow trench isolation structure according to the above item, wherein an operating temperature of the high-density plasma chemical vapor deposition process is about 550 ° C to about 700 ° C. 11. The method for manufacturing a shallow trench isolation structure according to item 8 of the scope of the patent application, wherein in the high-density plasma chemical vapor deposition process, the operating power of the low-frequency RF is about 2700W to 4500W. This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 508725 A8 B8 7419twf.doc / 006 C8 D8 6. Application for patent scope 12. The shallow trench isolation structure as described in item 8 of the scope of patent application In the manufacturing method, in the high-density plasma chemical vapor deposition process, the operating power of the high-frequency radio frequency is about 2700W to 4000W. 13. The method for manufacturing a shallow trench isolation structure as described in item 8 of the scope of the patent application, wherein a reactive gas source used in the high-density plasma chemical vapor deposition process includes sand box yard, oxygen, and nitrogen. 14. The method for manufacturing a shallow trench isolation structure as described in item 13 of the scope of the patent application, wherein the flow rate of the silicon gas of the reactive gas source is about 80 seem to 150 seem, the oxygen flow rate is about 120 seem to 210 seem, and helium The flow is around 180 seem to 280 seem. 15. The method for manufacturing a shallow trench isolation structure as described in item 8 of the scope of patent application, wherein the material of the insulating layer includes silicon oxide. -------------- Install --- (Please read the note on the back ¥ 5 ^^ write this page first) • Thread-Printed Paper Size by Employee Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs Applicable to China National Standard (CNS) A4 (210 X 297 mm)
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7327009B2 (en) 2004-10-21 2008-02-05 Taiwan Semiconductor Manufacturing Co., Ltd. Selective nitride liner formation for shallow trench isolation
CN113937053A (en) * 2020-06-29 2022-01-14 无锡华润微电子有限公司 Manufacturing method of shallow trench isolation structure and manufacturing method of semiconductor device

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US7812375B2 (en) * 2003-05-28 2010-10-12 Samsung Electronics Co., Ltd. Non-volatile memory device and method of fabricating the same
KR100843244B1 (en) 2007-04-19 2008-07-02 삼성전자주식회사 Semiconductor device and method of fabricating the same
US20110014726A1 (en) * 2009-07-20 2011-01-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming shallow trench isolation structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7327009B2 (en) 2004-10-21 2008-02-05 Taiwan Semiconductor Manufacturing Co., Ltd. Selective nitride liner formation for shallow trench isolation
CN113937053A (en) * 2020-06-29 2022-01-14 无锡华润微电子有限公司 Manufacturing method of shallow trench isolation structure and manufacturing method of semiconductor device

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