TW377501B - Method of dual damascene - Google Patents
Method of dual damasceneInfo
- Publication number
- TW377501B TW377501B TW086112919A TW86112919A TW377501B TW 377501 B TW377501 B TW 377501B TW 086112919 A TW086112919 A TW 086112919A TW 86112919 A TW86112919 A TW 86112919A TW 377501 B TW377501 B TW 377501B
- Authority
- TW
- Taiwan
- Prior art keywords
- metal
- holes
- dielectric layer
- oxide layer
- photolithography
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 4
- 230000009977 dual effect Effects 0.000 title abstract 2
- 239000002184 metal Substances 0.000 abstract 5
- 238000000206 photolithography Methods 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 abstract 1
- 238000005498 polishing Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW086112919A TW377501B (en) | 1997-09-08 | 1997-09-08 | Method of dual damascene |
US08/991,193 US6001414A (en) | 1997-09-08 | 1997-12-16 | Dual damascene processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW086112919A TW377501B (en) | 1997-09-08 | 1997-09-08 | Method of dual damascene |
Publications (1)
Publication Number | Publication Date |
---|---|
TW377501B true TW377501B (en) | 1999-12-21 |
Family
ID=21626970
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086112919A TW377501B (en) | 1997-09-08 | 1997-09-08 | Method of dual damascene |
Country Status (2)
Country | Link |
---|---|
US (1) | US6001414A (zh) |
TW (1) | TW377501B (zh) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6680248B2 (en) | 1998-06-01 | 2004-01-20 | United Microelectronics Corporation | Method of forming dual damascene structure |
TW383463B (en) | 1998-06-01 | 2000-03-01 | United Microelectronics Corp | Manufacturing method for dual damascene structure |
TW377492B (en) * | 1998-06-08 | 1999-12-21 | United Microelectronics Corp | Method of manufacturing dual damascene |
US6207545B1 (en) * | 1998-11-30 | 2001-03-27 | Taiwan Semiconductor Manufacturing Corporation | Method for forming a T-shaped plug having increased contact area |
US6093632A (en) * | 1998-12-07 | 2000-07-25 | Industrial Technology Research Institute | Modified dual damascene process |
KR100280288B1 (ko) | 1999-02-04 | 2001-01-15 | 윤종용 | 반도체 집적회로의 커패시터 제조방법 |
US6147005A (en) * | 1999-07-23 | 2000-11-14 | Worldwide Semiconductor Manufacturing Corp. | Method of forming dual damascene structures |
US6287970B1 (en) * | 1999-08-06 | 2001-09-11 | Agere Systems Inc. | Method of making a semiconductor with copper passivating film |
US7138329B2 (en) * | 2002-11-15 | 2006-11-21 | United Microelectronics Corporation | Air gap for tungsten/aluminum plug applications |
US6917109B2 (en) * | 2002-11-15 | 2005-07-12 | United Micorelectronics, Corp. | Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device |
US7449407B2 (en) * | 2002-11-15 | 2008-11-11 | United Microelectronics Corporation | Air gap for dual damascene applications |
DE102006025405B4 (de) * | 2006-05-31 | 2018-03-29 | Globalfoundries Inc. | Verfahren zur Herstellung einer Metallisierungsschicht eines Halbleiterbauelements mit unterschiedlich dicken Metallleitungen |
US7951683B1 (en) * | 2007-04-06 | 2011-05-31 | Novellus Systems, Inc | In-situ process layer using silicon-rich-oxide for etch selectivity in high AR gapfill |
US7994639B2 (en) * | 2007-07-31 | 2011-08-09 | International Business Machines Corporation | Microelectronic structure including dual damascene structure and high contrast alignment mark |
US20110084332A1 (en) * | 2009-10-08 | 2011-04-14 | Vishay General Semiconductor, Llc. | Trench termination structure |
US8227339B2 (en) * | 2009-11-02 | 2012-07-24 | International Business Machines Corporation | Creation of vias and trenches with different depths |
CN104425450B (zh) * | 2013-09-05 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | 过刻蚀率的测试结构及其形成方法、过刻蚀率的测量方法 |
KR102447671B1 (ko) | 2016-02-17 | 2022-09-27 | 삼성전자주식회사 | 배선 구조물 형성 방법 및 반도체 장치의 제조 방법 |
US10692760B2 (en) | 2017-11-30 | 2020-06-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and method for manufacturing the same |
US11600519B2 (en) * | 2019-09-16 | 2023-03-07 | International Business Machines Corporation | Skip-via proximity interconnect |
US11177166B2 (en) | 2020-04-17 | 2021-11-16 | International Business Machines Corporation | Etch stop layer removal for capacitance reduction in damascene top via integration |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2711275B1 (fr) * | 1993-10-15 | 1996-10-31 | Intel Corp | Procédé automatiquement aligné de contact en fabrication de semi-conducteurs et dispositifs produits. |
US5382545A (en) * | 1993-11-29 | 1995-01-17 | United Microelectronics Corporation | Interconnection process with self-aligned via plug |
US5635423A (en) * | 1994-10-11 | 1997-06-03 | Advanced Micro Devices, Inc. | Simplified dual damascene process for multi-level metallization and interconnection structure |
US5705430A (en) * | 1995-06-07 | 1998-01-06 | Advanced Micro Devices, Inc. | Dual damascene with a sacrificial via fill |
EP0792513A1 (en) * | 1995-09-14 | 1997-09-03 | Advanced Micro Devices, Inc. | Damascene process for reduced feature size |
US5818110A (en) * | 1996-11-22 | 1998-10-06 | International Business Machines Corporation | Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same |
-
1997
- 1997-09-08 TW TW086112919A patent/TW377501B/zh not_active IP Right Cessation
- 1997-12-16 US US08/991,193 patent/US6001414A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6001414A (en) | 1999-12-14 |
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Legal Events
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MK4A | Expiration of patent term of an invention patent |