TW377422B - Pipeline processor capable of reducing branch hazards with small-scale circuit - Google Patents
Pipeline processor capable of reducing branch hazards with small-scale circuitInfo
- Publication number
- TW377422B TW377422B TW087110470A TW87110470A TW377422B TW 377422 B TW377422 B TW 377422B TW 087110470 A TW087110470 A TW 087110470A TW 87110470 A TW87110470 A TW 87110470A TW 377422 B TW377422 B TW 377422B
- Authority
- TW
- Taiwan
- Prior art keywords
- instruction
- decoded
- branch target
- register
- sent
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
- G06F9/381—Loop buffering
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17455197 | 1997-06-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW377422B true TW377422B (en) | 1999-12-21 |
Family
ID=15980543
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW087110470A TW377422B (en) | 1997-06-30 | 1998-06-29 | Pipeline processor capable of reducing branch hazards with small-scale circuit |
Country Status (6)
Country | Link |
---|---|
US (1) | US6189092B1 (zh) |
EP (1) | EP0889395B1 (zh) |
KR (1) | KR100510030B1 (zh) |
CN (1) | CN1105350C (zh) |
DE (1) | DE69801617T2 (zh) |
TW (1) | TW377422B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7032100B1 (en) * | 1999-12-17 | 2006-04-18 | Koninklijke Philips Electronics N.V. | Simple algorithmic cryptography engine |
US6728872B1 (en) | 2000-02-04 | 2004-04-27 | International Business Machines Corporation | Method and apparatus for verifying that instructions are pipelined in correct architectural sequence |
KR100360888B1 (ko) * | 2000-08-01 | 2002-11-13 | 엘지전자 주식회사 | 피디피 티브이 모듈의 단자전압 자동 조정장치 |
FR2825810A1 (fr) * | 2001-06-06 | 2002-12-13 | Koninkl Philips Electronics Nv | Dispositif electronique a processeur pipeline utilisant un compactage de code et procede de gestion d'un tel processeur |
US7185177B2 (en) * | 2002-08-26 | 2007-02-27 | Gerald George Pechanek | Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors |
US7020769B2 (en) * | 2003-09-30 | 2006-03-28 | Starcore, Llc | Method and system for processing a loop of instructions |
US7412587B2 (en) * | 2004-02-16 | 2008-08-12 | Matsushita Electric Industrial Co., Ltd. | Parallel operation processor utilizing SIMD data transfers |
CN101156134B (zh) * | 2005-04-08 | 2010-10-06 | 松下电器产业株式会社 | 处理器及指令填充方法 |
JP2006309337A (ja) * | 2005-04-26 | 2006-11-09 | Toshiba Corp | プロセッサ及びプロセッサの命令バッファ動作方法 |
US9507600B2 (en) * | 2014-01-27 | 2016-11-29 | Texas Instruments Deutschland Gmbh | Processor loop buffer |
CN104699463B (zh) * | 2015-03-20 | 2017-05-17 | 浪潮集团有限公司 | 一种低功耗流水线的实现方法 |
GB2548604B (en) * | 2016-03-23 | 2018-03-21 | Advanced Risc Mach Ltd | Branch instruction |
CN115314161A (zh) * | 2022-08-05 | 2022-11-08 | 北京天融信网络安全技术有限公司 | 报文处理方法、装置、电子设备及存储介质 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4463422A (en) | 1982-07-12 | 1984-07-31 | Csp, Inc. | Method of processing an iterative program loop |
JPS6051948A (ja) | 1983-08-31 | 1985-03-23 | Hitachi Ltd | 情報処理装置 |
US4714994A (en) | 1985-04-30 | 1987-12-22 | International Business Machines Corp. | Instruction prefetch buffer control |
JP2708405B2 (ja) | 1986-03-03 | 1998-02-04 | 株式会社日立製作所 | コンパイラにおけるループ展開方法 |
US4933837A (en) | 1986-12-01 | 1990-06-12 | Advanced Micro Devices, Inc. | Methods and apparatus for optimizing instruction processing in computer systems employing a combination of instruction cache and high speed consecutive transfer memories |
US5522053A (en) * | 1988-02-23 | 1996-05-28 | Mitsubishi Denki Kabushiki Kaisha | Branch target and next instruction address calculation in a pipeline processor |
JP3102027B2 (ja) | 1990-11-20 | 2000-10-23 | 日本電気株式会社 | ループ制御のネスティング管理機構 |
US5450585A (en) | 1991-05-15 | 1995-09-12 | International Business Machines Corporation | Compiler with delayed conditional branching |
JP2761688B2 (ja) * | 1992-02-07 | 1998-06-04 | 三菱電機株式会社 | データ処理装置 |
GB2285154B (en) | 1993-12-24 | 1998-04-01 | Advanced Risc Mach Ltd | Branch cache |
JP2987311B2 (ja) * | 1995-05-12 | 1999-12-06 | 松下電器産業株式会社 | プロセッサ及び翻訳装置 |
-
1998
- 1998-06-18 US US09/099,299 patent/US6189092B1/en not_active Expired - Lifetime
- 1998-06-22 EP EP98304886A patent/EP0889395B1/en not_active Expired - Lifetime
- 1998-06-22 DE DE69801617T patent/DE69801617T2/de not_active Expired - Lifetime
- 1998-06-29 CN CN98103178A patent/CN1105350C/zh not_active Expired - Lifetime
- 1998-06-29 TW TW087110470A patent/TW377422B/zh active
- 1998-06-30 KR KR10-1998-0025495A patent/KR100510030B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0889395B1 (en) | 2001-09-12 |
DE69801617T2 (de) | 2002-02-07 |
KR19990007479A (ko) | 1999-01-25 |
KR100510030B1 (ko) | 2005-12-21 |
EP0889395A2 (en) | 1999-01-07 |
DE69801617D1 (de) | 2001-10-18 |
CN1206144A (zh) | 1999-01-27 |
EP0889395A3 (en) | 1999-03-24 |
US6189092B1 (en) | 2001-02-13 |
CN1105350C (zh) | 2003-04-09 |
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