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Priority to TW087110413ApriorityCriticalpatent/TW370711B/en
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Internal Circuitry In Semiconductor Integrated Circuit Devices
(AREA)
Abstract
The present invention provides an improved manufacturing process of connection in a semiconductor, which utilizes an appropriate ion implanting process to increase etching speed of a high dielectric material so as to raise the etching selectivity of the material and an etching stop layer. Thus, a thinner etching stop layer can be used to produce a damascene interconnect structure and to achieve the purpose of reducing effective capacitance and RC lag time, so that the present manufacturing process of damascene interconnect can be applied to new generation ultra-large-scale integration (ULSI).
TW087110413A1998-06-261998-06-26Method for manufacturing damascene interconnect structure
TW370711B
(en)