TW368636B - Dynamic conversion between different instruction codes by recombination of instruction elements - Google Patents

Dynamic conversion between different instruction codes by recombination of instruction elements

Info

Publication number
TW368636B
TW368636B TW086114958A TW86114958A TW368636B TW 368636 B TW368636 B TW 368636B TW 086114958 A TW086114958 A TW 086114958A TW 86114958 A TW86114958 A TW 86114958A TW 368636 B TW368636 B TW 368636B
Authority
TW
Taiwan
Prior art keywords
instruction
elements
code
recombination
initial
Prior art date
Application number
TW086114958A
Other languages
English (en)
Inventor
Rolf Hilgendorf
Hartmut Schwermer
Werner Soell
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW368636B publication Critical patent/TW368636B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
TW086114958A 1997-02-27 1997-10-13 Dynamic conversion between different instruction codes by recombination of instruction elements TW368636B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP97103233 1997-02-27

Publications (1)

Publication Number Publication Date
TW368636B true TW368636B (en) 1999-09-01

Family

ID=8226531

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086114958A TW368636B (en) 1997-02-27 1997-10-13 Dynamic conversion between different instruction codes by recombination of instruction elements

Country Status (5)

Country Link
US (1) US5925124A (zh)
JP (1) JP3180075B2 (zh)
KR (1) KR100300001B1 (zh)
DE (1) DE69841769D1 (zh)
TW (1) TW368636B (zh)

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JP2001515240A (ja) * 1997-09-01 2001-09-18 フジツウ シーメンス コンピューターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング オブジェクトコードからプログラムコードへの変換方法
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US6275927B2 (en) * 1998-09-21 2001-08-14 Advanced Micro Devices. Compressing variable-length instruction prefix bytes
US6240506B1 (en) 1998-10-02 2001-05-29 Advanced Micro Devices, Inc. Expanding instructions with variable-length operands to a fixed length
US6339822B1 (en) 1998-10-02 2002-01-15 Advanced Micro Devices, Inc. Using padded instructions in a block-oriented cache
WO2000065440A2 (en) * 1999-04-27 2000-11-02 Transitive Technologies Limited Exception handling method and apparatus for use in program code conversion
US6654869B1 (en) * 1999-10-28 2003-11-25 International Business Machines Corporation Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling
US7418580B1 (en) * 1999-12-02 2008-08-26 International Business Machines Corporation Dynamic object-level code transaction for improved performance of a computer
US6697939B1 (en) * 2000-01-06 2004-02-24 International Business Machines Corporation Basic block cache microprocessor with instruction history information
US6978233B1 (en) * 2000-03-03 2005-12-20 Unisys Corporation Method for emulating multi-processor environment
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US6732257B1 (en) * 2000-09-29 2004-05-04 Intel Corporation Reducing the length of lower level instructions by splitting and recombining an immediate
US7873814B1 (en) * 2000-12-22 2011-01-18 Lsi Corporation Microcode based hardware translator to support a multitude of processors
US6775892B2 (en) * 2000-12-22 2004-08-17 Diebolt International, Inc. Retaining ring installation tool
US6691306B1 (en) * 2000-12-22 2004-02-10 Lsi Logic Corporation Use of limited program space of general purpose processor for unlimited sequence of translated instructions
GB0202728D0 (en) * 2002-02-06 2002-03-27 Transitive Technologies Ltd Condition code flag emulation for program code conversion
US7331040B2 (en) * 2002-02-06 2008-02-12 Transitive Limted Condition code flag emulation for program code conversion
US7162617B2 (en) * 2003-02-14 2007-01-09 Fine Arc Incorporated Data processor with changeable architecture
US7219337B2 (en) * 2003-03-06 2007-05-15 Northrop Grumman Corporation Direct instructions rendering emulation computer technique
US7272700B1 (en) * 2003-12-23 2007-09-18 Altera Corporation Methods and apparatus for indirect compound VLIW execution using operand address mapping techniques
US8427490B1 (en) 2004-05-14 2013-04-23 Nvidia Corporation Validating a graphics pipeline using pre-determined schedules
JP2006092158A (ja) * 2004-09-22 2006-04-06 Toshiba Corp デジタル信号処理回路
US8624906B2 (en) * 2004-09-29 2014-01-07 Nvidia Corporation Method and system for non stalling pipeline instruction fetching from memory
US8725990B1 (en) 2004-11-15 2014-05-13 Nvidia Corporation Configurable SIMD engine with high, low and mixed precision modes
US20060155961A1 (en) * 2005-01-06 2006-07-13 International Business Machines Corporation Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor
TW200643781A (en) * 2005-06-02 2006-12-16 Rdc Semiconductor Co Ltd Conversion interface of memory device
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect
US9436468B2 (en) * 2005-11-22 2016-09-06 Intel Corporation Technique for setting a vector mask
US8683126B2 (en) * 2007-07-30 2014-03-25 Nvidia Corporation Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory
US8698819B1 (en) 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US8659601B1 (en) 2007-08-15 2014-02-25 Nvidia Corporation Program sequencer for generating indeterminant length shader programs for a graphics processor
US9024957B1 (en) 2007-08-15 2015-05-05 Nvidia Corporation Address independent shader program loading
US8411096B1 (en) 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US8780123B2 (en) * 2007-12-17 2014-07-15 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US9064333B2 (en) 2007-12-17 2015-06-23 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US7502918B1 (en) * 2008-03-28 2009-03-10 International Business Machines Corporation Method and system for data dependent performance increment and power reduction
US8681861B2 (en) * 2008-05-01 2014-03-25 Nvidia Corporation Multistandard hardware video encoder
US8923385B2 (en) * 2008-05-01 2014-12-30 Nvidia Corporation Rewind-enabled hardware encoder
US8489851B2 (en) * 2008-12-11 2013-07-16 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
GB2484489A (en) * 2010-10-12 2012-04-18 Advanced Risc Mach Ltd Instruction decoder using an instruction set identifier to determine the decode rules to use.

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US4236204A (en) * 1978-03-13 1980-11-25 Motorola, Inc. Instruction set modifier register
US4415969A (en) * 1980-02-07 1983-11-15 Intel Corporation Macroinstruction translator unit for use in a microprocessor
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EP0476722B1 (en) * 1985-04-08 1997-02-26 Hitachi, Ltd. Data processing system
US4791559A (en) * 1985-12-16 1988-12-13 Sperry Corporation High-speed instruction control for vector processors with remapping
US5115500A (en) * 1988-01-11 1992-05-19 International Business Machines Corporation Plural incompatible instruction format decode method and apparatus
GB2289354B (en) * 1994-05-03 1997-08-27 Advanced Risc Mach Ltd Multiple instruction set mapping
US5638525A (en) * 1995-02-10 1997-06-10 Intel Corporation Processor capable of executing programs that contain RISC and CISC instructions

Also Published As

Publication number Publication date
KR19980070019A (ko) 1998-10-26
DE69841769D1 (de) 2010-09-02
US5925124A (en) 1999-07-20
JP3180075B2 (ja) 2001-06-25
JPH10240524A (ja) 1998-09-11
KR100300001B1 (ko) 2001-09-03

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