TW368622B - Method and apparatus for correcting a multilevel cell memory by using error locating codes - Google Patents

Method and apparatus for correcting a multilevel cell memory by using error locating codes

Info

Publication number
TW368622B
TW368622B TW086114878A TW86114878A TW368622B TW 368622 B TW368622 B TW 368622B TW 086114878 A TW086114878 A TW 086114878A TW 86114878 A TW86114878 A TW 86114878A TW 368622 B TW368622 B TW 368622B
Authority
TW
Taiwan
Prior art keywords
multilevel cell
correcting
cell memory
error locating
charge state
Prior art date
Application number
TW086114878A
Other languages
English (en)
Inventor
Daniel H Leemann
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of TW368622B publication Critical patent/TW368622B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Detection And Correction Of Errors (AREA)
TW086114878A 1996-10-25 1997-10-09 Method and apparatus for correcting a multilevel cell memory by using error locating codes TW368622B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/740,247 US5859858A (en) 1996-10-25 1996-10-25 Method and apparatus for correcting a multilevel cell memory by using error locating codes

Publications (1)

Publication Number Publication Date
TW368622B true TW368622B (en) 1999-09-01

Family

ID=24975669

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086114878A TW368622B (en) 1996-10-25 1997-10-09 Method and apparatus for correcting a multilevel cell memory by using error locating codes

Country Status (9)

Country Link
US (1) US5859858A (zh)
JP (1) JP3982639B2 (zh)
KR (1) KR100331139B1 (zh)
CN (1) CN1113294C (zh)
AU (1) AU3911797A (zh)
DE (2) DE19782077T1 (zh)
MY (1) MY114049A (zh)
TW (1) TW368622B (zh)
WO (1) WO1998019241A1 (zh)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3165101B2 (ja) * 1998-03-05 2001-05-14 日本電気アイシーマイコンシステム株式会社 多値式半導体メモリ装置およびその不良救済方法
US6532556B1 (en) 2000-01-27 2003-03-11 Multi Level Memory Technology Data management for multi-bit-per-cell memories
US6396744B1 (en) 2000-04-25 2002-05-28 Multi Level Memory Technology Flash memory with dynamic refresh
US6856568B1 (en) 2000-04-25 2005-02-15 Multi Level Memory Technology Refresh operations that change address mappings in a non-volatile memory
US7079422B1 (en) 2000-04-25 2006-07-18 Samsung Electronics Co., Ltd. Periodic refresh operations for non-volatile multiple-bit-per-cell memory
US6466476B1 (en) 2001-01-18 2002-10-15 Multi Level Memory Technology Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell
JP4437519B2 (ja) * 2001-08-23 2010-03-24 スパンション エルエルシー 多値セルメモリ用のメモリコントローラ
US6751766B2 (en) * 2002-05-20 2004-06-15 Sandisk Corporation Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data
JP3935139B2 (ja) 2002-11-29 2007-06-20 株式会社東芝 半導体記憶装置
ITMI20022669A1 (it) * 2002-12-18 2004-06-19 Simicroelectronics S R L Struttura e metodo di rilevamento errori in un dispositivo
US7388781B2 (en) * 2006-03-06 2008-06-17 Sandisk Il Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US8848442B2 (en) * 2006-03-06 2014-09-30 Sandisk Il Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
DE102006010820A1 (de) 2006-03-07 2007-09-13 Micronas Gmbh Fehlerkorrektur- und Fehlererfassungs-Verfahren zum Auslesen von gespeicherten Informationsdaten und Speichersteuereinrichtung dafür
US7945840B2 (en) * 2007-02-12 2011-05-17 Micron Technology, Inc. Memory array error correction apparatus, systems, and methods
US7633798B2 (en) * 2007-11-21 2009-12-15 Micron Technology, Inc. M+N bit programming and M+L bit read for M bit memory cells
KR101515122B1 (ko) * 2008-02-15 2015-04-27 삼성전자주식회사 저장된 데이터의 오류에 기반하여 기준 전압을 제어하는 방법과 메모리 데이터 검출 장치
KR101434405B1 (ko) * 2008-02-20 2014-08-29 삼성전자주식회사 메모리 장치 및 메모리 데이터 읽기 방법
KR101506655B1 (ko) * 2008-05-15 2015-03-30 삼성전자주식회사 메모리 장치 및 메모리 데이터 오류 관리 방법
US20100016675A1 (en) * 2008-07-18 2010-01-21 Cohen Jason C Method of assessing a condition using sucking patterns
KR101537018B1 (ko) * 2008-10-01 2015-07-17 삼성전자주식회사 보안 메모리 인터페이스, 이를 포함하는 시스템 및 스마트카드
US8291297B2 (en) * 2008-12-18 2012-10-16 Intel Corporation Data error recovery in non-volatile memory
US8589766B2 (en) * 2010-02-24 2013-11-19 Apple Inc. Codeword remapping schemes for non-volatile memories
US8732557B2 (en) * 2011-05-31 2014-05-20 Micron Technology, Inc. Data protection across multiple memory blocks
US20150067437A1 (en) * 2013-08-30 2015-03-05 Kuljit S. Bains Apparatus, method and system for reporting dynamic random access memory error information
KR102157875B1 (ko) 2013-12-19 2020-09-22 삼성전자주식회사 불휘발성 메모리 장치 및 그것을 포함한 메모리 시스템
US9501350B2 (en) * 2014-09-22 2016-11-22 Empire Technology Development Llc Detecting unidirectional resistance drift errors in a multilevel cell of a phase change memory
US9519539B2 (en) * 2014-10-24 2016-12-13 Macronix International Co., Ltd. Monitoring data error status in a memory
US9679661B1 (en) 2016-06-28 2017-06-13 Sandisk Technologies Llc Non-volatile storage system with self-test for read performance enhancement feature setup
US9672940B1 (en) 2016-08-18 2017-06-06 Sandisk Technologies Llc Non-volatile memory with fast read process
CN114765055B (zh) * 2021-01-14 2024-05-03 长鑫存储技术有限公司 纠错系统
US11990201B2 (en) 2021-01-14 2024-05-21 Changxin Memory Technologies, Inc. Storage system
CN114765056B (zh) 2021-01-14 2024-07-12 长鑫存储技术有限公司 存储系统
EP4050608B1 (en) 2021-01-14 2023-06-28 Changxin Memory Technologies, Inc. Comparator with xor and xnor logic circuits
JP7343709B2 (ja) 2021-01-14 2023-09-12 チャンシン メモリー テクノロジーズ インコーポレイテッド 誤り訂正システム
US11599417B2 (en) 2021-01-14 2023-03-07 Changxin Memory Technologies, Inc. Error correction system

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0600137A1 (en) * 1992-11-30 1994-06-08 International Business Machines Corporation Method and apparatus for correcting errors in a memory
US5550849A (en) * 1993-05-20 1996-08-27 Ceram Incorporated Method and apparatus for detecting single or multiple bit errors instorage devices
JP3999822B2 (ja) * 1993-12-28 2007-10-31 株式会社東芝 記憶システム
US5450363A (en) * 1994-06-02 1995-09-12 Intel Corporation Gray coding for a multilevel cell memory system
EP0704854B1 (en) * 1994-09-30 1999-12-01 STMicroelectronics S.r.l. Memory device having error detection and correction function, and methods for writing and erasing the memory device
US5555250A (en) * 1994-10-14 1996-09-10 Compaq Computer Corporation Data error detection and correction system
DE69423104T2 (de) * 1994-10-31 2000-07-20 Stmicroelectronics S.R.L., Agrate Brianza Fehlernachweis- und Korrekturverfahren in einem mehrstufigen Speicher und Speicher für dieses Verfahren
US5541886A (en) * 1994-12-27 1996-07-30 Intel Corporation Method and apparatus for storing control information in multi-bit non-volatile memory arrays
US5475693A (en) * 1994-12-27 1995-12-12 Intel Corporation Error management processes for flash EEPROM memory arrays

Also Published As

Publication number Publication date
CN1113294C (zh) 2003-07-02
JP3982639B2 (ja) 2007-09-26
WO1998019241A1 (en) 1998-05-07
DE19782077T1 (de) 1999-09-23
US5859858A (en) 1999-01-12
DE19782077B4 (de) 2011-04-07
KR20000052798A (ko) 2000-08-25
MY114049A (en) 2002-07-31
AU3911797A (en) 1998-05-22
JP2001503181A (ja) 2001-03-06
KR100331139B1 (ko) 2002-04-01
CN1242088A (zh) 2000-01-19

Similar Documents

Publication Publication Date Title
TW368622B (en) Method and apparatus for correcting a multilevel cell memory by using error locating codes
TW364111B (en) Method and apparatus for correcting a multilevel cell memory by using interleaving
GB2313217B (en) Management of memory modules
TW335484B (en) Method and apparatus for reading data from a disc carrier
AU552984B2 (en) Data processing using symbol correcting code
GB2226168B (en) Error checking and correction in digital memory devices
TW328598B (en) Non-volatile memory device and refreshing method
EP1619582A3 (en) Semiconductor memory device with an ECC circuit and method of testing the memory
JPS55105900A (en) Error correction/detection system
EP0278415A3 (en) Memory system and related error detection and correction apparatus
GB8602171D0 (en) Memory refresh & parity checking circuit
KR870007502A (ko) 에러 정정 장치
EP0528234A3 (en) Data processing system for generating data bits based on stored data
CA2136058A1 (en) Error Correction Circuit
AU3015101A (en) Portable data carrier provided with access protection by rendering messages unfamiliar
EP0632293A3 (en) Procedure for correcting seismic data from a reference surface.
CA2022024A1 (en) Decoder apparatus
EP0327309A3 (en) Memory apparatus having error correction function
EP0341851A3 (en) Method and apparatus for interleaved encoding
JPS57162188A (en) Error detecting system for storage device
JPS5683154A (en) Transmission method for pcm data
JPS54152832A (en) Loading system
EP0236053A3 (en) Memory system employing a zero dc power gate array for error correction
JPS5471528A (en) Read-in system for magnetic bubble memory
JPS6426952A (en) Soft error correcting circuit

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees