TW360911B - Process for producing semiconductor device and semiconductor device - Google Patents

Process for producing semiconductor device and semiconductor device

Info

Publication number
TW360911B
TW360911B TW086101501A TW86101501A TW360911B TW 360911 B TW360911 B TW 360911B TW 086101501 A TW086101501 A TW 086101501A TW 86101501 A TW86101501 A TW 86101501A TW 360911 B TW360911 B TW 360911B
Authority
TW
Taiwan
Prior art keywords
chip
substrate
semiconductor device
wire
bonding
Prior art date
Application number
TW086101501A
Other languages
Chinese (zh)
Inventor
Osamu Horiuchi
Toshihiro Tsuboi
Hirotaka Nishizawa
Masataka Murata
Original Assignee
Hitachi Ltd
Hitachi Ulsi Sys Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Ulsi Sys Co Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW360911B publication Critical patent/TW360911B/en

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2855Environmental, reliability or burn-in testing
    • G01R31/286External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433Sockets for IC's or transistors
    • G01R1/0483Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips
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    • H01ELECTRIC ELEMENTS
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    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Environmental & Geological Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A process for producing a semiconductor device by which a high-performance highly reliable KGD can be manufactured easily and stably at a low cost. A semiconductor device manufactured by the method is also disclosed. A bare chip carrier (18) comprises a chip supporting substrate (10), an upper lid member (15), and a lower lid member (12), and a bare chip (1) is held between the member (12) and the substrate (10) through insulating sheets (14). The chip (1) is connected to the substrate (10) through a bonding aluminum wire (4) for inspection. To separate the bare chip (1) from the substrate (10) after burn-in inspection, a substrate-wide wire bonding section (4d) or its vicinity is fixed with an adhesive tape and the wire (4) is stuck to the adhesive tape by moving the chip (1) from the substrate (10). After the separation, the chip (1) is connected to a lead section by performing wire bonding using a new gold bonding wire. Then the chip (1), bonding wire, and part of the lead section are encapsulated with resin, thus completing a semiconductor device.
TW086101501A 1996-09-18 1997-02-04 Process for producing semiconductor device and semiconductor device TW360911B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP24583496 1996-09-18
PCT/JP1997/000095 WO1998012568A1 (en) 1996-09-18 1997-01-20 Process for producing semiconductor device and semiconductor device

Publications (1)

Publication Number Publication Date
TW360911B true TW360911B (en) 1999-06-11

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ID=17139549

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086101501A TW360911B (en) 1996-09-18 1997-02-04 Process for producing semiconductor device and semiconductor device

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Country Link
TW (1) TW360911B (en)
WO (1) WO1998012568A1 (en)

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JP3921163B2 (en) * 2000-09-26 2007-05-30 株式会社アドバンストシステムズジャパン Spiral contactor, manufacturing method thereof, semiconductor inspection apparatus using the same, and electronic component
US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
JP6395045B2 (en) * 2014-11-18 2018-09-26 日亜化学工業株式会社 Composite substrate, light emitting device, and manufacturing method thereof

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JPH0511019A (en) * 1991-07-04 1993-01-19 Nippon Mektron Ltd Circuit component testing method and flexible circuit board therefor
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JPH08124980A (en) * 1994-10-27 1996-05-17 Sharp Corp Burn-in method of bare chip

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