TW358962B - Method for designing an architectural system - Google Patents

Method for designing an architectural system

Info

Publication number
TW358962B
TW358962B TW086115537A TW86115537A TW358962B TW 358962 B TW358962 B TW 358962B TW 086115537 A TW086115537 A TW 086115537A TW 86115537 A TW86115537 A TW 86115537A TW 358962 B TW358962 B TW 358962B
Authority
TW
Taiwan
Prior art keywords
designing
design works
architectural system
architectural
works
Prior art date
Application number
TW086115537A
Other languages
English (en)
Inventor
Kayhan Kucukcakar
Chih-Tung Chen
Wilhelmus J Philipsen
Thomas E Tkacik
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW358962B publication Critical patent/TW358962B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
TW086115537A 1996-12-03 1997-10-21 Method for designing an architectural system TW358962B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/758,331 US5912819A (en) 1996-12-03 1996-12-03 Method for designing an architectural system

Publications (1)

Publication Number Publication Date
TW358962B true TW358962B (en) 1999-05-21

Family

ID=25051360

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086115537A TW358962B (en) 1996-12-03 1997-10-21 Method for designing an architectural system

Country Status (6)

Country Link
US (1) US5912819A (zh)
EP (1) EP0847022A3 (zh)
JP (1) JPH10171848A (zh)
KR (1) KR19980063723A (zh)
CN (1) CN1195825A (zh)
TW (1) TW358962B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6314552B1 (en) * 1998-05-18 2001-11-06 Lev A. Markov Electronic design creation through architectural exploration
US6305006B1 (en) 1998-05-18 2001-10-16 Mentor Graphics Corporation Generating candidate architectures for an architectural exploration based electronic design creation process
US6917909B1 (en) 1998-05-18 2005-07-12 Lev A. Markov Facilitating guidance provision for an architectural exploration based design creation process
JP2000123061A (ja) * 1998-10-16 2000-04-28 Matsushita Electric Ind Co Ltd 集積回路装置の設計用データベース及び集積回路装置の設計方法
GB2348970B (en) 1998-12-29 2003-10-22 Sgs Thomson Microelectronics Maintenance of a system model
JP3842489B2 (ja) * 1999-06-30 2006-11-08 株式会社東芝 回路設計装置、回路設計方法および回路設計プログラムを格納したコンピュータ読み取り可能な記録媒体
US6671857B1 (en) 1999-08-18 2003-12-30 Matsushita Electric Industrial Co., Ltd. Method of designing integrated circuit device using common parameter at different design levels, and database thereof
US7023566B2 (en) 2000-12-12 2006-04-04 Xerox Corporation Page description language on demand printing
US7302670B2 (en) * 2000-12-21 2007-11-27 Bryan Darrell Bowyer Interactive interface resource allocation in a behavioral synthesis tool
US6601230B2 (en) * 2001-04-05 2003-07-29 Agilent Technologies, Inc. Low power circuit design through judicious module selection
JP2005520238A (ja) * 2002-03-08 2005-07-07 メンター グラフィックス コーポレイション 動作合成ツールにおけるアレイ変換
CN101131713B (zh) * 2002-04-17 2012-01-11 富士通株式会社 Asic和可编程逻辑器件并行开发系统和开发方法
CN100395758C (zh) * 2002-10-14 2008-06-18 英业达股份有限公司 应用在线路布局工程上设定与激活群组化显示的方法
DE10324565A1 (de) * 2003-05-30 2004-12-30 Chipvision Desigin Systems Ag Verfahren und Vorrichtung zum Schaltungsentwurf mittels High-Level-Synthese
JP2005242812A (ja) 2004-02-27 2005-09-08 Nec Electronics Corp 回路設計支援システム、回路設計支援方法及びプログラム
CN100373388C (zh) * 2005-09-16 2008-03-05 北京中星微电子有限公司 一种快速生成逻辑电路的方法
US7735050B2 (en) 2006-02-09 2010-06-08 Henry Yu Managing and controlling the use of hardware resources on integrated circuits
US8484589B2 (en) * 2011-10-28 2013-07-09 Apple Inc. Logical repartitioning in design compiler
IT201900000625A1 (it) 2019-01-15 2020-07-15 Texa Spa Metodo di redazione di schemi elettrici

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5555201A (en) * 1990-04-06 1996-09-10 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
US5533179A (en) * 1994-12-01 1996-07-02 Motorola, Inc. Apparatus and method of modifying hardware description language statements

Also Published As

Publication number Publication date
EP0847022A2 (en) 1998-06-10
KR19980063723A (ko) 1998-10-07
US5912819A (en) 1999-06-15
CN1195825A (zh) 1998-10-14
JPH10171848A (ja) 1998-06-26
EP0847022A3 (en) 1999-11-17

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