TW357420B - Method and apparatus for packaging and testing semiconductor dice - Google Patents

Method and apparatus for packaging and testing semiconductor dice

Info

Publication number
TW357420B
TW357420B TW085103796A TW85103796A TW357420B TW 357420 B TW357420 B TW 357420B TW 085103796 A TW085103796 A TW 085103796A TW 85103796 A TW85103796 A TW 85103796A TW 357420 B TW357420 B TW 357420B
Authority
TW
Taiwan
Prior art keywords
contact
dice
packaging
package
testing
Prior art date
Application number
TW085103796A
Other languages
Chinese (zh)
Inventor
Warren M Farnworth
Alan G Wood
David R Hembree
Salman Akram
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/580,687 external-priority patent/US5815000A/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of TW357420B publication Critical patent/TW357420B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A method for packaging and testing semiconductor die, including: having the conventional testing apparatus; placing a temporary package on the dice, being of the size and the external pin identical to that of a conventional semiconductor package, which is a sort of semiconductor package selected from DIP, ZIP, LCC, SOP, QFP, TSOP, SOJ, PGA, LGA, or BGA; including the package a first contact for setting up a temporary electric contact with the second contact on the dice, being the first contact in electric contact with the external pin; placing the dice in the package, for the second contact of the dice and the first contact of the packing having electric contact; and testing the dice by means of the temporary packaging and conventional testing equipment.
TW085103796A 1995-12-29 1996-04-01 Method and apparatus for packaging and testing semiconductor dice TW357420B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/580,687 US5815000A (en) 1991-06-04 1995-12-29 Method for testing semiconductor dice with conventionally sized temporary packages

Publications (1)

Publication Number Publication Date
TW357420B true TW357420B (en) 1999-05-01

Family

ID=24322126

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085103796A TW357420B (en) 1995-12-29 1996-04-01 Method and apparatus for packaging and testing semiconductor dice

Country Status (4)

Country Link
JP (1) JP3072591B2 (en)
KR (1) KR100261942B1 (en)
SG (1) SG59989A1 (en)
TW (1) TW357420B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2785044B1 (en) * 1998-10-27 2001-01-26 Gemplus Card Int UNIVERSAL TEMPLATE FOR GEOMETRIC CHECKING OF A CARD
JP2002328150A (en) * 2001-05-01 2002-11-15 Mitsubishi Electric Corp Chip carrier
KR102152014B1 (en) * 2020-03-03 2020-09-04 제엠제코(주) Pressure type semiconductor package and method of manufacturing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451165A (en) * 1994-07-27 1995-09-19 Minnesota Mining And Manufacturing Company Temporary package for bare die test and burn-in

Also Published As

Publication number Publication date
KR100261942B1 (en) 2000-07-15
JP3072591B2 (en) 2000-07-31
KR970053690A (en) 1997-07-31
JPH09197006A (en) 1997-07-31
SG59989A1 (en) 1999-02-22

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees