SG59989A1 - Method and apparatus for packaging and testing semiconductor die - Google Patents

Method and apparatus for packaging and testing semiconductor die

Info

Publication number
SG59989A1
SG59989A1 SG1996009287A SG1996009287A SG59989A1 SG 59989 A1 SG59989 A1 SG 59989A1 SG 1996009287 A SG1996009287 A SG 1996009287A SG 1996009287 A SG1996009287 A SG 1996009287A SG 59989 A1 SG59989 A1 SG 59989A1
Authority
SG
Singapore
Prior art keywords
packaging
semiconductor die
testing semiconductor
testing
die
Prior art date
Application number
SG1996009287A
Inventor
Warren M Farnworth
Allen G Wood
David R Hembree
Salman Akram
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/580,687 external-priority patent/US5815000A/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG59989A1 publication Critical patent/SG59989A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
SG1996009287A 1995-12-29 1996-04-18 Method and apparatus for packaging and testing semiconductor die SG59989A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/580,687 US5815000A (en) 1991-06-04 1995-12-29 Method for testing semiconductor dice with conventionally sized temporary packages

Publications (1)

Publication Number Publication Date
SG59989A1 true SG59989A1 (en) 1999-02-22

Family

ID=24322126

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996009287A SG59989A1 (en) 1995-12-29 1996-04-18 Method and apparatus for packaging and testing semiconductor die

Country Status (4)

Country Link
JP (1) JP3072591B2 (en)
KR (1) KR100261942B1 (en)
SG (1) SG59989A1 (en)
TW (1) TW357420B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2785044B1 (en) * 1998-10-27 2001-01-26 Gemplus Card Int UNIVERSAL TEMPLATE FOR GEOMETRIC CHECKING OF A CARD
JP2002328150A (en) * 2001-05-01 2002-11-15 Mitsubishi Electric Corp Chip carrier
KR102152014B1 (en) * 2020-03-03 2020-09-04 제엠제코(주) Pressure type semiconductor package and method of manufacturing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451165A (en) * 1994-07-27 1995-09-19 Minnesota Mining And Manufacturing Company Temporary package for bare die test and burn-in

Also Published As

Publication number Publication date
TW357420B (en) 1999-05-01
KR970053690A (en) 1997-07-31
JP3072591B2 (en) 2000-07-31
KR100261942B1 (en) 2000-07-15
JPH09197006A (en) 1997-07-31

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