TW343318B - Register addressing in a data processing apparatus - Google Patents

Register addressing in a data processing apparatus

Info

Publication number
TW343318B
TW343318B TW085112298A TW85112298A TW343318B TW 343318 B TW343318 B TW 343318B TW 085112298 A TW085112298 A TW 085112298A TW 85112298 A TW85112298 A TW 85112298A TW 343318 B TW343318 B TW 343318B
Authority
TW
Taiwan
Prior art keywords
processing apparatus
data processing
register
register addressing
registers
Prior art date
Application number
TW085112298A
Other languages
English (en)
Inventor
York Richard
James Hedley
Symes Dominic
Biles Stuart
Original Assignee
Advanced Risc Mach Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB9619823A external-priority patent/GB2317464A/en
Application filed by Advanced Risc Mach Ltd filed Critical Advanced Risc Mach Ltd
Application granted granted Critical
Publication of TW343318B publication Critical patent/TW343318B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
TW085112298A 1996-09-23 1996-10-08 Register addressing in a data processing apparatus TW343318B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9619823A GB2317464A (en) 1996-09-23 1996-09-23 Register addressing in a data processing apparatus

Publications (1)

Publication Number Publication Date
TW343318B true TW343318B (en) 1998-10-21

Family

ID=10800360

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085112298A TW343318B (en) 1996-09-23 1996-10-08 Register addressing in a data processing apparatus

Country Status (9)

Country Link
EP (1) EP0927389B1 (zh)
JP (1) JP3645573B2 (zh)
KR (1) KR100500889B1 (zh)
CN (1) CN1103959C (zh)
DE (1) DE69718485T2 (zh)
IL (1) IL128211A0 (zh)
MY (1) MY121677A (zh)
RU (1) RU2193228C2 (zh)
TW (1) TW343318B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6950929B2 (en) * 2001-05-24 2005-09-27 Samsung Electronics Co., Ltd. Loop instruction processing using loop buffer in a data processing device having a coprocessor
CN100409187C (zh) * 2004-02-12 2008-08-06 松下电器产业株式会社 程序转换装置及程序转换方法
US8274518B2 (en) 2004-12-30 2012-09-25 Microsoft Corporation Systems and methods for virtualizing graphics subsystems
US7962731B2 (en) 2005-10-20 2011-06-14 Qualcomm Incorporated Backing store buffer for the register save engine of a stacked register file
US9710269B2 (en) * 2006-01-20 2017-07-18 Qualcomm Incorporated Early conditional selection of an operand
JP5289688B2 (ja) * 2006-07-05 2013-09-11 ルネサスエレクトロニクス株式会社 プロセッサシステム及びプロセッサシステムを動作させるオペレーティングシステムプログラムの処理方法
US8914619B2 (en) * 2010-06-22 2014-12-16 International Business Machines Corporation High-word facility for extending the number of general purpose registers available to instructions
CN102231180B (zh) * 2011-07-30 2014-05-28 张鹏 处理器指令编码可重定义的方法
WO2013101216A1 (en) * 2011-12-30 2013-07-04 Intel Corporation Cache coprocessing unit
US9588762B2 (en) * 2012-03-15 2017-03-07 International Business Machines Corporation Vector find element not equal instruction
US20130339656A1 (en) * 2012-06-15 2013-12-19 International Business Machines Corporation Compare and Replace DAT Table Entry
US10228941B2 (en) * 2013-06-28 2019-03-12 Intel Corporation Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register
US20150293767A1 (en) * 2014-04-11 2015-10-15 Fujitsu Limited Rotating register file with bit expansion support
RU2666458C1 (ru) * 2017-11-27 2018-09-07 Акционерное общество "МЦСТ" Микропроцессор
CN110350922A (zh) * 2019-07-18 2019-10-18 南京风兴科技有限公司 一种二进制编码的寻址方法及寻址器
CN115858018B (zh) * 2023-02-27 2023-05-16 珠海星云智联科技有限公司 一种嵌入式系统的自适应寄存器更新方法、设备及介质

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04293124A (ja) * 1991-03-20 1992-10-16 Hitachi Ltd データ処理プロセッサ
US5655132A (en) * 1994-08-08 1997-08-05 Rockwell International Corporation Register file with multi-tasking support

Also Published As

Publication number Publication date
KR20000048532A (ko) 2000-07-25
JP3645573B2 (ja) 2005-05-11
EP0927389A1 (en) 1999-07-07
RU2193228C2 (ru) 2002-11-20
CN1103959C (zh) 2003-03-26
EP0927389B1 (en) 2003-01-15
JP2001505679A (ja) 2001-04-24
DE69718485T2 (de) 2003-12-04
MY121677A (en) 2006-02-28
IL128211A0 (en) 1999-11-30
DE69718485D1 (de) 2003-02-20
KR100500889B1 (ko) 2005-07-14
CN1231740A (zh) 1999-10-13

Similar Documents

Publication Publication Date Title
TW343318B (en) Register addressing in a data processing apparatus
IL101623A (en) Digital signature device
JPS6436336A (en) Calculator system
EP0652510A3 (en) Software scheduled superscaler computer architecture
MY115481A (en) Recirculating register file.
TW242678B (en) Multiple instruction set mapping
EP0789297A3 (en) Data processor and method of processing data
TW374132B (en) Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory
DE2965636D1 (en) Data processing system having an integrated stack and register machine architecture
WO1998013740A3 (en) Method and apparatus for aliasing memory data in an advanced microprocessor
TW429345B (en) Processor architecture scheme having multiple sources for supplying bank address values and method therefor
EP0397433A3 (en) Image processing apparatus
JPS6437587A (en) Line generator for display system
EP0250130A3 (en) A method and apparatus for identifying the precision of an operand in a multiprecision floating-point processor
TW325552B (en) Data processing condition code flags
GB2016753A (en) Data Processing System
TW346595B (en) Single-instruction-multiple-data processing with combined scalar/vector operations
EP0377431A3 (en) Apparatus and method for address translation of non-aligned double word virtual addresses
TW228580B (en) Information processing system and method of operation
DE69428818D1 (de) Paralleler arithmetisch-logischer Prozessor für Vektor und Matrix Datenverarbeitung
CA2026225A1 (en) Apparatus for accelerating store operations in a risc computer
CA2116284A1 (en) Parallel Data Transfer Circuit
EP0292791A3 (en) Microprogrammed systems software instruction undo
TW345637B (en) Data processor with branch target address cache and method of operation a data processor has a BTAC storing a number of recently encountered fetch address-target address pairs.
JPS6435647A (en) Data processing system

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees