TW340966B - The salicide process for mask ROM - Google Patents

The salicide process for mask ROM

Info

Publication number
TW340966B
TW340966B TW086104371A TW86104371A TW340966B TW 340966 B TW340966 B TW 340966B TW 086104371 A TW086104371 A TW 086104371A TW 86104371 A TW86104371 A TW 86104371A TW 340966 B TW340966 B TW 340966B
Authority
TW
Taiwan
Prior art keywords
polysilicon
substrate
bit lines
word lines
etch
Prior art date
Application number
TW086104371A
Other languages
Chinese (zh)
Inventor
Yih-Jong Shenq
Jenn-Huei Jong
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW086104371A priority Critical patent/TW340966B/en
Priority to US08/863,626 priority patent/US5854109A/en
Application granted granted Critical
Publication of TW340966B publication Critical patent/TW340966B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Semiconductor Memories (AREA)

Abstract

A salicide process for mask ROM, it includes following steps:  Provide a Si substrate, which has serially formed gate oxide and 1st polysilicon layer;  Use lithography process to define pattern, and implant an ion, and along 1st direction to form plural bit lines on surface of Si substrate;  Etch 1st polysilicon to forming plural polysilicon strips along 1st direction;  Form 2nd polysilicon on the substrate to cover these polysilicon strips and bit lines;  Use lithography and etch techniques to define 2nd polysilicon and those polysilicon strips to form plural word lines, which are perpendicular to the 1st direction;  Form spacer on the side wall of word lines; and  Form a metal layer on the substrate and through high temperature and wet-etch processes to form salicide on those word lines and bit lines.
TW086104371A 1997-04-07 1997-04-07 The salicide process for mask ROM TW340966B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW086104371A TW340966B (en) 1997-04-07 1997-04-07 The salicide process for mask ROM
US08/863,626 US5854109A (en) 1997-04-07 1997-05-27 Silicide process for manufacturing a mask ROM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086104371A TW340966B (en) 1997-04-07 1997-04-07 The salicide process for mask ROM

Publications (1)

Publication Number Publication Date
TW340966B true TW340966B (en) 1998-09-21

Family

ID=21626519

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086104371A TW340966B (en) 1997-04-07 1997-04-07 The salicide process for mask ROM

Country Status (2)

Country Link
US (1) US5854109A (en)
TW (1) TW340966B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6372580B1 (en) * 2000-03-15 2002-04-16 Winbond Electronics Corp. Process for making mask ROM using a salicide process and mask ROM
KR100449322B1 (en) * 2001-12-26 2004-09-18 동부전자 주식회사 method for fabricating Mask ROM
TW530331B (en) * 2002-05-06 2003-05-01 Macronix Int Co Ltd Low thermal budget fabrication method for a mask read only memory device
US6720210B1 (en) * 2002-10-17 2004-04-13 Macronix International Co., Ltd Mask ROM structure and manufacturing method thereof
KR100674800B1 (en) * 2005-04-07 2007-01-26 매그나칩 반도체 유한회사 Method for manufacturing semiconductor device
CN102810516B (en) * 2011-06-02 2015-02-04 无锡华润上华半导体有限公司 ROM (read only memory) device and manufacturing method thereof
NL1042970B1 (en) * 2017-08-28 2019-06-26 Asml Netherlands Bv Memory device with predetermined start-up value

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362662A (en) * 1989-08-11 1994-11-08 Ricoh Company, Ltd. Method for producing semiconductor memory device having a planar cell structure
US5308777A (en) * 1993-07-28 1994-05-03 United Microelectronics Corporation Mask ROM process
US5453637A (en) * 1994-05-18 1995-09-26 United Microelectronics Corp. Read-only memory cell configuration with steep trenches
KR0135047B1 (en) * 1994-06-30 1998-04-20 문정환 Coding system of read only memory semiconductor device
KR100218294B1 (en) * 1995-12-30 1999-09-01 구본준 Fabrication method of a mask rom

Also Published As

Publication number Publication date
US5854109A (en) 1998-12-29

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