TW337044B - Method for manufacturing source/drain formation for flash EEPROM capable of avoiding electrical shorting - Google Patents

Method for manufacturing source/drain formation for flash EEPROM capable of avoiding electrical shorting

Info

Publication number
TW337044B
TW337044B TW084109480A TW84109480A TW337044B TW 337044 B TW337044 B TW 337044B TW 084109480 A TW084109480 A TW 084109480A TW 84109480 A TW84109480 A TW 84109480A TW 337044 B TW337044 B TW 337044B
Authority
TW
Taiwan
Prior art keywords
electrical shorting
flash eeprom
avoiding electrical
contact surface
drain formation
Prior art date
Application number
TW084109480A
Other languages
Chinese (zh)
Inventor
Richard William Gregor
Original Assignee
At & T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by At & T Corp filed Critical At & T Corp
Application granted granted Critical
Publication of TW337044B publication Critical patent/TW337044B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Method of avoiding electrical shorting on a substrate surface having pn contact from pn contact surface, where, during formation of the partition layer, a part of the pn contact surface protrudes by etching and afield oxide adhacent to the pn contact surface, including the method the following steps: performance of a drain wash implant, with the pn contact surface protrusion under the field oxide, for removal of the protrusion.
TW084109480A 1994-11-28 1995-09-08 Method for manufacturing source/drain formation for flash EEPROM capable of avoiding electrical shorting TW337044B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US34595494A 1994-11-28 1994-11-28

Publications (1)

Publication Number Publication Date
TW337044B true TW337044B (en) 1998-07-21

Family

ID=23357271

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084109480A TW337044B (en) 1994-11-28 1995-09-08 Method for manufacturing source/drain formation for flash EEPROM capable of avoiding electrical shorting

Country Status (5)

Country Link
JP (1) JPH08222650A (en)
KR (1) KR960019758A (en)
CN (1) CN1131818A (en)
DE (1) DE19543089A1 (en)
TW (1) TW337044B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1309055C (en) * 2004-03-25 2007-04-04 力晶半导体股份有限公司 Method for producing flash memory device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5671971A (en) * 1979-11-16 1981-06-15 Fujitsu Ltd Mos integrated circuit system and preparation method thereof
US4663191A (en) * 1985-10-25 1987-05-05 International Business Machines Corporation Salicide process for forming low sheet resistance doped silicon junctions
US5001082A (en) * 1989-04-12 1991-03-19 Mcnc Self-aligned salicide process for forming semiconductor devices and devices formed thereby
US5272098A (en) * 1990-11-21 1993-12-21 Texas Instruments Incorporated Vertical and lateral insulated-gate, field-effect transistors, systems and methods
US5272099A (en) * 1992-11-27 1993-12-21 Etron Technology Inc. Fabrication of transistor contacts

Also Published As

Publication number Publication date
CN1131818A (en) 1996-09-25
DE19543089A1 (en) 1996-05-30
KR960019758A (en) 1996-06-17
JPH08222650A (en) 1996-08-30

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