TW334570B - Method for arranging power lines of semiconductor memory device - Google Patents

Method for arranging power lines of semiconductor memory device

Info

Publication number
TW334570B
TW334570B TW085114784A TW85114784A TW334570B TW 334570 B TW334570 B TW 334570B TW 085114784 A TW085114784 A TW 085114784A TW 85114784 A TW85114784 A TW 85114784A TW 334570 B TW334570 B TW 334570B
Authority
TW
Taiwan
Prior art keywords
memory device
semiconductor memory
power lines
arranging power
conductive materials
Prior art date
Application number
TW085114784A
Other languages
English (en)
Inventor
Jeon Jun-Young
Park Pil-Soon
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW334570B publication Critical patent/TW334570B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
TW085114784A 1995-12-04 1996-11-29 Method for arranging power lines of semiconductor memory device TW334570B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950046426A KR970053805A (ko) 1995-12-04 1995-12-04 반도체 메모리 장치의 파워라인 배치방법

Publications (1)

Publication Number Publication Date
TW334570B true TW334570B (en) 1998-06-21

Family

ID=19437586

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085114784A TW334570B (en) 1995-12-04 1996-11-29 Method for arranging power lines of semiconductor memory device

Country Status (4)

Country Link
US (1) US5748550A (zh)
JP (1) JP3696706B2 (zh)
KR (1) KR970053805A (zh)
TW (1) TW334570B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2930025B2 (ja) * 1996-08-29 1999-08-03 日本電気株式会社 半導体装置及びその製造方法
DE19844944C1 (de) * 1998-09-30 2000-02-10 Siemens Ag Integrierte Schaltungsanordnung mit einer Konfigurations-Baugruppe
US6339541B1 (en) * 2000-06-16 2002-01-15 United Memories, Inc. Architecture for high speed memory circuit having a relatively large number of internal data lines
US6768206B2 (en) 2002-05-07 2004-07-27 Kabushiki Kaisha Toshiba Organic substrate for flip chip bonding
DE10344605B4 (de) * 2003-09-25 2008-09-18 Infineon Technologies Ag Leitbahn-Verbindungsstruktur sowie zugehöriges Herstellungsverfahren
WO2010001467A1 (ja) * 2008-07-02 2010-01-07 富士電機ホールディングス株式会社 面発光表示装置
US10468090B1 (en) 2018-09-10 2019-11-05 Micron Technology, Inc. Multilayered network of power supply lines

Also Published As

Publication number Publication date
JPH09172014A (ja) 1997-06-30
JP3696706B2 (ja) 2005-09-21
KR970053805A (ko) 1997-07-31
US5748550A (en) 1998-05-05

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees